DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/20/2023 and 10/6/2025 were filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-12 of U.S. Patent No. 12,396,181. Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations of the claims of the present invention are taught by the claims of U.S. Patent No. 12,396,181.
Present invention
U.S. Patent No. 12,396,181
1. An imaging device comprising a first layer and a second layer, wherein the first layer comprises a region overlapped with the second layer, wherein the first layer comprises a plurality of pixel circuits and a plurality of first memory circuits, wherein the second layer comprises a plurality of product-sum operation circuits and a plurality of first binarization circuits, wherein the plurality of pixel circuits and the plurality of first memory circuits each comprise a transistor including a metal oxide comprising at least indium in a channel formation region, and wherein each of the plurality of first memory circuits is configured to retain a weight coefficient to be supplied to the plurality of product-sum operation circuits.
1. An imaging device comprising a plurality of pixel blocks, wherein the plurality of pixel blocks comprise a first layer and a second layer, wherein the first layer comprises a region overlapped with the second layer, wherein each of the plurality of pixel blocks comprises: a plurality of pixel circuits and a plurality of first memory circuits in the first layer; and a plurality of product-sum operation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer, wherein the plurality of pixel circuits and the plurality of first memory circuits each comprise a transistor including a metal oxide comprising In in a channel formation region, wherein each of the plurality of first memory circuits is configured to retain a weight coefficient to be supplied to the plurality of product-sum operation circuits, wherein each of the plurality of first memory circuits comprises a memory cell, and wherein the memory cell comprises a capacitor including a ferroelectric layer.
2. The imaging device according to claim 1, wherein the plurality of product-sum operation circuits and the plurality of first binarization circuits each comprise a transistor including silicon in a channel formation region.
3. The imaging device according to claim 1, wherein the plurality of product-sum operation circuits, the plurality of first binarization circuits, and the plurality of second binarization circuits each comprise a transistor including silicon in a channel formation region.
3. The imaging device according to claim 1, wherein a number of the plurality of pixel circuits is the same as a number of the plurality of first binarization circuits.
4. The imaging device according to claim 1, wherein a number of the plurality of pixel circuits is the same as a number of the plurality of first binarization circuits.
4. The imaging device according to claim 1, wherein one of the plurality of pixel circuits is electrically connected to one of the plurality of first binarization circuits, and wherein each of the plurality of first binarization circuits is electrically connected to the plurality of product-sum operation circuits.
5. The imaging device according to claim 1, wherein one of the plurality of pixel circuits is electrically connected to one of the plurality of first binarization circuits, wherein each of the plurality of first binarization circuits is electrically connected to the plurality of product-sum operation circuits, and wherein one of the plurality of product-sum operation circuits is electrically connected to one of the plurality of second binarization circuits.
5. The imaging device according to claim 1, wherein the second layer further comprises a plurality of second binarization circuits, and wherein one of the plurality of product-sum operation circuits is electrically connected to one of the plurality of second binarization circuits.
The underlined limitation above in Claim 1 teaches “a plurality of second binarization circuits in the second layer”. The underlined limitation above in Claim 5 teaches and wherein one of the plurality of product-sum operation circuits is electrically connected to one of the plurality of second binarization circuits.
6. The imaging device according to claim 5, wherein a number of the plurality of first binarization circuits is larger than a number of the plurality of second binarization circuits.
6. The imaging device according to claim 1, wherein a number of the plurality of first binarization circuits is larger than a number of the plurality of second binarization circuits.
7. The imaging device according to claim 5, wherein a number of the plurality of product-sum operation circuits is the same as a number of the plurality of second binarization circuits.
7. The imaging device according to claim 1, wherein a number of the plurality of product-sum operation circuits is the same as a number of the plurality of second binarization circuits.
8. The imaging device according to claim 1, wherein a driver circuit of the plurality of pixel circuits and a driver circuit of the plurality of first memory circuits are provided in the second layer.
8. The imaging device according to claim 1, wherein a driver circuit of the plurality of pixel circuits and a driver circuit of the plurality of first memory circuits are provided in the second layer.
9. The imaging device according to claim 1, wherein the metal oxide further comprises zinc and gallium.
12. The imaging device according to claim 1, wherein the metal oxide further comprises Zn, and M, M being one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf.
10. The imaging device according to claim 1, wherein each of the plurality of first memory circuits comprises a memory cell, and wherein the memory cell comprises a capacitor including a ferroelectric layer.
Claim 1 above teaches “wherein each of the plurality of first memory circuits comprises a memory cell, and wherein the memory cell comprises a capacitor including a ferroelectric layer.”
Furthermore, claims 11-20 of the present invention are rejected for reasons discussed related to Claims 1-10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. USPN 10,659,707 Oka et al teaches Oka et al teaches on Column 42, Lines 49-65 and depicts in Figure 34 An imaging device comprising a plurality of pixel blocks, wherein the pixel block comprises a first layer (viewed as the combination of 501 and 502) and a second layer (503), wherein the first layer (combination of 501 and 502) comprises a region overlapped with the second layer (503), wherein the pixel block comprises: a plurality of pixel circuits (511) and a plurality of first memory circuits (523) in the first layer (combination of 501 and 502); and a signal processing circuit Column 41, Lines 22-39 and depicted as element 113 in Figure 4), a plurality of first binarization circuits (540-1), and a plurality of second binarization circuits (540-2) in the second layer (503), wherein the pixel circuit (511) and the first memory circuit (523) each comprise a transistor (CMOS transistors used) including a metal oxide in a channel formation region (CMOS), wherein the first memory circuit (523) comprises a memory cell. Oka et al teaches in the abstract performing subject detection using signal processing circuits. However, does not explicitly teach the signal processing circuit includes a plurality of product-sum operation circuits.
US 2019/0311217 Tsuji teaches an image processing system that performs subject detection similar to Oka et al and further teaches in Paragraph [0036] that it is advantageous to perform subject detection using a graphic processing unit (GPU) having a plurality of product-sum operators due to their superiority at matrix calculation.
US 2007/0007567 Yaegashi et al teaches in Paragraphs [0007 and 0008] a ferroelectric storage device (referred to hereinafter as FeRAM) that stores information in a ferroelectric film in the form of spontaneous polarization. With such FeRAMs, each memory cell transistor is formed of a single MOS transistor similarly to the case of a DRAM, except that the dielectric film in the memory cell capacitor is replaced by a ferroelectric layer and further teaches an FeRAM is advantageous for use in high-density integration.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES M HANNETT whose telephone number is (571)272-7309. The examiner can normally be reached 8:00 AM-5:00 PM Monday thru Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at 571-272-7406 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES M HANNETT/Primary Examiner, Art Unit 2639
JMH
August 26, 2026
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