DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pub. No. 2019/0156761 by Kim et al. (“Kim”).
As to claim 12, Kim discloses a driving method of an electronic device (Kim, display device 100, Figure 1) comprising:
generating a spread spectrum clock signal using a first spread spectrum method (Kim, The clock generator 200 may be a spread spectrum clock generator that spreads power of the gate clock signal CPV by changing a time period of the gate clock signal CPV as time progresses (i.e., modulating the gate clock signal CPV). Figure 1, ¶ [0042]); and
generating the spread spectrum clock signal by using a second spread spectrum method different from the first spread spectrum method after a predetermined time (Kim, the clock generator 200 may modulate the gate clock signal CPV with a first modulation pattern in a first frame period, and may downmodulate the gate clock signal CPV with a second modulation pattern different from the first modulation pattern in a second frame period. ¶ [0043]),
wherein the predetermined time is at least one frame period (Kim, the clock generator 200 may modulate the gate clock signal CPV with a first modulation pattern in a first frame period, and may downmodulate the gate clock signal CPV with a second modulation pattern different from the first modulation pattern in a second frame period. ¶ [0043]),
wherein the first spread spectrum method and the second spread spectrum method are alternately changed by at least one frame period(Kim, the clock generator 200 may modulate the gate clock signal CPV with a first modulation pattern in a first frame period, and may downmodulate the gate clock signal CPV with a second modulation pattern different from the first modulation pattern in a second frame period. ¶ [0043]).
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0156761 by Kim et al. (“Kim”) in view of U.S. Pub. No. 2013/0249609 by Taki (“Taki”).
As to claim 1, Kim discloses a display device (Kim, display device 100, Figure 1) comprising:
a display panel (Kim, display panel 110, Figure 1) wherein a plurality of pixels (Kim, pixels PX, Figure 1) and a plurality of data lines (Kim, data lines DL1,…DLn, Figure 1) are disposed (Kim, a gate driver 120 providing gate signals to the plurality of pixels PX, a data driver 130 providing data signals to the plurality of pixels PX, Figure 1, ¶ [0037]);
a timing controller (Kim, timing controller 140, Figure 1) to generate an output clock signal based on an input clock signal (Kim, the input control signal CTRL may include, but not limited to, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal and a master clock signal. The timing controller 140 may generate the gate control signal CTRL1, the data control signal CTRL2 and the digital data DAT based on the input image data IMGD and the input control signal CTRL. Figure 1, ¶ [0041]); and
a data driver to supply data signals to the data lines corresponding to the output clock signal (Kim, The data driver 130 may generate the data signals that are analog data voltages based on digital data DAT and a data control signal CTRL2 from the timing controller 140, and may apply the data signals to the data lines (e.g., DL1, DL2, ..., and DLn). Figure 1, ¶ [0040]),
wherein the timing controller is configured to change a spread spectrum method (Kim, The clock generator 200 may be a spread spectrum clock generator that spreads power of the gate clock signal CPV by changing a time period of the gate clock signal CPV as time progresses (i.e., modulating the gate clock signal CPV). Figure 1, ¶ [0042]) by at least one frame period (Kim, the clock generator 200 may modulate the gate clock signal CPV with a first modulation pattern in a first frame period, and may downmodulate the gate clock signal CPV with a second modulation pattern different from the first modulation pattern in a second frame period. ¶ [0043]),
Kim does not expressly teach
wherein the timing controller is configured to alternately change the spread spectrum method from a first spread spectrum method to a second spread spectrum method or from the second spread spectrum method to the first spread spectrum method, and
wherein the first spread spectrum method is different from the second spread spectrum method.
Taki teaches an integrated circuit device
wherein the timing controller is configured to alternately change the spread spectrum method from a first spread spectrum method to a second spread spectrum method or from the second spread spectrum method to the first spread spectrum method (Taki, FIG. 2 is a timing chart showing typical operations of the clock generator and division ratio modulation circuit in the first embodiment. The clock generator 1 operates as a center-spread SSCG. The clock generator 1 outputs the modulated clock 92 obtained by modulating a frequency df over time in the positive and negative directions about a frequency
f
0
acquired by multiplying the frequency of the reference clock 91 by a multiplication count N. As shown in the upper part of FIG. 2, the frequency of the modulated clock 92 bottoms out at time t1 and time t5 (the lowest frequency
f
0
-df) and peaks at time t3 (the highest frequency
f
0
+df). The period from time t2 to time t4 where the frequency of the modulated clock 92 is higher than
f
0
is an up-spread period, and the period from time t4 to time t6 where the frequency of the modulated clock 92 is lower than
f
0
is a down-spread period. Figure 2, ¶ [0065]), and
wherein the first spread spectrum method is different from the second spread spectrum method (Taki, FIG. 2 is a timing chart showing typical operations of the clock generator and division ratio modulation circuit in the first embodiment. The clock generator 1 operates as a center-spread SSCG. The clock generator 1 outputs the modulated clock 92 obtained by modulating a frequency df over time in the positive and negative directions about a frequency
f
0
acquired by multiplying the frequency of the reference clock 91 by a multiplication count N. As shown in the upper part of FIG. 2, the frequency of the modulated clock 92 bottoms out at time t1 and time t5 (the lowest frequency
f
0
-df) and peaks at time t3 (the highest frequency
f
0
+df). The period from time t2 to time t4 where the frequency of the modulated clock 92 is higher than
f
0
is an up-spread period, and the period from time t4 to time t6 where the frequency of the modulated clock 92 is lower than
f
0
is a down-spread period. Figure 2, ¶ [0065]). Taki teaches the different center-spread, up-spread, and down-spread timing periods.
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Kim’s spread spectrum timing signal to include Taki’s spread spectrum timing because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Kim’s spread spectrum timing signal and Taki’s spread spectrum timing perform the same general and predictable function, the predictable function being providing timing signals. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Kim’s spread spectrum timing signal by replacing it with Taki’s spread spectrum timing. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Kim, as modified by Taki, teaches the timing controller which changes the spread spectrum over time between center, up, and down spread.
As to claim 2, Kim, as modified by Taki, teaches the display device wherein the first spread spectrum method is one of an up-spread method, a down spread method, and a center-spread method (Taki, FIG. 2 is a timing chart showing typical operations of the clock generator and division ratio modulation circuit in the first embodiment. The clock generator 1 operates as a center-spread SSCG. The clock generator 1 outputs the modulated clock 92 obtained by modulating a frequency df over time in the positive and negative directions about a frequency
f
0
acquired by multiplying the frequency of the reference clock 91 by a multiplication count N. As shown in the upper part of FIG. 2, the frequency of the modulated clock 92 bottoms out at time t1 and time t5 (the lowest frequency
f
0
-df) and peaks at time t3 (the highest frequency
f
0
+df). The period from time t2 to time t4 where the frequency of the modulated clock 92 is higher than
f
0
is an up-spread period, and the period from time t4 to time t6 where the frequency of the modulated clock 92 is lower than
f
0
is a down-spread period. Figure 2, ¶ [0065]). The first spread spectrum method is center-spread. In addition, the motivation used is the same as in the rejection of claim 1.
As to claim 3, Kim, as modified by Taki, teaches the display device wherein the second spread spectrum method is another one of the up-spread method, the down spread method, and the center-spread method (Taki, FIG. 2 is a timing chart showing typical operations of the clock generator and division ratio modulation circuit in the first embodiment. The clock generator 1 operates as a center-spread SSCG. The clock generator 1 outputs the modulated clock 92 obtained by modulating a frequency df over time in the positive and negative directions about a frequency
f
0
acquired by multiplying the frequency of the reference clock 91 by a multiplication count N. As shown in the upper part of FIG. 2, the frequency of the modulated clock 92 bottoms out at time t1 and time t5 (the lowest frequency
f
0
-df) and peaks at time t3 (the highest frequency
f
0
+df). The period from time t2 to time t4 where the frequency of the modulated clock 92 is higher than
f
0
is an up-spread period, and the period from time t4 to time t6 where the frequency of the modulated clock 92 is lower than
f
0
is a down-spread period. Figure 2, ¶ [0065]). The second spread spectrum method is up-spread. In addition, the motivation used is the same as in the rejection of claim 1.
As to claim 4, Kim discloses an electronic device (Kim, display device 100, Figure 1) comprising:
a processor (Kim, GPU) to output an input clock signal (Kim, The timing controller 140 may receive input image data IMGD and an input control signal CTRL from an external host (e.g., a graphic processing unit (GPU)). Figure 1, ¶ [0041]);
pixels connected to data lines (Kim, the plurality of pixels PX is coupled to the plurality of gate lines (e.g., GL1,..., and GLm) and the plurality of data lines (e.g., DL1, DL2,..., and DLn). Figure 1, ¶ [0038]);
a timing controller (Kim, timing controller 140, Figure 1) to generate an output clock signal based on the input clock signal (Kim, the input control signal CTRL may include, but not limited to, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal and a master clock signal. The timing controller 140 may generate the gate control signal CTRL1, the data control signal CTRL2 and the digital data DAT based on the input image data IMGD and the input control signal CTRL. Figure 1, ¶ [0041]); and
a data driver to supply data signals to the data lines corresponding to the output clock signal (Kim, The data driver 130 may generate the data signals that are analog data voltages based on digital data DAT and a data control signal CTRL2 from the timing controller 140, and may apply the data signals to the data lines (e.g., DL1, DL2, ..., and DLn). Figure 1, ¶ [0040]),
wherein the timing controller is configured to change a spread spectrum method (Kim, The clock generator 200 may be a spread spectrum clock generator that spreads power of the gate clock signal CPV by changing a time period of the gate clock signal CPV as time progresses (i.e., modulating the gate clock signal CPV). Figure 1, ¶ [0042]) by at least one frame period (Kim, the clock generator 200 may modulate the gate clock signal CPV with a first modulation pattern in a first frame period, and may downmodulate the gate clock signal CPV with a second modulation pattern different from the first modulation pattern in a second frame period. ¶ [0043]),
Kim does not expressly teach
wherein the timing controller is configured to alternately change the spread spectrum method from a first spread spectrum method to a second spread spectrum method or from the second spread spectrum method to the first spread spectrum method, and
wherein the first spread spectrum method is different from the second spread spectrum method.
Taki teaches an integrated circuit device
wherein the timing controller is configured to alternately change the spread spectrum method from a first spread spectrum method to a second spread spectrum method or from the second spread spectrum method to the first spread spectrum method (Taki, FIG. 2 is a timing chart showing typical operations of the clock generator and division ratio modulation circuit in the first embodiment. The clock generator 1 operates as a center-spread SSCG. The clock generator 1 outputs the modulated clock 92 obtained by modulating a frequency df over time in the positive and negative directions about a frequency
f
0
acquired by multiplying the frequency of the reference clock 91 by a multiplication count N. As shown in the upper part of FIG. 2, the frequency of the modulated clock 92 bottoms out at time t1 and time t5 (the lowest frequency
f
0
-df) and peaks at time t3 (the highest frequency
f
0
+df). The period from time t2 to time t4 where the frequency of the modulated clock 92 is higher than
f
0
is an up-spread period, and the period from time t4 to time t6 where the frequency of the modulated clock 92 is lower than
f
0
is a down-spread period. Figure 2, ¶ [0065]), and
wherein the first spread spectrum method is different from the second spread spectrum method (Taki, FIG. 2 is a timing chart showing typical operations of the clock generator and division ratio modulation circuit in the first embodiment. The clock generator 1 operates as a center-spread SSCG. The clock generator 1 outputs the modulated clock 92 obtained by modulating a frequency df over time in the positive and negative directions about a frequency
f
0
acquired by multiplying the frequency of the reference clock 91 by a multiplication count N. As shown in the upper part of FIG. 2, the frequency of the modulated clock 92 bottoms out at time t1 and time t5 (the lowest frequency
f
0
-df) and peaks at time t3 (the highest frequency
f
0
+df). The period from time t2 to time t4 where the frequency of the modulated clock 92 is higher than
f
0
is an up-spread period, and the period from time t4 to time t6 where the frequency of the modulated clock 92 is lower than
f
0
is a down-spread period. Figure 2, ¶ [0065]). Taki teaches the different center-spread, up-spread, and down-spread timing periods.
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Kim’s spread spectrum timing signal to include Taki’s spread spectrum timing because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Kim’s spread spectrum timing signal and Taki’s spread spectrum timing perform the same general and predictable function, the predictable function being providing timing signals. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Kim’s spread spectrum timing signal by replacing it with Taki’s spread spectrum timing. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Kim, as modified by Taki, teaches the timing controller which changes the spread spectrum over time between center, up, and down spread.
As to claim 5, Kim, as modified by Taki, teaches the electronic device wherein the first spread spectrum method is one of an up-spread method, a down spread method, and a center-spread method (Taki, FIG. 2 is a timing chart showing typical operations of the clock generator and division ratio modulation circuit in the first embodiment. The clock generator 1 operates as a center-spread SSCG. The clock generator 1 outputs the modulated clock 92 obtained by modulating a frequency df over time in the positive and negative directions about a frequency
f
0
acquired by multiplying the frequency of the reference clock 91 by a multiplication count N. As shown in the upper part of FIG. 2, the frequency of the modulated clock 92 bottoms out at time t1 and time t5 (the lowest frequency
f
0
-df) and peaks at time t3 (the highest frequency
f
0
+df). The period from time t2 to time t4 where the frequency of the modulated clock 92 is higher than
f
0
is an up-spread period, and the period from time t4 to time t6 where the frequency of the modulated clock 92 is lower than
f
0
is a down-spread period. Figure 2, ¶ [0065]). The first spread spectrum method is center-spread. In addition, the motivation used is the same as in the rejection of claim 4.
As to claim 6, Kim, as modified by Taki, teaches the electronic device wherein the second spread spectrum method is another one of the up-spread method, the down spread method, and the center-spread method (Taki, FIG. 2 is a timing chart showing typical operations of the clock generator and division ratio modulation circuit in the first embodiment. The clock generator 1 operates as a center-spread SSCG. The clock generator 1 outputs the modulated clock 92 obtained by modulating a frequency df over time in the positive and negative directions about a frequency
f
0
acquired by multiplying the frequency of the reference clock 91 by a multiplication count N. As shown in the upper part of FIG. 2, the frequency of the modulated clock 92 bottoms out at time t1 and time t5 (the lowest frequency
f
0
-df) and peaks at time t3 (the highest frequency
f
0
+df). The period from time t2 to time t4 where the frequency of the modulated clock 92 is higher than
f
0
is an up-spread period, and the period from time t4 to time t6 where the frequency of the modulated clock 92 is lower than
f
0
is a down-spread period. Figure 2, ¶ [0065]). The second spread spectrum method is up-spread. In addition, the motivation used is the same as in the rejection of claim 4.
As to claim 7, Kim, as modified by Taki, teaches the electronic device wherein
the timing controller comprises a spread spectrum clock generator (Kim, The clock generator 200 may be a spread spectrum clock generator that spreads power of the gate clock signal CPV by changing a time period of the gate clock signal CPV as time progresses (i.e., modulating the gate clock signal CPV). Figure 1, ¶ [0042]), wherein the spread spectrum clock generator includes:
a phase frequency detector (Kim, phase frequency detector 220, Figure 3) that receives the input clock signal and a divided clock signal, and outputs a phase frequency signal representing a phase difference and a frequency difference between the input clock signal and the divided clock signal (Kim, The phase locked loop circuit 210 may include a phase frequency detector 220 that generates an error signal corresponding to a phase difference (and/or a frequency difference) between the input clock signal ICLK and a feedback clock signal FCLK… a programmable divider 260 that receives a divider value DV from the modulation control circuit 270a and generates the feedback clock signal FCLK by dividing the gate clock signal CPV by the received divider value DV. , Figure 3, ¶ [0052]);
a charge pump (Kim, charge pump 230, Figure 3) which receives the phase frequency signal and outputs a voltage or current corresponding to the phase frequency signal (Kim, a charge pump 230 that generates a current corresponding to the error signal, Figure 3, ¶ [0052]);
a loop filter that filters the voltage or current (Kim, a loop filter 240 that converts the current generated by the charge pump 230 into a control voltage, Figure 3, ¶ [0052]);
a profile register (Kim, modulation profile circuit 280a, Figure 3) that stores a spread spectrum method, a spread ratio, and a predetermined time interval (Kim, modulation profile circuit 280a that stores a reference modulation pattern 287a, ¶ [0053]);
a modulator (Kim, modulation control circuit 270a, Figure 3) that modulates a voltage supplied to the loop filter in response to the spread spectrum method, the spread ratio, and the predetermined time interval (Kim, an inversion circuit 290a that outputs the reference modulation pattern 287a as a first modulation pattern 292a in a first frame period and inverts the reference modulation pattern 287a to output an inverted reference modulation pattern as the second modulation pattern 294a in a second frame period. Figure 3, ¶ [0053]); and
a voltage controlled oscillator (Kim, voltage controlled oscillator 250 with inversion circuit 290a, Figure 3) that generates a frequency-modulated output clock signal using the voltage modulated by the modulator (Kim, a voltage controlled oscillator 250 that generates the gate clock signal CPV having a frequency corresponding to the control voltage, Figure 3, ¶ [0052]).
As to claim 8, Kim, as modified by Taki, teaches the electronic device wherein the spread spectrum clock generator further includes:
a divider (Kim, programmable divider 260, Figure 3) configured to generate the divided clock signal by dividing the output clock signal (Kim, a programmable divider 260 that receives a divider value DV from the modulation control circuit 270a and generates the feedback clock signal FCLK by dividing the gate clock signal CPV by the received divider value DV. Figure 3, [0052]).
As to claim 9, Kim, as modified by Taki, teaches the electronic device wherein a communication method between the processor and the timing controller is at least one of a bus, a general purpose input/output, a serial peripheral interface, a mobile industry processor interface, and an ultra path interconnect (Kim, The timing controller 140 may receive input image data IMGD and an input control signal CTRL from an external host (e.g., a graphic processing unit (GPU)). Figure 1, ¶ [0041]). The timing controller is connected to the GPU by an interface.
As to claim 11, Kim, as modified by Taki, teaches the electronic device wherein the electronic device is at least one of a portable communication device, a smartphone, a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance (Kim, The example embodiments of the inventive concepts may be applied to any display device and any electronic device including the display device. For example, the example embodiments of the inventive concepts may be applied to a television (TV), a digital TV, a 3D TV, a smart phone, a mobile phone, a tablet computer, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc. ¶ [0070]).
As to claim 13, Kim does not expressly teach the driving method wherein the first spread spectrum method is one of an up-spread method, a down spread method, and a center-spread method, and
wherein the second spread spectrum method is another one of the up-spread method, the down spread method, and the center-spread method.
Taki teaches an integrated circuit device wherein the first spread spectrum method is one of an up-spread method, a down spread method, and a center-spread method (Taki, FIG. 2 is a timing chart showing typical operations of the clock generator and division ratio modulation circuit in the first embodiment. The clock generator 1 operates as a center-spread SSCG. The clock generator 1 outputs the modulated clock 92 obtained by modulating a frequency df over time in the positive and negative directions about a frequency
f
0
acquired by multiplying the frequency of the reference clock 91 by a multiplication count N. As shown in the upper part of FIG. 2, the frequency of the modulated clock 92 bottoms out at time t1 and time t5 (the lowest frequency
f
0
-df) and peaks at time t3 (the highest frequency
f
0
+df). The period from time t2 to time t4 where the frequency of the modulated clock 92 is higher than
f
0
is an up-spread period, and the period from time t4 to time t6 where the frequency of the modulated clock 92 is lower than
f
0
is a down-spread period. Figure 2, ¶ [0065]), The first spread spectrum method is center-spread.
wherein the second spread spectrum method is another one of the up-spread method, the down spread method, and the center-spread method (Taki, FIG. 2 is a timing chart showing typical operations of the clock generator and division ratio modulation circuit in the first embodiment. The clock generator 1 operates as a center-spread SSCG. The clock generator 1 outputs the modulated clock 92 obtained by modulating a frequency df over time in the positive and negative directions about a frequency
f
0
acquired by multiplying the frequency of the reference clock 91 by a multiplication count N. As shown in the upper part of FIG. 2, the frequency of the modulated clock 92 bottoms out at time t1 and time t5 (the lowest frequency
f
0
-df) and peaks at time t3 (the highest frequency
f
0
+df). The period from time t2 to time t4 where the frequency of the modulated clock 92 is higher than
f
0
is an up-spread period, and the period from time t4 to time t6 where the frequency of the modulated clock 92 is lower than
f
0
is a down-spread period. Figure 2, ¶ [0065]). The second spread spectrum method is up-spread.
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Kim’s spread spectrum timing signal to include Taki’s spread spectrum timing because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Kim’s spread spectrum timing signal and Taki’s spread spectrum timing perform the same general and predictable function, the predictable function being providing timing signals. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Kim’s spread spectrum timing signal by replacing it with Taki’s spread spectrum timing. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Kim, as modified by Taki, teaches the timing controller which changes the spread spectrum over time between center, up, and down spread.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2019/0156761 by Kim et al. (“Kim”), in view of U.S. Pub. No. 2013/0249609 by Taki (“Taki”), and in further view of U.S. Pub. No. 2020/0098330 by Pyun et al. (“Pyun”).
As to claim 10, Kim, as modified by Taki, does not expressly teach the electronic device wherein a communication method between the timing controller and the data driver is at least one of a universal serial bus(USB), a Peripheral Component Interconnect express(PCIe), a Secure Digital Input/Output(SDIO), and a Mobile Industry Processor Interface(MIPI).
Pyun teaches a data drive and display device wherein a communication method between the timing controller and the data driver is at least one of a universal serial bus(USB), a Peripheral Component Interconnect express(PCIe), a Secure Digital Input/Output(SDIO), and a Mobile Industry Processor Interface(MIPI) (Pyun, The interface method between the timing controller 120 and the data driving circuits 141 to 144 may be one of the high-speed serial interface methods, such as an universal serial interface (USI), a mobile industry processor interface (MIPI), a mobile display digital interface (MDDI), and an inter-integrated circuit (
I
2
C
). Figure 1, ¶ [0052]).
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Kim’s timing control to data driver connection to include Pyun’s MIPI connection because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Kim’s timing control to data driver connection and Pyun’s MIPI connection perform the same general and predictable function, the predictable function being providing a high speed data connection between display device components. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Kim’s timing control to data driver connection by replacing it with Pyun’s MIPI connection. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Kim, as modified by Taki and Pyun, teaches the MIPI connection between the timing controller and the data driver.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-8 and 12-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12,361,863. Although the claims at issue are not identical, they are not patentably distinct from each other because the parent patent recites nearly the same limitations with minor differences or further detail than the claims of the instant application and is therefore an obvious variant thereof.
Instant application (Claim 1)
Parent Patent No. 12,361,863 (Claim 7)
A display device comprising:
A display device comprising:
a display panel wherein a plurality of pixels and a plurality of data lines are disposed;
pixels disposed to be connected to scan lines and data lines;
a timing controller to generate an output clock signal based on an input clock signal; and
a timing controller for controlling the data driver;
a data driver to supply data signals to the data lines corresponding to the output clock signal,
a data driver for supplying data signals to the data lines;
wherein the timing controller is configured to change a spread spectrum method by at least one frame period,
a spread spectrum clock generator included in the timing controller and for generating an output clock signal, wherein
wherein the timing controller is configured to alternately change the spread spectrum method from a first spread spectrum method to a second spread spectrum method or from the second spread spectrum method to the first spread spectrum method, and
wherein the first spread spectrum method is different from the second spread spectrum method.
the spread spectrum clock generator generates the output clock signal at a predetermined time interval using a different spread spectrum method at the predetermined time interval, wherein the spread spectrum clock generator alternately changes the spread spectrum method from an up-spread method to a down-spread method or from the down-spread method to the up-spread method based on at least one frame period.
Instant application (Claim 4)
Parent Patent No. 12,361,863 (Claim 7)
An electronic device comprising:
A display device comprising:
a processor to output an input clock signal;
a processor, (Claim 1)
pixels connected to data lines;
pixels disposed to be connected to scan lines and data lines;
a timing controller to generate an output clock signal based on the input clock signal; and
a timing controller for controlling the data driver;
a data driver to supply data signals to the data lines corresponding to the output clock signal,
a data driver for supplying data signals to the data lines;
wherein the timing controller is configured to change a spread spectrum method by at least one frame period,
a spread spectrum clock generator included in the timing controller and for generating an output clock signal, wherein
herein the timing controller is configured to alternately change the spread spectrum method from a first spread spectrum method to a second spread spectrum method or from the second spread spectrum method to the first spread spectrum method, and
wherein the first spread spectrum method is different from the second spread spectrum method.
the spread spectrum clock generator generates the output clock signal at a predetermined time interval using a different spread spectrum method at the predetermined time interval, wherein the spread spectrum clock generator alternately changes the spread spectrum method from an up-spread method to a down-spread method or from the down-spread method to the up-spread method based on at least one frame period.
Instant application (Claim 12)
Parent Patent No. 12,361,863 (Claim 13)
A driving method of an electronic device comprising:
A driving method of a display device generating a spread spectrum clock signal for data transmission comprising:
generating a spread spectrum clock signal using a first spread spectrum method; and
generating the spread spectrum clock signal using a first spread spectrum method;
generating the spread spectrum clock signal by using a second spread spectrum method different from the first spread spectrum method after a predetermined time,
wherein the predetermined time is at least one frame period,
generating the spread spectrum clock signal by using a second spread spectrum method different from the first spread spectrum method after a predetermined time, wherein the predetermined time is at least one frame period,
wherein the first spread spectrum method and the second spread spectrum method are alternately changed by at least one frame period.
wherein the first spread spectrum method and the second spread spectrum method are alternately changed based on at least one frame period.
As to dependent claims 2, 3, 5-8 and 13, these claims are similarly rejected based on claims 1-14 of the parent Patent No. 12,361,863.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Pub. No. 2018/0269924 by Kaji et al. teaches a spread spectrum clock generator with upper-spread, center-spread, and down-spread modes.
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/BRENT D CASTIAUX/Primary Examiner, Art Unit 2623
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