DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/10/2025 and 04/29/2026 have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-2, 8, 11, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zheng (US Patent Publication No. 2021/0407409)
With reference to claims 1, 11, and 20, Zheng discloses an electronic display device (300) comprising:
a display panel comprising a pixel (330); and a driver (310/320) which outputs a driving signal to the pixel (330) (see paragraphs 121-124; Figs. 4A-B), wherein
the driver comprising (see paragraph 122; Fig. 4):
a first gate emission signal generator (320) which generates a first driving signal (Eout) (see paragraphs 121-122; Figs. 4A-B);
a second gate emission signal generator (310) which generates a second driving signal (Gout) different from the first driving signal (Eout) and has a circuit structure substantially identical to a circuit structure of the first gate emission signal generator (320) (see paragraphs 121-122; Figs. 4A-B);
a clock line (CK1-2) which is disposed between the first gate emission signal generator (320) and the second gate emission signal generator (310) and outputs a clock signal (see paragraphs 136-137, 141; Fig. 4B); and
a low voltage line (VGL) which is disposed between the first gate emission signal generator (320) and the second gate emission signal generator (310) and outputs a first low gate voltage (see paragraph 139, 141; Fig. 4B),
wherein the first gate emission signal generator (320) is electrically connected to the clock line (CK1-2) and the low voltage line (VHL) (see paragraph 139, 141; Fig. 4B), and
the second gate emission signal generator (310) is electrically connected to the clock line (CLK1-2) and the low voltage line (VHL) to which the first gate emission signal generator (320) is electrically connected (see paragraph 139, 141; Fig. 4B).
With reference to claim 2, Zheng discloses the driver of claim 1, and further discloses wherein the driver comprises a plurality of stages disposed in a direction (see paragraph 141, Fig. 4B), the first gate emission signal generator (320) comprises a plurality of first gate emission signal generators (STVEn) (see paragraphs 143-144; Fig. 4B); the second gate emission signal generator (310) comprises a plurality of second gate emission signal generators (STVGn) (see paragraphs 141-142; Fig. 4B); each of the plurality of stages comprises: a corresponding first gate emission signal generator (STVE1) among the plurality of first gate emission signal generators (STVn); and a corresponding second gate emission signal generator (STVG1) among the plurality of second gate emission signal generators (STVGn), and the clock line (CK1-2) comprises: a first clock line (CK1) electrically connected to stages of the plurality of stages (STV),which are disposed at odd-numbered rows (see paragraphs 139-141; Fig. 4B); and a second clock line (CK2) electrically connected to stages of the plurality of stages (STV), which are disposed at even-numbered rows (see paragraphs 139-141; Fig. 4B).
With reference to claim 8, Zheng discloses the driver of claim 1, and further discloses wherein the first gate emission signal generator (320) and the second gate emission signal generator (310) are line-symmetrical with respect to the low voltage line (see Fig. 4B).
With reference to claim 17, Zheng discloses the driver of claim 11, and further discloses wherein the pixel (100) comprises: a light-emitting element which emits light (see paragraph 66; Fig. 1B); a first pixel transistor (T.sub.D) which provides a driving current to the light-emitting element (see paragraph 82; Fig. 1B); a second pixel transistor (T3) which provides a data voltage to the first pixel transistor (T.sub.D) in response to a write gate signal (see paragraph 61; Fig. 1B); a third pixel transistor (T5) which diode-connects the first pixel transistor (T.sub.D) in response to a compensation gate signal (see paragraph 62; Fig. 1B); a fourth pixel transistor (T4) which provides a first initialization voltage to a gate electrode of the first pixel transistor in response to an initialization gate signal (see paragraph 52; Fig. 1B); a fifth pixel transistor (T5) which provides a driving voltage to the first pixel transistor in response to an emission signal (see paragraph 62); a sixth pixel transistor (T7) which electrically connects the first pixel transistor (T.sub.D) and the light-emitting element in response to the emission signal (see paragraph 69; Fig. 1B); and a seventh pixel transistor (T6) which provides a second initialization voltage to a first electrode of the light-emitting element in response to a bias gate signal (see paragraph 53).
With reference to claim 18, Zheng discloses the driver of claim 17, and further discloses wherein the first driving signal is a driving signal selected from a group consisting of the emission signal, the compensation gate signal, the initialization gate signal, and the bias gate signal, and the second driving signal is different from the first driving signal and is a driving signal selected from the group consisting of the emission signal, the compensation gate signal, the initialization gate signal, and the bias gate signal (see paragraphs 40-41, 43-45, 78; Figs. 1A-B).
With reference to claim 19, Zheng discloses the driver of claim 11, and further discloses wherein the driver comprises: a first driver (320); and a second driver (210) spaced apart from the first driver (320) (see Fig. 4B), the first gate emission signal generator comprises a plurality of first gate emission signal generators (STVE), the second gate emission signal generator comprises a plurality of second gate emission signal generators (STVG), each of the first driver and the second driver comprises: a corresponding first gate emission signal generator (STVE) among the plurality of first gate emission signal generators; and a corresponding second gate emission signal generator among the plurality of second gate emission signal generators (STVG), the first driving signal of the first driver is the emission signal (En), the second driving signal of the first driver is a gate signal selected from a group consisting of the compensation gate signal, the initialization gate signal, and the bias gate signal (see paragraphs 40-41, 43-45, 78; Figs. 1A-B), the first driving signal of the second driver is different from the second driving signal of the first driver and is a gate signal selected from the group consisting of the compensation gate signal, the initialization gate signal, and the bias gate signal, and the second driving signal of the second driver is a gate signal different from the second driving signal of the first driver and the first driving signal of the second driver (see paragraphs 40-41, 43-45, 78; Figs. 1A-B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Zheng as applied to claim 2 above, and further in view of Zhang et al. (US Patent Publication 2022/0301497; hereinafter Zhang).
With reference to claim 3, Zheng discloses the driver of claim 2, however fails to disclose the positioning of the voltage line in reference to the clock lines as recited.
Zhang discloses a display apparatus including a pixel driving circuit including a wherein the low voltage line (VGL) is disposed between the first clock line (CK) and the second clock line (XCK) in a plan view (see paragraph 68; Fig. 8).
Therefore it would have been obvious to one of ordinary skill in the art to allow the configuration of the voltage line and clock lines similar to that which is taught by Zhang to be carried out in a device similar to that which is taught by Zheng to thereby provide an alternative layout configuration (see Zhang; Figs. 5, 8, 11).
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng as applied to claim 2 or 11 above, and further in view of Seo et al. (US Patent Publication No. 2023/0127759; hereinafter Seo).
With reference to claims 4 and 12, Zheng discloses the driver of claim 2 or 11, however fails to disclose positions of the voltage line and clock lines within the layers of the display panel as recited.
Seo discloses a GIP display panel wherein the low voltage line, the first clock line, and the second clock line are disposed in a same layer (see paragraphs 127, 139; Fig. 7-8).
Therefore it would have been obvious to one of ordinary skill in the art to allow the configuration of the voltage line and clock lines similar to that which is taught by Seo to be carried out in a device similar to that which is taught by Zheng to thereby provide an alternative layout configuration (see Seo; Figs. 7-8).
Claim 5-7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng as applied to claim 2 above, and further in view of
Kim et al. (US Patent Publication No. 2006/0056267; hereinafter Kim).
With reference to claim 5, Zheng discloses the driver of claim 2, however fails to disclose positions of the voltage line and clock lines within the layers of the display panel as recited.
Kim discloses a display apparatus wherein the low voltage line (SL4) is disposed in a different layer from the first clock line (CL1) and the second clock line (CL2) (see paragraphs 52-53; Fig. 3).
Therefore it would have been obvious to one of ordinary skill in the art to allow the configuration of the voltage line and clock lines similar to that which is taught by Kim to be carried out in a device similar to that which is taught by Zheng to thereby provide an alternative layout configuration (see Kim; Figs. 3, 7).
With reference to claim 6, Zheng and Kim discloses the driver of claim 5, wherein Kim further discloses wherein the low voltage line (SL4) at least partially overlaps the first clock line (CL1) or the second clock line in a plan view (see Figs. 2-3, 7, 10).
With reference to claim 7, Zheng and Kim discloses the driver of claim 5, wherein Kim further discloses wherein the low voltage line is disposed under the first clock line and the second clock line (see Figs. 3, 7).
With reference to claim 13, Zheng discloses the driver of claim 11, however fails to disclose positions of the voltage line and clock lines as recited.
Kim wherein the low voltage line (SL4) and the clock line (CL1) are disposed in different layers, and the low voltage line at least partially overlaps the clock line in a plan view (see Figs. 2-3, 7, 10).
Therefore it would have been obvious to one of ordinary skill in the art to allow the configuration of the voltage line and clock lines similar to that which is taught by Kim to be carried out in a device similar to that which is taught by Zheng to thereby provide an alternative layout configuration (see Kim; Figs. 3, 7).
Allowable Subject Matter
Claims 9-10 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LI et al. (US2023/0065254) discloses a display a panel and a display device having a plurality of metal layers consisting of an electrode layer of the pixel circuit in the display region (see paragraphs 84-108; Figs. 1-22).
Conclusion
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/ADE/Examiner, Art Unit 2625 /WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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