Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 08/03/2026 have been fully considered but they are not persuasive.
Applicant argued that the present US Patent Application No. 19/268033 and Kim (US Patent 11,610,541, granted 03/21/2023) were not later than the effective filing date (September 20, 2022) of the claimed invention in the present U.S Patent Application No. 19/268,033, which is not correct. The effective filing date of the Application 19/323,682 is April 12, 2023, which is later than the US Patent Application No. 19/268033 and Kim (US Patent 11,610,541, granted 03/21/2023 unless an English translation of the Application 18/133,593.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 11,610,541).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claims 1, 8, 10, Kim et al., figs. 2, 6-8, discloses a pixel comprising: a light emitting element (LD); a first transistor including a gate electrode, a first electrode and a second electrode (T1); a second transistor configured to transfer a voltage corresponding to a data voltage to the gate electrode of the first transistor in response to a first scan signal having a turn-on level (T2); a first emission control transistor configured to switch an electrical connection between a first power line and the first electrode of the first transistor in response to a first emission control signal, wherein a first power voltage is applied to the first power emission control signal line (T6, The sixth transistor T6 may be connected between the first power VDD and the first electrode of the first transistor T1 (or a fifth node N5). The sixth transistor T6 may include a gate electrode receiving the emission control signal. For example, the gate electrode of the sixth transistor T6 may be connected to the emission control line ELi to receive the emission control signal. The sixth transistor T6 may be turned off when the emission control signal is supplied to the emission control line ELi, and may be turned on in other cases. The sixth transistor T6 in a turned-on state may connect the first electrode of the first transistor T1 to the first power VDD); a second emission control transistor configured to switch an electrical connection between the second electrode of the first transistor and the light emitting element in response to a second emission control signal (The eighth transistor T8 may be connected between the light emitting element LD (or the fourth node N4) and the anode initialization power Vaint. The eighth transistor T8 may include a gate electrode receiving the emission control signal. For example, the gate electrode of the eighth transistor T8 may be connected to the emission control line ELi to receive the emission control signal. The eighth transistor T8 may be turned on when the emission control signal is supplied to the emission control line ELI, to electrically connect the anode initialization power Vaint and the fourth node N4. Accordingly, a voltage of the fourth node N4 (or the anode of the light emitting element LD) may be initialized to the voltage of the anode initialization power Vaint); and a third emission control transistor configured to apply a voltage to the first electrode of the first transistor in response to a third emission control signal The ninth transistor T9 may be connected between the first electrode of the first transistor T1 (or a fifth node N5) and the bias power Vbs. The ninth transistor T9 may include a gate electrode receiving the emission control signal. For example, the gate electrode of the ninth transistor T9 may be connected to the emission control line ELi to receive the emission control signal. The ninth transistor T9 may be turned on when the emission control signal is supplied to the emission control line ELi, to electrically connect the fifth node N5 and the bias power Vbs.
Regarding claim 2, Kim et al., figs. 2, 6-8, discloses the pixel according to claim 1, wherein in a first period, the first emission control signal has a turn-on level, and the second emission control signal has a turn-off level (The eighth transistor T8 may be connected between the light emitting element LD (or the fourth node N4) and the anode initialization power Vaint. The eighth transistor T8 may include a gate electrode receiving the emission control signal. For example, the gate electrode of the eighth transistor T8 may be connected to the emission control line ELi to receive the emission control signal. The eighth transistor T8 may be turned on when the emission control signal is supplied to the emission control line ELI, to electrically connect the anode initialization power Vaint and the fourth node N4. Accordingly, a voltage of the fourth node N4 (or the anode of the light emitting element LD) may be initialized to the voltage of the anode initialization power Vaint).
Regarding claims 3, 9, Kim et al., figs. 2, 3, 6-8, discloses the pixel according to claim 2, wherein in a second period, the first emission control signal has a turn-off level, and the second emission control signals has the turn-off level, and wherein the second period is immediately after the first period (When the emission control signal EMi is not supplied, the sixth and seventh transistors T6 and T7 may be turned on, and the eighth and ninth transistors T8 and T9 may be turned off. When both of the sixth and seventh transistors T6 and T7 are turned on, the light emitting element LD may emit light with a luminance corresponding to the voltage of the first node N1. That is, the pixel PX may emit light during the sixth period P2b).
Regarding claim 4, Kim et al., figs. 2, 6-8, discloses the pixel according to claim 3, wherein in a third period, the first emission control signal has the turn-on level, and the second emission control signal has a turn-on level, and wherein the third period is immediately after the second period (Referring to FIGS. 2 and 3D, the supply of the emission control signal EMi may be maintained during the third period P3a and the first scan signal GWi may be supplied. When the eighth transistor T8 maintains a turn-on state, the voltage of the anode initialization power Vaint may be supplied to the fourth node N4. That is, the anode of the light emitting element LD may be initialized also during the third period P3a).
Regarding claim 5, Kim et al., figs. 2, 3, 6-8, discloses the pixel according to claim 3, the third light emission control transistor is turn on in the second period (When the emission control signal EMi is not supplied, the sixth and seventh transistors T6 and T7 may be turned on, and the eighth and ninth transistors T8 and T9 may be turned off. When both of the sixth and seventh transistors T6 and T7 are turned on, the light emitting element LD may emit light with a luminance corresponding to the voltage of the first node N1. That is, the pixel PX may emit light during the sixth period P2b).
Regarding claim 6, Kim et al., figs. 2, 3, 6-8, discloses the pixel according to claim 1, wherein each of the first transistor, the second transistor, the first light emission transistor, the second light emission transistor, and the third light emission transistor has a P-type semiconductor (the first, sixth, and seventh transistors T1, T6, and T7 may be P-type low-temperature poly-silicon (LTPS) thin film transistors, and the second, third, fourth, fifth, eighth, and ninth transistors T2, T3, T4, T5, T8, and T9 may be N-type oxide semiconductor thin film transistors. Meanwhile, all gate electrodes of each of the sixth, seventh, eighth, and ninth transistors T6, T7, T8, and T9 are connected to the emission control line Eli. However, since the sixth and seventh transistors T6 and T7 are P-type thin film transistors, and the eighth and ninth transistors T8 and T9 are N-type thin film transistors).
Regarding claim 7, Kim et al., figs. 2, 6-8, discloses the pixel according to claim 1, in response to the third emission control signal having a turn-on level, the voltage at a level higher than the first power voltage is applied to the first electrode of the first transistor (the first, sixth, and seventh transistors T1, T6, and T7 may be P-type low-temperature poly-silicon (LTPS) thin film transistors, and the second, third, fourth, fifth, eighth, and ninth transistors T2, T3, T4, T5, T8, and T9 may be N-type oxide semiconductor thin film transistors. Meanwhile, all gate electrodes of each of the sixth, seventh, eighth, and ninth transistors T6, T7, T8, and T9 are connected to the emission control line Eli. However, since the sixth and seventh transistors T6 and T7 are P-type thin film transistors, and the eighth and ninth transistors T8 and T9 are N-type thin film transistors).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Van N Chow whose telephone number is (571)272-7590. The examiner can normally be reached M-F 10-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Ke can be reached at 5712727776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VAN N CHOW/Primary Examiner, Art Unit 2627
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