DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
a) regarding claim 9:
Claim 9 recites the limitation "the first p-type transistor" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the second p-type transistor" in 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the first n-type transistor" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the second n-type transistor" in line 6. There is insufficient antecedent basis for this limitation in the claim.
b) regarding claim 18:
Claim 18 recites the limitation "the first p-type transistor" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "the second p-type transistor" in 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "the first n-type transistor" in line 5. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "the second n-type transistor" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Allowable Subject Matter
Claims 1-8, 10-17 and 19-20 are allowed.
Claims 9 and 18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to disclose or make obvious a circuit, comprising: a first buffer having a first buffer input coupled to a first transmission gate of the first sub-latch and a second transmission gate of the first sub-latch and a first buffer output coupled to the global output terminal; and a second buffer having a second buffer input coupled to a third transmission gate of the second sub-latch and a fourth transmission gate of the second sub-latch and a second buffer output coupled to the global output terminal; wherein the first DICE component and the third DICE component are configured to be in a first operation state, while the second DICE component and fourth DICE component are configured to be in a second, different operation state, along with all the other limitations as required by claim 1.
The prior art of record fails to disclose or make obvious a circuit comprising: wherein the first sub-latch is configured to provide, at a first node of the first sub-latch, a first intermediate signal based on the input signal and a first transmission gate of the first sub-latch, and the second sub-latch is configured to provide, at a second node of the second sub-latch, a second intermediate signal based on the input signal and a second transmission gate of the second sub-latch; a first inverter coupled to the first transmission gate of the first sub-latch and configured to logically invert the first intermediate signal and provide, at a third node, an output signal; and a second inverter coupled to the second transmission gate of the first sub-latch and configured to logically invert the second intermediate signal and provide, at the third node, the output signal, along with all the other limitations as required by claim 10.
The prior art of record fails to disclose or make obvious a method, comprising: providing, by the first sub-latch, a first intermediate signal at a first node of the first sub-latch based on the input signal and a first transmission gate of the first sub-latch; providing, by the second sub-latch, a second intermediate signal at a second node of the second sub-latch based on the input signal and a second transmission gate of the second sub- latch; logically inverting, by a first inverter and a second inverter, the first intermediate signal and the second intermediate signal; providing, at a third node corresponding to an output of the first inverter and the second inverter, an output signal, along with all the other limitations as required by claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick O'Neill whose telephone number is (571)270-1677. The examiner can normally be reached Monday- Friday 9AM-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571)270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICK O NEILL/Primary Examiner, Art Unit 2836
Prosecution Insights