DETAIL ACTION
Notice of Pre-AIA or AIA Status
● The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
● The instant application having application No. 18/644759 has a total of 20 claims pending in the application; there are 3 independent claim and 17 dependent claims, all of which are ready for examination by the examiner.
IFORMATION CONCENING IDS:
● The information disclosure statement (IDS) submitted on 07/08//2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner. A copy (copies) of PTOL-1449s initialed and signed by the examiner is/are attached to the instant office action.
IFORMATION CONCENING DRAWING:
● Application’s drawing submitted on 04/24/2024 are acceptable for examination purposes.
IFORMATION CONCENING CLAIMS:
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
● Claims 2-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
1. The independent claim 2, in part, recite the limitation(s):
“receive, in accordance with a size of available resources being greater than or equal to a size of a set of data and prior to writing the set of data, an indication of a beginning of a write operation for the set of data” (emphasis added).
The claimed specification does not appear to describe/support the above limitation as claimed as claimed. Independent claims 11 and 20 recite similar limitation(s) and are rejected based on the same ground of rejection. Dependent claims 3-10, 12-19, and 20 are rejected by virtue of their dependency from their respected independent based claim.
2. Claim 6 recites, in part, the limitation of:
“transmit, in accordance with writing the set of data to the available resources, an indication that the set of data was written to proper locations in the available resources” (emphasis added).
The claimed specification does not appear to describe/support the above limitation as claimed as claimed.
3. Claim 17 recites the limitation(s) of:
“wherein the instructions are further executable by the one or more processors to: prohibit, in accordance with the size of the available resources being greater than or equal to the size of the set of data, first garbage collection operations at the memory system.”
The claimed specification does not appear to describe/support the above limitation as claimed as claimed.
4. Claim 19 recites the limitation(s) of:
“wherein the instructions are further executable by the one or more processors to: prohibit the second garbage collection operations for the second set of resources; receive a request for an indication of whether the memory system comprises second available resources for storing a second set of data; and transmit, in response to the request, the indication of whether the memory system comprises the second available resources for storing the second set of data in accordance with a second comparison of a threshold size with a combined size of the first set of resources and the second set of resources.”
The claimed specification does not appear to describe/support the above limitation as claimed as claimed.
Double Patenting
● The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
● A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
● The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
● The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
● Claims 2, 5, 7-10, 14-16,18, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims1, 9, 18-19, 21, and 28 of U.S. Patent No. 11/989,439 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because, the minor variation in use of word and order of limitations in claims does make the two set of claims patentably distinct from each other.
● Claims 2, 5, 7-10, 14-16,18, and 20 of instant application (Application 19/269,964) is compared with claims of US Patent 11,989,439 B2 in the following table:
US Patent 11,989,439 B2
US Application 19/269,964
1.An apparatus, comprising: at least one memory device; and at least one controller coupled with the at least one memory device and configured to cause the apparatus to:
receive an indication that a set of data is to be written at a memory system comprising the at least one memory device; remove, based at least in part on the indication that the set of data is to be written, invalid data at the memory system until a size of available resources at the memory system is greater than or equal to a size of the set of data; delay garbage collection operations at the memory system based at least in part on the size of the available resources being greater than or equal to the size of the set of data after removing the invalid data; transmit, based at least in part on removing the invalid data, an indication that the size of the available resources is greater than or equal to the size of the set of data;
receive, based at least in part on the indicated size of the available resources being greater than or equal to the size of the set of data, an indication of a beginning of a write operation for the set of data;
receive the set of data based at least in part on receiving the indication of the beginning of the write operation; and write, based at least in part on receiving the set of data, the set of data to the available resources based at least in part on delaying the garbage collection operations.
9. The apparatus of claim 1, wherein the at least one controller is further configured to cause the apparatus to: store, based at least in part on receiving the indication of the beginning of the write operation, one or both of a first mapping comprising first associations between logical addresses and physical addresses at the memory system or a second mapping indicating a validity of data stored at physical addresses at the memory system.
2. A memory system, comprising: one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive, in accordance with a size of available resources being greater than or equal to a size of a set of data and prior to writing the set of data, an indication of a beginning of a write operation for the set of data;
and
write, in accordance with the write operation, the set of data to the available resources.
store, in accordance with receiving the indication of the beginning of the write operation, one or both of a first mapping comprising first associations between logical addresses and physical addresses at the memory system or a second mapping indicating a validity of data stored at physical addresses at the memory system;
Claim 1:
…
receive, based at least in part on the indicated size of the available resources being greater than or equal to the size of the set of data, an indication of a beginning of a write operation for the set of data; receive the set of data based at least in part on receiving the indication of the beginning of the write operation
…
5. The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
receive, in accordance with the size of the available resources being greater than or equal to the size of the set of data, the set of data, wherein the set of data is received in accordance with receiving the indication of the beginning of the write operation.
Claim 1:
…
remove, based at least in part on the indication that the set of data is to be written, invalid data at the memory system until a size of available resources at the memory system is greater than or equal to a size of the set of data
…
7. The memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to:
remove, in accordance with the indication of the beginning of the write operation, invalid data at the memory system until the size of the available resources at the memory system is greater than or equal to the size of the set of data.
Claim 1:
…
delay garbage collection operations at the memory system based at least in part on the size of the available resources being greater than or equal to the size of the set of data
8. The memory system of claim 7, wherein the processing circuitry is further configured to cause the memory system to:
delay, in accordance with the size of the available resources being greater than or equal to the size of the set of data, first garbage collection operations at the memory system.
Claim 18:
…
delay first garbage collection operations for a first set of resources… second garbage collection operations are enabled for a second set of resources at the memory system
9. The memory system of claim 8, wherein a first set of resources comprise the available resources, and wherein second garbage collection operations remain enabled for a second set of resources at the memory system.
19. The apparatus of claim 18, wherein the at least one controller is further configured to cause the apparatus to:
delay the second garbage collection operations for the second set of resources;
receive a second request for a second indication of whether the memory system comprises available resources for storing a second set of data; and
transmit, in response to the second request, the second indication of whether the memory system comprises available resources for storing the second set of data based at least in part on a second comparison of the threshold size with a combined size of the first set of resources and the second set of resources.
10. The memory system of claim 9, wherein the processing circuitry is further configured to cause the memory system to:
delay the second garbage collection operations for the second set of resources;
receive a request for an indication of whether the memory system comprises second available resources for storing a second set of data; and
transmit, in response to the request, the indication of whether the memory system comprises the second available resources for storing the second set of data in accordance with a second comparison of a threshold size with a combined size of the first set of resources and the second set of resources.
Claim 1:
…
receive, based at least in part on the indicated size of the available resources being greater than or equal to the size of the set of data, an indication of a beginning of a write operation for the set of data; receive the set of data based at least in part on receiving the indication of the beginning of the write operation
…
14. The non-transitory computer-readable medium of claim 11, wherein the instructions are further executable by the one or more processors to:
receive, in accordance with the size of the available resources being greater than or equal to the size of the set of data, the set of data, wherein the set of data is received in accordance with receiving the indication of the beginning of the write operation.
21. The apparatus of claim 18, wherein the at least one controller is further configured to cause the apparatus to:
transmit, based at least in part on writing the set of data to the first set of resources, an indication that the set of data was written successfully to the first set of resources;
receive, based at least in part on the set of data being written successfully, an indication of an end of the write operation; and
perform, based at least in part on indicating the end of the write operation, a set of garbage collection operations that were delayed for the first set of resources.
15. The non-transitory computer-readable medium of claim 11,
wherein the instructions are further executable by the one or more processors to:
transmit, in accordance with writing the set of data to the available resources, an indication that the set of data was written successfully written to the available resources;
receive, in accordance with the set of data being successfully written to the available resources, an indication of an end of the write operation; and
perform, in accordance with the end of the write operation, a set of garbage collection operations that were delayed.
Claim 1:
…
remove, based at least in part on the indication that the set of data is to be written, invalid data at the memory system until a size of available resources at the memory system is greater than or equal to a size of the set of data
…
16. The non-transitory computer-readable medium of claim 11, wherein the instructions are further executable by the one or more processors to:
remove, in accordance with the indication of the beginning of the write operation, invalid data at the memory system until the size of the available resources at the memory system is greater than or equal to the size of the set of data.
Claim 18:
…
delay first garbage collection operations for a first set of resources… second garbage collection operations are enabled for a second set of resources at the memory system
18. The non-transitory computer-readable medium of claim 17, wherein a first set of resources comprise the available resources, and wherein second garbage collection operations remain enabled for a second set of resources at the memory system.
Claim 28:
receiving, based at least in part on the indicated size of the available resources being greater than or equal to the size of the set of data, an indication of a beginning of a write operation for the set of data; …; and
writing, based at least in part on receiving the set of data, the set of data to the available resources…
Claim 9:
…
store, based at least in part on receiving the indication of the beginning of the write operation, one or both of a first mapping comprising first associations between logical addresses and physical addresses at the memory system or a second mapping indicating a validity of data stored at physical addresses at the memory system
20. (New) A method by a memory system, comprising:
receiving, in accordance with a size of available resources being greater than or equal to a size of a set of data and prior to writing the set of data, an indication of a beginning of a write operation for the set of data;
writing, in accordance with the write operation, the set of data to the available resources.
storing, in accordance with receiving the indication of the beginning of the write operation, one or both of a first mapping comprising first associations between logical addresses and physical addresses at the memory system or a second mapping indicating a validity of data stored at physical addresses at the memory system;
Conclusion
The prior art made of record and not relied upon are as follows:
● Muthiah (20200401341 A1) teaches “…The controller is further configured to: provide a hint to a host device on a condition of the memory; receive a command from the host device to alter memory capacity in order to alter memory performance…” (par. 0017)
● CHOI (US 20210278990 A1) teaches “…a garbage collection controller 196 may determine an operation mode for performing the garbage collection. For example, when the garbage collection controller 196 determines that the number of memory blocks (e.g., free blocks) capable of storing new data in the memory device 150 is sufficient based on the percentage of dirty blocks…” (par. 0069).
● Nimura et al. (US 2018/0039441 A1) teaches “…In FIG. 24, the storage control device 100 reads information of each SSD by referring to the SSD state table 900 (step S2401). The information of each SSD includes, for example, information indicating the capacity of a free space of each SSD…” (par. 0222).
● Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
● If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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