DETAILED ACTION
This FINAL action is in response to Application No. 19/270,882 originally filed 07/16/2025. The amendment presented on 06/24/2026 which provides amendments to claims 1, 15, 19, and 20 is hereby acknowledged.
Currently Claim(s) 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 06/24/2026 have been fully considered but they are not persuasive.
The Office notes During patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." The Federal Circuit’s en banc decision in Phillips v. AWH Corp., 415 F.3d 1303, 1316, 75 USPQ2d 1321, 1329 (Fed. Cir. 2005). The Office also notes that drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972). Applicant asserts “Jeon completely fails to disclose that the stages of the scan driver 150 and the emission driver 170 are arranged in the same driving circuit column”. The prior art of Jeon in this case clearly shows all the claimed structural features including the claimed arrangement of the various stage driving circuits in their respective columns at the peripheral of the display panel. The claimed invention broadly claims two columns and multiple stages in at least one of these columns. Figure 3 clearly shows this claimed feature. See the disclosure of Jeon at [0057-0064]. Furthermore, it would be apparent in view of Figures 1 and 3, that each individual stage is disposed in the arrangement as seen in the figures including where each different signal for each of stages. These are clearly shown divided into their respective columns based on their signal type (ie. GB GI GW etc.). Each row shown can be considered the first, second, etc. stage and each column shown can be considered the first, second, third etc. column. Applicants’ claimed invention is sufficiently broad enough to still read on the prior art. Therefore, these arguments are therefore not found persuasive and the rejection will be currently maintained.
With respect to the additional limitations of the pixel circuit, Jeon clearly shows at least two “switching transistors” (i.e. T2, T4, T7, T5, T6) and individual scanning lines signals (i.e. GW, GI, GB, EM) in Figure 2. Applicants’ claimed invention is sufficiently broad enough to still read on the prior art. Therefore, these arguments are not found persuasive and the rejection will be currently maintained.
Remaining arguments regarding the prior art of Kim ‘818 and other applied art appear to be based on the assumption that Jeon failed to teach certain portions of the claimed invention. However as discussed above, Applicants’ claimed invention is sufficiently broad enough to still read on the prior art. Therefore, these arguments are not found persuasive and the rejection will be currently maintained.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-2, 5-9, 11-12, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. U.S. Patent Application Publication No. 2020/0211469 A1 hereinafter Jeon.
Consider Claim 1:
Jeon discloses a display panel comprising: (Jeon, See Abstract.)
a plurality of pixel circuits disposed in a display area; and (Jeon, [0043], “The display panel 110 may include a plurality of data lines, a plurality of scan lines, a plurality of gate initialization lines, a plurality of diode initialization lines, a plurality of emission control lines, and a plurality of pixels PX connected thereto. The display panel 110 may be an OLED display panel where each pixel PX includes an OLED. In some example embodiments, the display panel 110 may be a flexible display panel, such as a foldable display panel, a rollable display panel, a stretchable display panel, etc.”)
a scan driver disposed in a peripheral area adjacent to the display area and (Jeon, [0042], “Referring to FIG. 1, an OLED display device 100 according to example embodiments may include a display panel 110, a data driver 130 that provides data signals DS to the display panel 110, a scan driver 150 that provides scan signals GW1 through GWN+M, gate initialization signals GI1 through GIN+M and diode initialization signals GB1 through GBN+M to the display panel 110, an emission driver 170 that provides emission control signals EM1 through EMN+M to the display panel 110, and a controller 190 that controls the data driver 130, the scan driver 150 and the emission driver 170.”)
comprising a first driving circuit and a second driving circuit, (Jeon, [0078], “FIG. 5 is a block diagram illustrating an example of an emission driver included in the OLED display device of FIG. 1, and FIG. 6 is a circuit diagram illustrating an example of each stage included in the emission driver of FIG. 5.”)
wherein the first driving circuit comprises a plurality of first stages that output first scan signals to the plurality of pixel circuits, the second driving circuit comprises a plurality of second stages that output second scan signals to the plurality of pixel circuits, the plurality of first stages and the plurality of second stages are disposed in a same driving circuit column, the plurality of first stages are disposed in odd-numbered rows, the plurality of second stages are disposed in even-numbered rows, and (Jeon, [0080], [0058], “Referring to FIG. 1 and FIG. 3, a scan driver 150 may include first through (N+M)-th scan stages GW_STG1 through GW_STGN+M, a scan input control circuit including GWICT1 and GWICT2, first through (N+M)-th gate initialization stages GI_STG1 through GI_STGN+M, a gate initialization input control circuit GIICT1 and GIICT2, first through (N+M)-th diode initialization stages GB_STG1 through GB_STGN+M, a diode initialization input control circuit GBICT1 and GBICT2, and an inverter 155 outputting an inverted mode control signal /MCS.”)
each of the plurality of pixel circuits comprises: a driving transistor; a first switching transistor having a gate configured to receive a corresponding first scan signal among the first scan signals; and a second switching transistor having a gate configured to receive a corresponding second scan signal among the second scan signals. (Jeon, [0044], “In some example embodiments, as illustrated in FIG. 2, each pixel PX may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a gate initialization transistor T4, a first emission transistor T5, a second emission transistor T6, a diode initialization transistor T7, a storage capacitor CST and an organic light emitting diode EL. The driving transistor T1 may generate a driving current based on a voltage stored in the storage capacitor CST. The switching transistor T2 may transfer a data signal DS to a source of the driving transistor T1 in response to a scan signal GW. The compensation transistor T3 may diode-connect the driving transistor T1 in response to the scan signal GW. The storage capacitor CST may be connected between a gate of the driving transistor T1 and a line ELVDDL of a first power supply voltage ELVDD. For example, when the scan signal GW is applied, a compensation voltage, where a negative threshold voltage of the driving transistor T1 is added to the data signal DS, may be applied to the storage capacitor CST through the diode-connected driving transistor T1. The gate initialization transistor T4 may apply an initialization voltage VINIT to the gate of the driving transistor T1 and the storage capacitor CST in response to a gate initialization signal GI. The gate of the driving transistor T1 and the storage capacitor CST may be initialized by the initialization voltage VINIT applied through the gate initialization transistor T4. The first emission transistor T5 may connect the first power supply voltage line ELVDDL to the source of the driving transistor T1 in response to an emission control signal EM, and the second emission transistor T6 may connect a drain of the driving transistor T1 to the organic light emitting diode EL in response to the emission control signal EM. For example, while the emission control signal EM is applied, the first and second emission transistors T5 and T6 may be turned on to form a path of the driving current from the first power supply voltage line ELVDDL through the first emission transistor T5, the driving transistor T1, the second emission transistor T6 and the organic light emitting diode EL to a line of a second power supply voltage ELVSS. The diode initialization transistor (e.g., a bypass transistor) T7 may connect a line VINITL of the initialization voltage VINIT to an anode of the organic light emitting diode EL and a drain of the second emission transistor T6 in response to a diode initialization signal (e.g., a bypass signal) GB.”)
Consider Claim 2:
Jeon discloses the display panel of claim 1, further comprising: a first carry signal line that connects an input terminal of a first stage located at an nth position among the plurality of first stages to an output terminal of a first stage located at an (n-1)th position among the plurality of first stages; and a second carry signal line that connects an input terminal of a second stage located at an nth position among the plurality of second stages to an output terminal of a second stage located at an (n-1)th position among the plurality of second stages, wherein n is a natural number greater than or equal to 2. (Jeon, [0080], [0050], “The emission driver 170 may provide the emission control signals EM1 through EMN+M to the plurality of pixels PX based on an emission driver control signal received from the controller 190. In some example embodiments, the emission driver control signal may include, but is not limited to, the mode control signal MCS, first and second emission control start signals EM_FLM1 and EM_FLM2 and first and second emission control clock signals EM_CLK1 and EM_CLK2.” See also Fig. 5-6)
Consider Claim 5:
Jeon discloses the display panel of claim 2, wherein a first start signal is input to an input terminal of a first stage located at a first position among the plurality of first stages, and a second start signal that is different from the first start signal is input to an input terminal of a second stage located at a first position among the plurality of second stages. (Jeon, [0080], [0050], “The emission driver 170 may provide the emission control signals EM1 through EMN+M to the plurality of pixels PX based on an emission driver control signal received from the controller 190. In some example embodiments, the emission driver control signal may include, but is not limited to, the mode control signal MCS, first and second emission control start signals EM_FLM1 and EM_FLM2 and first and second emission control clock signals EM_CLK1 and EM_CLK2.” See also Fig. 5-6)
Consider Claim 6:
Jeon discloses the display panel of claim 5, wherein a first scan signal output by the first stage located at the (n-1)th position is input to the input terminal of the first stage located at the nth position among the plurality of first stages, and a second scan signal output by the second stage located at the (n-1)th position is input to the input terminal of the second stage located at the nth position among the plurality of second stages. (Jeon, [0080], [0050], “The emission driver 170 may provide the emission control signals EM1 through EMN+M to the plurality of pixels PX based on an emission driver control signal received from the controller 190. In some example embodiments, the emission driver control signal may include, but is not limited to, the mode control signal MCS, first and second emission control start signals EM_FLM1 and EM_FLM2 and first and second emission control clock signals EM_CLK1 and EM_CLK2.” See also Fig. 5-6)
Consider Claim 7:
Jeon discloses the display panel of claim 1, further comprising: clock lines connected to the scan driver, wherein the clock lines comprise a first clock line to which a first clock signal is input and a second clock line to which a second clock signal is input, and the first clock signal and the second clock signal comprise signals having a same waveform with a shifted phase. (Jeon, [0050], [0080], “The first through (N+M)-th emission control stages EM_STG1 through EM_STGN+M may sequentially apply the first through (N+M)-th emission control signals EM1 through EMN+M to first through (N+M)-th pixel rows PXR1 through PXRN+M based on first and second emission control start signals EM_FLM1 and EM_FLM2 and first and second emission control clock signals EM_CLK1 and EM_CLK2. In some example embodiments, the first and second emission control clock signals EM_CLK1 and EM_CLK2 may have opposite phases to each other. In some example embodiments, each odd-numbered emission control stage (e.g., EM_STG1, EM_STGN+1, etc.) may receive the first and second emission control clock signals EM_CLK1 and EM_CLK2 at first and second clock inputs, respectively, and each even-numbered emission control stage (e.g., EM_STG2, EM_STGN, EM_STGN+2, EM_STGN+M, etc.) may receive the second and first emission control clock signals EM_CLK2 and EM_CLK1 at the first and second clock inputs, respectively.”)
Consider Claim 8:
Jeon discloses the display panel of claim 7, wherein the plurality of first stages and the plurality of second stages each comprise a first clock terminal and a second clock terminal, the first clock line and the second clock line are alternately connected to the first clock terminals of the plurality of first stages and the plurality of second stages, and the second clock line and the first clock line are alternately connected to the second clock terminals of the plurality of first stages and the plurality of second stages. (Jeon, [0080], [0081], “In some example embodiments, as illustrated in FIG. 6, each stage EM_STG of the first through (N+M)-th emission control stages (e.g., EM_STG1 through EM_STGN+M) may include first through tenth transistors EMM1 through EMM10 and first through third capacitors EMC1, EMC2, and EMC3. The first transistor EMM1 may transfer an emission control start signal EM_FLM or a previous emission control signal PEM to a first node EMN1 in response to the first emission control clock signal EM_CLK1. The second transistor EMM2 may transfer the first emission control clock signal EM_CLK1 to a second node EMN2 in response to a voltage of the first node EMN1. The third transistor EMM3 may transfer a low gate voltage VGL to the second node EMN2 in response to the first emission control clock signal EM_CLK1. The fourth and fifth transistors EMM4 and EMM5 may transfer a high gate voltage VGH to the first node EMN1 in response to the second emission control clock signal EM_CLK2 and a voltage of the second node EMN2. The sixth transistor EMM6 may transfer the second emission control clock signal EM_CLK2 to a third node EMN3 in response to the voltage of the second node EMN2. The seventh transistor EMM7 may connect the third node EMN3 and a fourth node EMN4 in response to the second emission control clock signal EM_CLK2. The eighth transistor EMM8 may transfer the high gate voltage VGH to the fourth node EMN4 in response to the voltage of the first node EMN1. The ninth transistor EMM9 may transfer the high gate voltage VGH to an output node EMNO in response to a voltage of the fourth node EMN4. The tenth transistor EMM10 may transfer the low gate voltage VGL as an emission control signal EM to the output node EMNO in response to the voltage of the first node EMN1. The first capacitor EMC1 may be connected between the first node EMN1 and a line of the second emission control clock signal EM_CLK2, the second capacitor EMC2 may be connected between the second node EMN2 and the third node EMN3, and the third capacitor EMC3 may be connected between a line of the high gate voltage VGH and the fourth node EMN4.”)
Consider Claim 9:
Jeon discloses the display panel of claim 1, further comprising: clock lines connected to the scan driver, wherein the clock lines comprise a first clock line to which a first clock signal is input, a second clock line to which a second clock signal is input, a third clock line to which a third clock signal is input, and a fourth clock line to which a fourth clock signal is input, the first clock signal and the second clock signal comprise signals having a same waveform with a shifted phase, and the third clock signal and the fourth clock signal comprise signals having a same waveform with a shifted phase. (Jeon, [0048], “The scan driver 150 may sequentially provide the scan signals GW1 through GWN+M, the gate initialization signals GI1 through GIN+M and the diode initialization signals GB1 through GBN+M on a pixel row basis based on a scan control signal received from the controller 190. In some example embodiments, the scan control signal may include, but is not limited to, a mode control signal MCS, first and second scan start signals GW_FLM1 and GW_FLM2, first and second scan clock signals GW_CLK1 and GW_CLK2, first and second gate initialization start signals GI_FLM1 and GI_FLM2, first and second gate initialization clock signals GI_CLK1 and GI_CLK2, first and second diode initialization start signals GB_FLM1 and GB_FLM2, and first and second diode initialization clock signals GB_CLK1 and GB_CLK2.”)
Consider Claim 11:
Jeon discloses the display panel of claim 1, wherein a first stage located at an ith position among the plurality of first stages outputs a first scan signal to ones of the plurality of pixel circuits disposed in a (2i-1)th row and in a 2ith row, a second stage located at an ith position among the plurality of second stages outputs a second scan signal to the ones of the plurality of pixel circuits disposed in the (2i-1 )th row and the 2ith row, and i is a natural number greater than or equal to 1. (Jeon, [0059], [0058], “Referring to FIG. 1 and FIG. 3, a scan driver 150 may include first through (N+M)-th scan stages GW_STG1 through GW_STGN+M, a scan input control circuit including GWICT1 and GWICT2, first through (N+M)-th gate initialization stages GI_STG1 through GI_STGN+M, a gate initialization input control circuit GIICT1 and GIICT2, first through (N+M)-th diode initialization stages GB_STG1 through GB_STGN+M, a diode initialization input control circuit GBICT1 and GBICT2, and an inverter 155 outputting an inverted mode control signal /MCS.”)
Consider Claim 12:
Jeon discloses the display panel of claim 1, wherein the scan driver further comprises a third driving circuit, the third driving circuit comprises a plurality of third stages that output third scan signals to the plurality of pixel circuits, and the plurality of third stages are spaced apart from the plurality of first stages and the plurality of second stages in a first direction. (Jeon, [0042], “Referring to FIG. 1, an OLED display device 100 according to example embodiments may include a display panel 110, a data driver 130 that provides data signals DS to the display panel 110, a scan driver 150 that provides scan signals GW1 through GWN+M, gate initialization signals GI1 through GIN+M and diode initialization signals GB1 through GBN+M to the display panel 110, an emission driver 170 that provides emission control signals EM1 through EMN+M to the display panel 110, and a controller 190 that controls the data driver 130, the scan driver 150 and the emission driver 170.”)
Consider Claim 20:
Jeon discloses an electronic device comprising: (Jeon, See Abstract.)
a display panel; and a lower cover constituting an exterior of the electronic device and having an opening exposing a portion of the display panel in a front surface, wherein the display panel comprises: a plurality of pixel circuits disposed in a display area; and (Jeon, [0043], “The display panel 110 may include a plurality of data lines, a plurality of scan lines, a plurality of gate initialization lines, a plurality of diode initialization lines, a plurality of emission control lines, and a plurality of pixels PX connected thereto. The display panel 110 may be an OLED display panel where each pixel PX includes an OLED. In some example embodiments, the display panel 110 may be a flexible display panel, such as a foldable display panel, a rollable display panel, a stretchable display panel, etc.”)
a scan driver disposed in a peripheral area adjacent to the display area and (Jeon, [0042], “Referring to FIG. 1, an OLED display device 100 according to example embodiments may include a display panel 110, a data driver 130 that provides data signals DS to the display panel 110, a scan driver 150 that provides scan signals GW1 through GWN+M, gate initialization signals GI1 through GIN+M and diode initialization signals GB1 through GBN+M to the display panel 110, an emission driver 170 that provides emission control signals EM1 through EMN+M to the display panel 110, and a controller 190 that controls the data driver 130, the scan driver 150 and the emission driver 170.”)
comprising a first driving circuit and a second driving circuit, (Jeon, [0078], “FIG. 5 is a block diagram illustrating an example of an emission driver included in the OLED display device of FIG. 1, and FIG. 6 is a circuit diagram illustrating an example of each stage included in the emission driver of FIG. 5.”)
the first driving circuit comprises a plurality of first stages that output first scan signals to the plurality of pixel circuits, the second driving circuit comprises a plurality of second stages that output second scan signals to the plurality of pixel circuits, the plurality of first stages and the plurality of second stages are disposed in a same driving circuit column, the plurality of first stages and the plurality of second stages are disposed alternately in different rows, and (Jeon, [0080], [0058], “Referring to FIG. 1 and FIG. 3, a scan driver 150 may include first through (N+M)-th scan stages GW_STG1 through GW_STGN+M, a scan input control circuit including GWICT1 and GWICT2, first through (N+M)-th gate initialization stages GI_STG1 through GI_STGN+M, a gate initialization input control circuit GIICT1 and GIICT2, first through (N+M)-th diode initialization stages GB_STG1 through GB_STGN+M, a diode initialization input control circuit GBICT1 and GBICT2, and an inverter 155 outputting an inverted mode control signal /MCS.”)
each of the plurality of pixel circuits comprises: a driving transistor; a first switching transistor having a gate configured to receive a corresponding first scan signal among the first scan signals; and a second switching transistor having a gate configured to receive a corresponding second scan signal among the second scan signals. (Jeon, [0044], “In some example embodiments, as illustrated in FIG. 2, each pixel PX may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a gate initialization transistor T4, a first emission transistor T5, a second emission transistor T6, a diode initialization transistor T7, a storage capacitor CST and an organic light emitting diode EL. The driving transistor T1 may generate a driving current based on a voltage stored in the storage capacitor CST. The switching transistor T2 may transfer a data signal DS to a source of the driving transistor T1 in response to a scan signal GW. The compensation transistor T3 may diode-connect the driving transistor T1 in response to the scan signal GW. The storage capacitor CST may be connected between a gate of the driving transistor T1 and a line ELVDDL of a first power supply voltage ELVDD. For example, when the scan signal GW is applied, a compensation voltage, where a negative threshold voltage of the driving transistor T1 is added to the data signal DS, may be applied to the storage capacitor CST through the diode-connected driving transistor T1. The gate initialization transistor T4 may apply an initialization voltage VINIT to the gate of the driving transistor T1 and the storage capacitor CST in response to a gate initialization signal GI. The gate of the driving transistor T1 and the storage capacitor CST may be initialized by the initialization voltage VINIT applied through the gate initialization transistor T4. The first emission transistor T5 may connect the first power supply voltage line ELVDDL to the source of the driving transistor T1 in response to an emission control signal EM, and the second emission transistor T6 may connect a drain of the driving transistor T1 to the organic light emitting diode EL in response to the emission control signal EM. For example, while the emission control signal EM is applied, the first and second emission transistors T5 and T6 may be turned on to form a path of the driving current from the first power supply voltage line ELVDDL through the first emission transistor T5, the driving transistor T1, the second emission transistor T6 and the organic light emitting diode EL to a line of a second power supply voltage ELVSS. The diode initialization transistor (e.g., a bypass transistor) T7 may connect a line VINITL of the initialization voltage VINIT to an anode of the organic light emitting diode EL and a drain of the second emission transistor T6 in response to a diode initialization signal (e.g., a bypass signal) GB.”)
Claim Rejections - 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. U.S. Patent Application Publication No. 2020/0211469 A1 as applied to claim 2 above, and further in view of Park U.S. Patent Application Publication No. 2020/0349892 A1 hereinafter Park.
Consider Claim 3:
Jeon discloses the display panel of claim 2, however does not appear to specify wherein, in a plan view, the first carry signal line intersects the second carry signal line.
Park however teaches that it was a known technique to provide in a plan view, the first carry signal line intersects the second carry signal line. (Park, [0134], “The carry signal output lines transmitting the carry signal across the stages are represented in FIG. 8.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide connections that overlap since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japiske, 86 USPQ 70 C.C.P.A. 1950). In this case, the relevant portions are taught in view of Park and such an arrangement would have been obvious. The rearrangement in this case does not modify the operation of the device because the outputs of the prior stages are connected similarly as in the prior art. Therefore, providing a connection to an additional stage that overlaps would not modify the operation of the device and the results would have been predictable.
Consider Claim 4:
Jeon discloses the display panel of claim 3, wherein the first carry signal line and the second carry signal line are disposed on different layers in an area where the first carry signal line and the second carry signal line intersect each other.
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide connections that overlap since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japiske, 86 USPQ 70 C.C.P.A. 1950). In this case, the relevant portions are taught in view of Park and such an arrangement providing them on different layers would have been obvious as one of skill would readily recognize this prevents the lines from being shorted. The rearrangement in this case does not modify the operation of the device because the outputs of the prior stages are connected similarly as in the prior art. Therefore, providing a connection to an additional stage that overlaps on different layers would not modify the operation of the device and the results would have been predictable.
Claim Rejections - 35 USC § 103
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. U.S. Patent Application Publication No. 2020/0211469 A1 as applied to claim 9 above, and further in view of Kim et al. U.S. Patent Application Publication No. 2020/0211493 A1 hereinafter Kim.
Consider Claim 10:
Jeon discloses the display panel of claim 9, wherein the plurality of first stages and the plurality of second stages each comprise a first clock terminal and a second clock terminal, Jeon however does not further specify the connections having the first clock line and the second clock line are alternately connected to the first clock terminals of the plurality of first stages, the second clock line and the first clock line are alternately connected to the second clock terminals of the plurality of first stages, the third clock line and the fourth clock line are alternately connected to the first clock terminals of the plurality of second stages, and the fourth clock line and the third clock line are alternately connected to the second clock terminals of the plurality of second stages.
Kim however teaches that it was a known technique to those of skill in the art before the effective filing date of the invention to provide a first clock line and the second clock line are alternately connected to the first clock terminals of the plurality of first stages, the second clock line and the first clock line are alternately connected to the second clock terminals of the plurality of first stages, the third clock line and the fourth clock line are alternately connected to the first clock terminals of the plurality of second stages, and the fourth clock line and the third clock line are alternately connected to the second clock terminals of the plurality of second stages. (Kim, [0086] That is, the third gate driving circuit 330 may include the odd stages ST1 to ST(2n−1) corresponding to the total number of odd gate lines GL1 to GL(2n−1) and the even stages ST2 to ST(2n) corresponding to the total number of even gate lines GL2 to GL(2n). In detail, the third gate driving circuit 330 may receive first and second driving voltages VDD and VSS through a common signal line CGS passing through a fourth non-display area NA4, receive first, third, fifth, and seventh gate clocks CLK1, CLK3, CLK5, and CLK7 through an odd clock line CLK_ODD, and receive second, fourth, sixth, and eighth gate clocks CLK2, CLK4, CLK6, and CLK8 through an even clock line CLK_EVEN. Here, each of the first to eighth gate clocks CLK1 to CLK8 may have a phase which is sequentially shifted. In this case, the odd clock line CLK_ODD may transfer the first, third, fifth, and seventh gate clocks CLK1, CLK3, CLK5, and CLK7 to the odd stages ST1 to ST(2n−1), and the even clock line CLK_EVEN may transfer the second, fourth, sixth, and eighth gate clocks CLK2, CLK4, CLK6, and CLK8 to the even stages ST2 to ST(2n).”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to alternatively connect clock signals choosing from four clocks as this was a known technique in view of Kim and would have been utilized for the purpose of may prevent delay from occurring in high speed driving (or high frequency driving), and thus, may easily perform the high-speed driving of a large display panel, thereby enhancing image quality. (Kim, [0120])
Claim Rejections - 35 USC § 103
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. U.S. Patent Application Publication No. 2020/0211469 A1.
Consider Claim 13:
Jeon discloses the display panel of claim 12, however does not specify wherein a width of one of the plurality of first stages in a second direction intersecting the first direction is equal to a width of one of the plurality of second stages in the second direction. (Jeon, [0059], [0058], “Referring to FIG. 1 and FIG. 3, a scan driver 150 may include first through (N+M)-th scan stages GW_STG1 through GW_STGN+M, a scan input control circuit including GWICT1 and GWICT2, first through (N+M)-th gate initialization stages GI_STG1 through GI_STGN+M, a gate initialization input control circuit GIICT1 and GIICT2, first through (N+M)-th diode initialization stages GB_STG1 through GB_STGN+M, a diode initialization input control circuit GBICT1 and GBICT2, and an inverter 155 outputting an inverted mode control signal /MCS.”)
A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). In addition, it has been held that a mere change in shape of an element is generally recognized as being within the level of ordinary skill in the art when the change in shape is not significant to the function of the combination, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Consider Claim 14:
Jeon discloses the display panel of claim 13, wherein a width of one of the plurality of third stages is equal to a sum of the width of the one of the plurality of first stages and the width of the one of the plurality of second stages. (Jeon, [0059], [0058], “Referring to FIG. 1 and FIG. 3, a scan driver 150 may include first through (N+M)-th scan stages GW_STG1 through GW_STGN+M, a scan input control circuit including GWICT1 and GWICT2, first through (N+M)-th gate initialization stages GI_STG1 through GI_STGN+M, a gate initialization input control circuit GIICT1 and GIICT2, first through (N+M)-th diode initialization stages GB_STG1 through GB_STGN+M, a diode initialization input control circuit GBICT1 and GBICT2, and an inverter 155 outputting an inverted mode control signal /MCS.”)
A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). In addition, it has been held that a mere change in shape of an element is generally recognized as being within the level of ordinary skill in the art when the change in shape is not significant to the function of the combination, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim Rejections - 35 USC § 103
Claim(s) 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. U.S. Patent Application Publication No. 2020/0211469 A1 and further in view of Kim et al. U.S. Patent Application Publication No. 2016/0055818 hereinafter Kim ‘818
Consider Claim 15:
Jeon discloses a display panel comprising: (Jeon, See Abstract.)
a plurality of pixel circuits disposed in a display area; and a scan driver disposed in a peripheral area adjacent to the display area and comprising (Jeon, [0043], “The display panel 110 may include a plurality of data lines, a plurality of scan lines, a plurality of gate initialization lines, a plurality of diode initialization lines, a plurality of emission control lines, and a plurality of pixels PX connected thereto. The display panel 110 may be an OLED display panel where each pixel PX includes an OLED. In some example embodiments, the display panel 110 may be a flexible display panel, such as a foldable display panel, a rollable display panel, a stretchable display panel, etc.”)
a first driving circuit, a second driving circuit, and a third driving circuit, (Jeon, [0042], “Referring to FIG. 1, an OLED display device 100 according to example embodiments may include a display panel 110, a data driver 130 that provides data signals DS to the display panel 110, a scan driver 150 that provides scan signals GW1 through GWN+M, gate initialization signals GI1 through GIN+M and diode initialization signals GB1 through GBN+M to the display panel 110, an emission driver 170 that provides emission control signals EM1 through EMN+M to the display panel 110, and a controller 190 that controls the data driver 130, the scan driver 150 and the emission driver 170.”)
wherein the first driving circuit comprises a plurality of first stages that output first scan signals to the plurality of pixel circuits, the second driving circuit comprises a plurality of second stages that output second scan signals to the plurality of pixel circuits, the third driving circuit comprises a plurality of third stages that output third scan signals to the plurality of pixel circuits, the plurality of first stages, the plurality of second stages and the plurality of third stages are disposed in a same driving circuit column, and (Jeon, [0080], [0058], “Referring to FIG. 1 and FIG. 3, a scan driver 150 may include first through (N+M)-th scan stages GW_STG1 through GW_STGN+M, a scan input control circuit including GWICT1 and GWICT2, first through (N+M)-th gate initialization stages GI_STG1 through GI_STGN+M, a gate initialization input control circuit GIICT1 and GIICT2, first through (N+M)-th diode initialization stages GB_STG1 through GB_STGN+M, a diode initialization input control circuit GBICT1 and GBICT2, and an inverter 155 outputting an inverted mode control signal /MCS.”)
each of the plurality of pixel circuits comprises: a driving transistor; a first switching transistor having a gate configured to receive a corresponding first scan signal among the first scan signals; a second switching transistor having a gate configured to receive a corresponding second scan signal among the second scan signals; and a third switching transistor having a gate configured to receive a corresponding third scan signal among the third scan signals. (Jeon, [0044], “In some example embodiments, as illustrated in FIG. 2, each pixel PX may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a gate initialization transistor T4, a first emission transistor T5, a second emission transistor T6, a diode initialization transistor T7, a storage capacitor CST and an organic light emitting diode EL. The driving transistor T1 may generate a driving current based on a voltage stored in the storage capacitor CST. The switching transistor T2 may transfer a data signal DS to a source of the driving transistor T1 in response to a scan signal GW. The compensation transistor T3 may diode-connect the driving transistor T1 in response to the scan signal GW. The storage capacitor CST may be connected between a gate of the driving transistor T1 and a line ELVDDL of a first power supply voltage ELVDD. For example, when the scan signal GW is applied, a compensation voltage, where a negative threshold voltage of the driving transistor T1 is added to the data signal DS, may be applied to the storage capacitor CST through the diode-connected driving transistor T1. The gate initialization transistor T4 may apply an initialization voltage VINIT to the gate of the driving transistor T1 and the storage capacitor CST in response to a gate initialization signal GI. The gate of the driving transistor T1 and the storage capacitor CST may be initialized by the initialization voltage VINIT applied through the gate initialization transistor T4. The first emission transistor T5 may connect the first power supply voltage line ELVDDL to the source of the driving transistor T1 in response to an emission control signal EM, and the second emission transistor T6 may connect a drain of the driving transistor T1 to the organic light emitting diode EL in response to the emission control signal EM. For example, while the emission control signal EM is applied, the first and second emission transistors T5 and T6 may be turned on to form a path of the driving current from the first power supply voltage line ELVDDL through the first emission transistor T5, the driving transistor T1, the second emission transistor T6 and the organic light emitting diode EL to a line of a second power supply voltage ELVSS. The diode initialization transistor (e.g., a bypass transistor) T7 may connect a line VINITL of the initialization voltage VINIT to an anode of the organic light emitting diode EL and a drain of the second emission transistor T6 in response to a diode initialization signal (e.g., a bypass signal) GB.”)
Jeon however does not specify that the plurality of first stages are disposed in a (3j-2)th row, the plurality of second stages are disposed in a (3j-1 )th row, the plurality of third stages are disposed in a 3jth row, and j is a natural number greater than or equal to 1.
Kim ‘818 however teaches that it was a known technique to those of skill in the art before the effective filing date of the invention to provide an arrangement of wherein stages are disposed in a (3j-2)th row, the plurality of second stages are disposed in a (3j-1 )th row, the plurality of third stages are disposed in a 3jth row, and j is a natural number greater than or equal to 1. (Kim ‘818, [0140-0149], [0145] As shown in FIG. 9, clock signals having opposite phases to each other (i.e., having the phase difference of 180 degrees) are applied to the stages (SRj−3, SRj+3) that are disposed by the three steps therebefore or thereafter. Therefore, the stages receiving the clock signals (CK1, CK1B; CK2, CK2B; CK3, CK3B) having opposite phases to each other transmit and receive the carry signal to and from each other.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide an arrangement of a three stage interval having a carry signal to a corresponding third stage below as this was a known technique in view of Kim ‘818 and would have been utilized for the purpose of the gate driver may simultaneously drive an odd-numbered gate line and an even-numbered gate line adjacent thereto, and can separately drive odd-numbered gate lines and even-numbered gate lines. Accordingly, in such embodiment, the displaying time of the black image inserted for preventing crosstalk may be substantially reduced. (Kim ‘818, [0032])
Consider Claim 16:
Jeon in view of Kim ‘818 disclose the display panel of claim 15, further comprising: a first carry signal line that connects an input terminal of a first stage located at an nth position among the plurality of first stages to an output terminal of a first stage located at an (n-1)th position among the plurality of first stages; a second carry signal line that connects an input terminal of a second stage located at an nth position among the plurality of second stages to an output terminal of a second stage located at an (n-1)th position among the plurality of second stages; and a third carry signal line that connects an input terminal of a third stage located at an nth position among the plurality of third stages to an output terminal of a third stage located at an (n-1)th position among the plurality of third stages, wherein n is a natural number greater than or equal to 2. (Kim ‘818, [0140-0149], [0144], “In such an embodiment, as described above, the 1st to 3rd stages (SR1-SR3) start the operations thereof by the start pulse vertical signal STV, and the other stages (SR4, SR5, . . . ) start the operations by the carry signal (CRj−3) of the stage (SRj−3) that is disposed by the three steps therebefore. All stages finish the operations by the carry signal (CRj+4) of the stage (SRj+4) that is disposed by the four steps thereafter. The last three stages from among all stages, which have no stage that is disposed by the three steps thereafter, may receive the carry signal from 1st to 3rd dummy stages (not shown). In such an embodiment, all stages may receive the carry signal (CRj+6) from the stage (SRj+6) that is disposed by the six steps thereafter, and in this case, the last three stages may receive a carry signal from 4th to 6th dummy stages (not shown). The 4th to 6th dummy stages may receive the start pulse vertical signal STV and finish the operations thereof.”)
Consider Claim 17:
Jeon in view of Kim ‘818 disclose the display panel of claim 15, further comprising: clock lines connected to the scan driver, wherein the clock lines comprise a first clock line to which a first clock signal is input, a second clock line to which a second clock signal is input, a third clock line to which a third clock signal is input, and a fourth clock line to which a fourth clock signal is input, the first clock signal and the second clock signal comprise signals having a same waveform with a shifted phase, and the third clock signal and the fourth clock signal comprise signals having a same waveform with a shifted phase. (Jeon, [0052], Kim ‘818, [0140-0149], [0146], “In an exemplary embodiment, as shown in FIG. 10, the first to third clock signals (CK1-CK3) may have a duty ratio of about 50%, have a pulse width of 3H, and be sequentially phase-delayed by 1H from one another. The first to third inverted clock signals (CK1B-CK3B) have opposite phases to those of the first to third clock signals (CK1-CK3). When the clock signals (CK1-CK3, CK1B-CK3B) are applied to the stages of the gate driver connected as shown in FIG. 9, the respective stages transmit and receive the carry signal, and output the 3H-width gate-on voltage that is sequentially phase-delayed by 1H to the gate lines.”)
Consider Claim 18:
Jeon in view of Kim ‘818 disclose the display panel of claim 17, wherein the plurality of first stages, the plurality of second stages, and the plurality of third stages each comprise a first clock terminal and a second clock terminal, the first clock line and the second clock line are alternately connected to the first clock terminals of the plurality of first stages, the second clock line and the first clock line are alternately connected to the second clock terminals of the plurality of first stages, the first clock line and the second clock line are alternately connected to the first clock terminals of the plurality of second stages, the second clock line and the first clock line are alternately connected to the second clock terminals of the plurality of second stages, the third clock line and the fourth clock line are alternately connected to the first clock terminals of the plurality of third stages, and the fourth clock line and the third clock line are alternately connected to the second clock terminals of the plurality of third stages. (Jeon, [0052], Kim ‘818, [0141], “Referring to FIG. 9, the respective stages are shown with blocks, and the clock signals input to the stages are indicated in the blocks. The respective blocks show 1st, 2nd, . . . , 12th stages from top to bottom, and are connected to the 1st, 2nd, . . . , 12th gate lines (G1, G2, . . . , G12). For convenience of illustration and description, twelve stages are shown in FIG. 9, but not being limited thereto. In an exemplary embodiment, the gate driver may include many more stages, for example, hundreds or thousands of stages depending on the resolution of the display device, and the gate driver may further include dummy stages. In such an embodiment, as shown in FIG. 9, the first to third clock signals CK1, CK2 and CK3 and the first to third inverted clock signals CK1B, CK2B and CK3B are sequentially input to each stage from the first stage with six consecutive stages as a repetition unit. The respective stages may have a circuit structure substantially the same as the circuit structure described above with reference to FIG. 5.”)
Consider Claim 19:
Jeon in view of Kim ‘818 disclose the display panel of claim 15, wherein a first stage located at an ith position among the plurality of first stages outputs a first scan signal to ones of the plurality of pixel circuits disposed in a (2i-1 )th row and a 2ith row, a second stage located at an ith position among the plurality of second stages outputs a second scan signal to the ones of the plurality of pixel circuits disposed in the (2i-1)th row and the pixel circuits disposed in the 2ith row, a third stage located at an ith position among the plurality of third stages outputs a third scan signal to the ones of the plurality of pixel circuits disposed in the (2i-1)th row and the 2ith row, and i is a natural number greater than or equal to 1. (Kim ‘818, [0144], “In such an embodiment, as described above, the 1st to 3rd stages (SR1-SR3) start the operations thereof by the start pulse vertical signal STV, and the other stages (SR4, SR5, . . . ) start the operations by the carry signal (CRj−3) of the stage (SRj−3) that is disposed by the three steps therebefore. All stages finish the operations by the carry signal (CRj+4) of the stage (SRj+4) that is disposed by the four steps thereafter. The last three stages from among all stages, which have no stage that is disposed by the three steps thereafter, may receive the carry signal from 1st to 3rd dummy stages (not shown). In such an embodiment, all stages may receive the carry signal (CRj+6) from the stage (SRj+6) that is disposed by the six steps thereafter, and in this case, the last three stages may receive a carry signal from 4th to 6th dummy stages (not shown). The 4th to 6th dummy stages may receive the start pulse vertical signal STV and finish the operations thereof.”)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Granting of After Final Interviews: “Interviews merely to restate arguments of record or to discuss new limitations which would require more than nominal reconsideration or new search should be denied.” See MPEP § 713.09.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J JANSEN II whose telephone number is (571)272-5604. The examiner can normally be reached Normally Available Monday-Friday 9am-4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached on 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michael J Jansen II/ Primary Examiner, Art Unit 2626
Prosecution Insights