Prosecution Insights
Last updated: October 26, 2026
Application No. 19/272,511

MULTI-OS-BASED ELECTRONIC APPARATUS AND METHOD FOR CONTROLLING SAME

Non-Final OA §102
Filed
Jul 17, 2025
Priority
Feb 15, 2023 — RE 10-2023-0020051 +1 more
Examiner
DONABED, NINOS
Art Unit
2444
Tech Center
2400 — Computer Networks
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
507 granted / 674 resolved
+17.2% vs TC avg
Strong +64% interview lift
Without
With
+64.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
18 currently pending
Career history
708
Total Applications
across all art units

Statute-Specific Performance

§101
20.3%
-19.7% vs TC avg
§103
43.9%
+3.9% vs TC avg
§102
10.9%
-29.1% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 674 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claims 1-20 are pending. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shaposhnik (U,S, Patent App Pub 20130332924) Regarding claim 1, Shaposhnik teaches an electronic apparatus, comprising: memory storing at least one instruction; and one or more processors, wherein the at least one instruction, when executed by the one or more processors, individually or collectively, cause the electronic apparatus to:based on a preconfigured event occurring, identify a context related to a network configuration of the electronic apparatus, and deactivate a network configuration function of a sub operating system (OS) of the electronic apparatus, and (See figure 6 and paragraphs 33-38, Shaposhnik teaches a host OS and a guest OS, deactivating a sub OS when a failure happens) change network configuration information of a host OS of the electronic apparatus based on the context. (See figure 6 and paragraphs 33-38, Shaposhnik teaches a host OS and a guest OS, reloading the sub and re executing. ) Regarding claim 2, Shaposhnik teaches the electronic apparatus as claimed in claim 1, wherein the at least one instruction, when executed by the one or more processors, individually or collectively, cause the electronic apparatus to, based the network configuration information of the host OS being changed and the network configuration function of the sub OS being deactivated: change network configuration information of the sub OS based on the changed network configuration information. (See figure 6 and paragraphs 33-38, Shaposhnik) Regarding claim 3, Shaposhnik teaches the electronic apparatus as claimed in claim 2, wherein the at least one instruction, when executed by the one or more processors, individually or collectively, cause the electronic apparatus to, based on the network configuration information of the host OS being changed from first network configuration information to second network configuration information, and the first network configuration information being restored to the first network configuration information within a critical period of time, maintain the first network configuration information without changing the network configuration information of the sub OS. (See paragraphs 83, 96, 99, Shaposhnik) Regarding claim 4, Shaposhnik teaches the electronic apparatus as claimed in claim 1, wherein the at least one instruction, when executed by the one or more processors, individually or collectively, cause the electronic apparatus to: based on the electronic apparatus being booted, identify the context, and deactivate the network configuration function of the sub OS based on the context. (See paragraphs 79, 121, Shaposhnik) Regarding claim 5, Shaposhnik teaches the electronic apparatus as claimed in claim 1, wherein the at least one instruction, when executed by the one or more processors, individually or collectively, cause the electronic apparatus to: based on the electronic apparatus being turned on and the sub OS being changed from a deactivated state to an activated state, identify the context, and deactivate the network configuration function of the sub OS based on the context arising from the sub OS. (See paragraphs 79, 106, 131, Shaposhnik) Regarding claim 6, Shaposhnik teaches the electronic apparatus as claimed in claim 1, further comprising a display, wherein the at least one instruction, when executed by the one or more processors, individually or collectively, cause the electronic apparatus to:provide a user interface (UI), via the display, for selecting whether to activate the network configuration function of the sub OS, and2 based on a user selecting a control of the UT for deactivating the network configuration function of the sub OS., provide a guide UT indicating that the network configuration function of the sub OS is deactivated. (See paragraphs 149-151, fig 1, Shaposhnik) Regarding claim 7, Shaposhnik teaches the electronic apparatus as claimed in claim 1, wherein the context comprises at least one of an Internet Protocol (IP) address being assigned to the electronic apparatus or a communication connection being established with an external device. (See paragraphs 185-186, 81, Shaposhnik) Regarding claim 8, Shaposhnik teaches the electronic apparatus as claimed in claim 1, wherein the network configuration information comprises at least one of IP address information of the electronic apparatus, information corresponding to an external device connected to the electronic apparatus, or a DNS server address of the electronic apparatus. (See paragraphs 185-186, 81, Shaposhnik) Regarding claim 9, Shaposhnik teaches the electronic apparatus as claimed in claim 1, wherein the host OS and the sub OS are different types of OS. (See figure 6 and paragraphs 33-38, Shaposhnik teaches a host OS and a guest OS are different. ) Regarding claim 10, Shaposhnik teaches the electronic apparatus as claimed in claim 1, wherein the sub OS is installed in a virtualization space of the host OS, and wherein the virtualization space is implemented as a virtual machine or a virtualization container. (See figure 6 and paragraphs 37-38, Shaposhnik) Claims 11-19 list all the same elements of claims 1-9, but in method form rather than system form. Therefore, the supporting rationale of the rejection to claims 19 applies equally as well to claims 11-19. Claim 20 list all the same elements of claim 1, but in medium form rather than system form. Therefore, the supporting rationale of the rejection to claim 20 applies equally as well to claim 20. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and located in the PTO-892 form. 1.Baldassarre, U.S. Patent 10863580, teaches a user device may receive, an output stream associated with an application session, wherein the output stream is associated with imperceptible content via an output component. The user device may transmit, via a short range wireless communication component, an advertisement associated with the application session. The user device may configure a main processing thread that is associated with executing the application session to provide the output stream to the output component. The main processing thread may be configured to provide the output stream to: cause the output component to operate in association with the imperceptible content and prevent an operating system from suspending the application session while the application session is executing in a background state. 2. Mueller, U.S. Patent App 20170195201, teaches methods and systems for implementing an infrastructure management system that supports hardware failure remediation are provided. A determination is made that a failure of a hardware component has occurred. The hardware component is part of a hardware composite. A remediation attribute of the hardware composite is accessed. The remediation attribute indicates a minimum operational bar for the hardware composite. The minimum operational bar is based on health metrics or optional and required components of the hardware composite. The bar supports determining whether the hardware composite should operate in a degraded state. A determination is made that the hardware composite if operating without the hardware component that has failed meets the minimum operational bar for the hardware composite. Operation of the hardware composite in the degraded state is initiated. In embodiments, hardware managers are associated with degraded state configurations to facilitate operating the hardware composite in the degraded state. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NINOS DONABED whose telephone number is (571)272-8757. The examiner can normally be reached Monday - Friday 8:00pm - 4:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John FOLLANSBEE can be reached on (571)272-3964. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NINOS DONABED/Primary Examiner, Art Unit 2444
Read full office action

Prosecution Timeline

Jul 17, 2025
Application Filed
Oct 14, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
99%
With Interview (+64.5%)
3y 2m (~1y 11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 674 resolved cases by this examiner. Grant probability derived from career allowance rate.

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