Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim 1 to claim 20 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 to claim 20 of US 12387677. Although all of the claims at issue are not identical, they are not patentably distinct from each other because they are obvious variation of each other. As current application is the broader recitation of the patented one.
Current Application
US 12387677
1. A pixel comprising: a light emitting element connected between a first power source line, configured to provide a first power source, and a first node; a first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node; a second transistor including a first electrode electrically connected to a data line configured to provide a data signal, a second electrode electrically connected to the third node, and a gate electrode configured to receive a scan signal; a third transistor including a first electrode, a second electrode electrically connected to the first node, and a gate electrode configured to receive a compensation scan signal; a fourth transistor including a first electrode electrically connected to a reference voltage line configured to provide a reference voltage, a second electrode electrically connected to the third node, and a gate electrode configured to receive an initialization scan signal; and a first capacitor connected between the second node and the third node.
2. The pixel of claim 1, wherein the first electrode of the third transistor is electrically connected to the first power source line.
3. The pixel of claim 1, further comprising: a fifth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode configured to receive a first emission signal.
4. The pixel of claim 3, further comprising: a sixth transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a second power source line configured to provide a second power source having a voltage level lower than the first power source, and a gate electrode configured to receive a second emission signal.
5. The pixel of claim 4, wherein each of the initialization scan signal and the second emission signal is configured to be at an active level during a first period.
6. The pixel of claim 5, wherein the reference voltage is configured to be provided to the third node, and the second power source is configured to be provided to the second node during the first period.
7. The pixel of claim 5, wherein each of the initialization scan signal, the compensation scan signal, and the first emission signal are configured to be at an active level during a second period continuous with the first period.
8. The pixel of claim 7, wherein a voltage value, which is obtained by subtracting a threshold voltage of the first transistor from the reference voltage, is configured to be provided to the second node during the second period.
9. The pixel of claim 7, wherein the scan signal is configured to be at an active level during a third period continuous with the second period.
10. The pixel of claim 9, wherein the data signal is configured to be provided to the third node during the third period.
11. The pixel of claim 9, wherein each of the first emission signal and the second emission signal is configured to be at an active level during a fourth period continuous with the third period.
12. The pixel of claim 1, further comprising: a second capacitor connected between the second node and the first power source line.
13. The pixel of claim 1, wherein the first electrode of the third transistor is electrically connected to a first initialization voltage line configured to provide a first initialization voltage.
14. The pixel of claim 13, further comprising: a 2-1st capacitor connected between the second node and the first initialization voltage line.
15. The pixel of claim 13, further comprising: a 2-2nd capacitor connected between the second node and a second initialization voltage line configured to provide a second initialization voltage having a voltage level different from a voltage level of the first initialization voltage.
16. The pixel of claim 13, wherein the first initialization voltage is greater than a voltage level obtained by subtracting a threshold voltage of the first transistor from the reference voltage.
17. The pixel of claim 1, further comprising: a seventh transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a third initialization voltage line configured to provide a third initialization voltage, and a gate electrode configured to receive an input scan signal.
18. A display device comprising: a display panel including a plurality of pixels, wherein each of the plurality of pixels includes: a light emitting element connected between a first power source line, configured to provide a first power source, and a first node; a first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node; a second transistor including a first electrode electrically connected to a data line configured to provide a data signal, a second electrode electrically connected to the third node, and a gate electrode configured to receive a scan signal; a third transistor including a first electrode electrically connected to the first power source line, a second electrode electrically connected to the first node, and a gate electrode configured to receive a compensation scan signal; a fourth transistor including a first electrode electrically connected to a reference voltage line configured to provide a reference voltage, a second electrode electrically connected to the third node, and a gate electrode configured to receive an initialization scan signal; and a first capacitor connected between the second node and the third node.
19. The display device of claim 18, further comprising: a fifth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode configured to receive a first emission signal; and a sixth transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a second power source line configured to provide a second power source having a voltage level lower than the first power source, and a gate electrode configured to receive a second emission signal.
20. The display device of claim 18, further comprising: a second capacitor connected between the second node and the first power source line.
1. A pixel comprising: a light emitting element having an anode and a cathode, the anode connected to a first power source line configured to provide a first power source and the cathode connected to a first node; a first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node; a second transistor including a first electrode electrically connected to a data line configured to provide a data signal, a second electrode electrically connected to the third node, and a gate electrode configured to receive a scan signal; a third transistor including a first electrode, a second electrode electrically connected to the first node, and a gate electrode configured to receive a compensation scan signal; a fourth transistor including a first electrode electrically connected to a reference voltage line configured to provide a reference voltage, a second electrode electrically connected to the third node, and a gate electrode configured to receive an initialization scan signal; and a first capacitor connected between the second node and the third node.
2. The pixel of claim 1, wherein the first electrode of the third transistor is electrically connected to the first power source line.
3. The pixel of claim 1, further comprising: a fifth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode configured to receive a first emission signal.
4. The pixel of claim 3, further comprising: a sixth transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a second power source line configured to provide a second power source having a voltage level lower than the first power source, and a gate electrode configured to receive a second emission signal.
5. The pixel of claim 4, wherein each of the initialization scan signal and the second emission signal is configured to be at an active level during a first period.
6. The pixel of claim 5, wherein the reference voltage is configured to be provided to the third node, and the second power source is configured to be provided to the second node during the first period.
7. The pixel of claim 5, wherein each of the initialization scan signal, the compensation scan signal, and the first emission signal are configured to be at an active level during a second period continuous with the first period.
8. The pixel of claim 7, wherein a voltage value, which is obtained by subtracting a threshold voltage of the first transistor from the reference voltage, is configured to be provided to the second node during the second period.
9. The pixel of claim 7, wherein the scan signal is configured to be at an active level during a third period continuous with the second period.
10. The pixel of claim 9, wherein the data signal is configured to be provided to the third node during the third period.
11. The pixel of claim 9, wherein each of the first emission signal and the second emission signal is configured to be at an active level during a fourth period continuous with the third period.
12. The pixel of claim 1, further comprising: a second capacitor connected between the second node and the first power source line.
13. The pixel of claim 1, wherein the first electrode of the third transistor is electrically connected to a first initialization voltage line configured to provide a first initialization voltage.
14. The pixel of claim 13, further comprising: a 2-1st capacitor connected between the second node and the first initialization voltage line.
15. The pixel of claim 13, further comprising: a 2-2nd capacitor connected between the second node and a second initialization voltage line configured to provide a second initialization voltage having a voltage level different from a voltage level of the first initialization voltage.16. The pixel of claim 13, wherein the first initialization voltage is greater than a voltage level obtained by subtracting a threshold voltage of the first transistor from the reference voltage.
17. The pixel of claim 1, further comprising: a seventh transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a third initialization voltage line configured to provide a third initialization voltage, and a gate electrode configured to receive an input scan signal.
18. A display device comprising: a display panel including a plurality of pixels, wherein each of the plurality of pixels includes: a light emitting element having an anode and a cathode, the anode connected to a first power source line configured to provide a first power source and the cathode connected to a first node; a first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node; a second transistor including a first electrode electrically connected to a data line configured to provide a data signal, a second electrode electrically connected to the third node, and a gate electrode configured to receive a scan signal; a third transistor including a first electrode electrically connected to the first power source line, a second electrode electrically connected to the first node, and a gate electrode configured to receive a compensation scan signal; a fourth transistor including a first electrode electrically connected to a reference voltage line configured to provide a reference voltage, a second electrode electrically connected to the third node, and a gate electrode configured to receive an initialization scan signal; and a first capacitor connected between the second node and the third node.
19. The display device of claim 18, further comprising: a fifth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode configured to receive a first emission signal; and a sixth transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to a second power source line configured to provide a second power source having a voltage level lower than the first power source, and a gate electrode configured to receive a second emission signal.
20. The display device of claim 18, further comprising: a second capacitor connected between the second node and the first power source line.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 12-14, 18, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim (US 20160042694).
Regarding claim 1 Lim teaches a pixel (fig. 4) comprising:
a light emitting element (fig. 4, EL) connected between a first power source line (fig. 4, ELVSS), configured to provide a first power source, and a first node (fig.4, node above EL);
a first transistor (fig. 4, TD) including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node (fig.4, node above TD), and a gate electrode electrically connected to a third node (fig. 4, N1);
a second transistor (Ts) including a first electrode electrically connected to a data line (Data) configured to provide a data signal, a second electrode electrically connected to the third node (N1), and a gate electrode configured to receive a scan signal (GW);
a third transistor (T2) including a first electrode, a second electrode electrically connected to the first node (fig.4, node above EL), and a gate electrode configured to receive a compensation scan signal (GI);
a fourth transistor (fig. 4, TE) including a first electrode electrically connected to a reference voltage line (ELVDD) configured to provide a reference voltage, a second electrode electrically connected to the third node (N1), and a gate electrode configured to receive an initialization scan signal (EM); and
a first capacitor (Cst) connected between the second node (fig.4, node above TD) and the third node (fig. 4, N1).
Regarding claim 2 Lim teaches wherein the first electrode of the third transistor (T3) is electrically connected to the first power source line (ELVSS).
Regarding claim 3 Lim teaches a fifth transistor (fig. 4, T1) including a first electrode electrically connected to the first node, a second electrode electrically connected to the first electrode of the first transistor, and a gate electrode configured to receive a first emission signal (GI).
Regarding claim 12 Lim teaches a second capacitor (fig. 4, Cth) connected between the second node (fig.4, node above TD) and the first power source line (fig. 4, ELVSS).
Regarding claim 13 Lim teaches wherein the first electrode (fig. 4, lower electrode) of the third transistor (T3) is electrically connected to a first initialization voltage (Vin) line configured to provide a first initialization voltage.
Regarding claim 14 Lim teaches a 2-1st capacitor (fig. 4, Cst) connected between the second node and the first initialization voltage line (Vin).
Regarding claim 18 Lim teaches display device comprising: a display panel including a plurality of pixels (Abstract: pixel circuit and an OLED display including the same are disclosed).
The other limitations are similar to the limitations of claim 1 so rejected same way.
Regarding claim 20 Lim teaches a second capacitor (fig. 4, Cth) connected between the second node and the first power source line (ELVSS).
Allowable Subject Matter
Claims 4-11, 15-17, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Soe US 2020/0402464
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TOWFIQ ELAHI whose telephone number is (571)270-1687. The examiner can normally be reached M-F: 10AM-3PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at (571)272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TOWFIQ ELAHI/Primary Examiner, Art Unit 2625
Prosecution Insights