DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,431,872 (hereafter ‘872). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of the instant application are anticipated by the claims of ‘872. In the table below, the differences between the claims are highlighted. If the claims are identical, only the claim number is listed.
Claims of instant application
Claims of ‘872
Claim 1: A semiconductor circuit, comprising:
a calibration device, configured to continuously generate a first signal comprising a first number of bits;
an adjustment device, configured to continuously receive the first signal and generate a second signal according to last two bits of the first signal, wherein the second signal comprises a second number of bits, and the second number is different from the first number; and
a driver, electrically coupled to the adjustment device, wherein when the last two bits of the first signal are different from the last two bits of another first signal prior to the first signal and the last bit of the first signal is a high bit value, the adjustment device is configured to provide a disregarded first signal by disregarding the last bit of the first signal, and the disregarded first signal is incremented by one bit value to generate the second signal.
Claim 1: A semiconductor circuit, comprising:
a calibration device, configured to continuously generate a first signal comprising a first number of bits;
an adjustment device, configured to continuously receive the first signal and generate a second signal according to last two bits of the first signal, wherein the second signal comprises a second number of bits, and the second number is different from the first number; and
a driver, electrically coupled to the adjustment device, wherein an output resistance of the driver is controllable in response to the second signal, wherein when the last two bits of the first signal are different from the last two bits of another first signal prior to the first signal and the last bit of the first signal is a high bit value, the adjustment device is configured to provide a disregarded first signal by disregarding the last bit of the first signal, and the disregarded first signal is incremented by one bit value to generate the second signal.
Claim 2
Claim 2
Claim 3
Claim 3
Claim 4
Claim 4
Claim 5
Claim 5
Claim 6
Claim 6
Claim 7
Claim 7
Claim 8
Claim 8
Claim 9
Claim 18
Claim 10
Claim 9
Claim 11: A semiconductor circuit, comprising:
a calibration device, configured to generate a first set of signals, each comprising a first number of bits; and
an adjustment device, configured to generate a second set of signals in response to the first set of signals, wherein each of the second set of signals comprises a second number of bits, the second number is less than the first number, and the second set of signals is generated by determining whether the last two bits of two successive ones of the first set of signals are different, wherein when the last two bits are different and the last bit is a high bit value, the adjustment device is configured to remove the last bit and increment the remaining bits by one to generate the second set of signals.
Claim 10: A semiconductor circuit, comprising:
a calibration device, configured to generate a first set of signals, each comprising a first number of bits; and
an adjustment device, configured to generate a second set of signals in response to the first set of signals, wherein each of the second set of signals comprises a second number of bits, the second number is less than the first number, and the second set of signals is generated by determining whether the last two bits of two successive ones of the first set of signals are different and whether the last bit of the latter one of the two successive ones of the first set of signals is a high bit value, wherein when the last two bits are different and the last bit is a high bit value, the adjustment device is configured to remove the last bit and increment the remaining bits by one to generate the second set of signals.
Claim 12
Claim 11
Claim 13
Claim 12
Claim 14
Claim 13
Claim 15
Claim 14
Claim 16
Claim 15
Claim 17
Claim 19
Claim 18
Claim 16
Claim 19: A method for operating a semiconductor circuit, comprising: generating, by a calibration device, a first set of signals each comprising a first number of bits;
determining, by a finite state machine of an adjustment device, whether the last two bits of two successive ones of the first set of signals are different; and
generating, by the adjustment device, a second set of signals each comprising a second number of bits in response to the first set of signals, wherein when the last two bits are different and the last bit is a high bit value, removing the last bit of the high bit value and incrementing the remaining bits by one to generate the second set of signals.
Claim 17: A method for operating a semiconductor circuit, comprising: generating, by a calibration device, a first set of signals each comprising a first number of bits;
determining, by a finite state machine of an adjustment device, whether the last two bits of two successive ones of the first set of signals are different;
determining, by the FSM, whether the last bit of the latter one of the two successive ones of the first set of signals is a high bit value; and
generating, by an adjustment device, a second set of signals each comprising a second number of bits in response to the first set of signals, wherein when the last two bits are different and the last bit is a high bit value, removing the last bit of the high bit value and incrementing the remaining bits by one to generate the second set of signals.
Claim 20
Claim 20
Allowable Subject Matter
Claims 1-20 are indicated as allowable if the double patenting rejection above is overcome.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior art does not fairly teach or suggest a driver, electrically coupled to the adjustment device, wherein when the last two bits of the first signal are different from the last two bits of another first signal prior to the first signal and the last bit of the first signal is a high bit value, the adjustment device is configured to provide a disregarded first signal by disregarding the last bit of the first signal, and the disregarded first signal is incremented by one bit value to generate the second signal in combination with the limitations of claim 1.
Kuwahara et al. (U.S. Patent 8,278,973, hereafter Kuwahara) teaches a calibration device (1421, 1422; Figure 2), and adjustment device (1471, 1472; Figures 2 and 7), and a driver (130; Figure 2). Kuwahara does not specifically teach when the last two bits of the first signal are different from the last two bits of another first signal prior to the first signal and the last bit of the first signal is a high bit value, the adjustment device is configured to provide a disregarded first signal by disregarding the last bit of the first signal, and the disregarded first signal is incremented by one bit value to generate the second signal.
Claims 2-10 are indicated as allowable merely for being dependent on claim 1.
Regarding claims 11 and 19, the prior art does not fairly teach or suggest when the last two bits are different and the last bit is a high bit value, the adjustment device is configured to remove the last bit and increment the remaining bits by one to generate the second set of signals in combination with the limitations of claims 11 and 19.
Claims 12-18 and 20 are indicated as allowable merely for being dependent on claims 11 and 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN J O'TOOLE whose telephone number is (571)270-1273. The examiner can normally be reached Monday - Friday, 9:00 am - 6:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.J.O/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
Prosecution Insights