DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by In et al. CN116895255A (see English Translation on U.S. Patent Publication No. 2023/0326411, hereinafter In).
Consider claim 15, In teaches a gate driver comprising (Figure 3, 130): an input circuit configured to transmit an input signal to a first control node in response to a first clock signal (Figure 5, T1 and respective connections); a pull-up circuit configured to pull up a gate output signal to a high voltage in response to a signal of a second control node (Figure 5, T13 and respective connections); a pull-down circuit configured to pull down the gate output signal to a first low voltage in response to a signal of a third control node (Figure 5, T14 and respective connections); a node separating circuit including a control electrode configured to receive the high voltage, a first electrode connected to the first control node and a second electrode connected to the second control node (Figure 5, T3 and respective connections); a first control node control circuit configured to control a signal of the first control node in response to the signal of the third control node (Figure 5, T2 and respective connections); and a third control node control circuit configured to control the signal of the third control node in response to the signal of the first control node (Figure 5, T10 and respective connections).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 7-9, 16-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. U.S. Patent Publication No. 2017/0294165 (hereinafter Park) in view of In.
Consider claim 1, Park teaches a gate driver comprising a plurality of stages (Figure 10, 200D), wherein a stage of the plurality of stages comprises: a first transistor comprising a first sub-transistor including a control electrode connected to a first clock signal line, a first electrode connected to an input signal line and a second electrode connected to a first intermediate node (Figure 11, M1-1 and respective connections), and a second sub- transistor including a control electrode connected to the first clock signal line, a first electrode connected to the first intermediate node and a second electrode connected to a first control node (Figure 11, M1-2 and respective connections); a second transistor comprising a first sub-transistor including a control electrode connected to a third control node, a first electrode connected to the first intermediate node and a second electrode connected to the first control node (Figure 11, M2-2 and respective connections), and a second sub- transistor including a control electrode connected to the third control node, a first electrode connected to a second low voltage line and a second electrode connected to the first intermediate node (Figure 11, M2-1 and respective connections); a third transistor including a control electrode connected to a high voltage line, a first electrode connected to the first control node and a second electrode connected to a second control node (Figure 11, M6 and respective connections); a fifth transistor including a control electrode connected to the second control node, a first electrode connected to a high voltage line and a second electrode connected to a carry output terminal (Figure 11, M10 and respective connections. [0078] and figure 5, CLK2 high level during P3); a sixth transistor including a control electrode connected to the third control node, a first electrode connected to the second low voltage line and a second electrode connected to the carry output terminal (Figure 11, M11 and respective connections); a seventh transistor including a control electrode connected to the second control node, a first electrode connected to a high voltage line and a second electrode connected to a gate output terminal (Figure 11, M7 and respective connections. [0078] and figure 5, CLK2 high level during P3); and an eighth transistor including a control electrode connected to the third control node, a first electrode connected to a first low voltage line and a second electrode connected to the gate output terminal (Figure 11, M8 and respective connections).
Park does not appear to specifically disclose a fifth transistor connected to the high voltage line; a seventh transistor connected to the high voltage line.
However, in a related field of endeavor, In teaches a stage of a gate driver (abstract) and further teaches a fifth transistor connected to the high voltage line (Figure 5, T11 and VGH); a seventh transistor connected to the high voltage line (Figure 5, T13 and VGH).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide high voltage for the output units with the benefit that the eleventh transistor T11 may be turned on or turned off in correspondence with the voltage level of the second node QF. The eleventh transistor T11 may be a pull-up transistor for outputting a high-level voltage. In addition, the thirteenth transistor T13 may be turned on or turned off in correspondence with the voltage level of the second node QF. The thirteenth transistor T13 may be a pull-up transistor for outputting a high-level voltage as suggested by In.
Consider claim 2, Park and In teach all the limitations of claim 1.
Park does not appear to specifically disclose wherein the stage of the plurality of stages further comprises: a fourth transistor including a control electrode connected to the second control node, a first electrode connected to a second clock signal line and a second electrode connected to a second electrode of a first capacitor, wherein the first capacitor includes a first electrode connected to the second control node.
However, In teaches wherein the stage of the plurality of stages further comprises: a fourth transistor including a control electrode connected to the second control node, a first electrode connected to a second clock signal line and a second electrode connected to a second electrode of a first capacitor (Figure 5, T4 and respective connections), wherein the first capacitor includes a first electrode connected to the second control node (Figure 5, C2 and respective connections).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide T4 as taught by In with the benefit that when the second clock signal CLK2 is in a high-level voltage, the second node QF may be boosted to a greater voltage (for example, twice the first voltage VGH) than the first voltage VGH by the turned-on fourth transistor T4 and the second capacitor C2 as suggested by In in [0096].
Consider claim 3, Park and In teach all the limitations of claim 1. In addition, Park teaches wherein the stage of the plurality of stages further comprises a second capacitor including a first electrode connected to the second control node and a second electrode connected to the gate output terminal (Figure 11, C1 and respective connections).
Consider claim 7, Park and In teach all the limitations of claim 1.
Park does not appear to specifically disclose wherein the stage of the plurality of stages further comprises: a thirteenth transistor comprising a first sub-transistor including a control electrode connected to the first control node, a first electrode connected to the high voltage line and a second electrode connected to a thirteenth intermediate node, and a second sub-transistor including a control electrode connected to the first control node, a first electrode connected to the thirteenth intermediate node and a second electrode connected to the first intermediate node.
However, In teaches wherein the stage of the plurality of stages further comprises: a thirteenth transistor comprising a first sub-transistor including a control electrode connected to the first control node, a first electrode connected to the high voltage line and a second electrode connected to a thirteenth intermediate node (Figure 5, T15-2 and respective connections), and a second sub-transistor including a control electrode connected to the first control node, a first electrode connected to the thirteenth intermediate node and a second electrode connected to the first intermediate node (Figure 5, T15-1 and respective connections).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide T15 or controller 250 with the benefit that the leakage controller 250 may block a leakage current to the first node Q of transistors connected to the first node Q as suggested in [0113].
Consider claim 8, Park and In teach all the limitations of claim 1. In addition, Park teaches fourteenth transistor M12.
Park does not appear to specifically disclose wherein the stage of the plurality of stages further comprises: a fourteenth transistor comprising a first sub-transistor including a control electrode connected to a reset signal line, a first electrode connected to the first intermediate node and a second electrode connected to the first control node, and a second sub-transistor including a control electrode connected to the reset signal line, a first electrode connected to the first low voltage line and a second electrode connected to the first intermediate node.
However, In teaches wherein the stage of the plurality of stages further comprises: a fourteenth transistor comprising a first sub-transistor including a control electrode connected to a reset signal line, a first electrode connected to the first intermediate node and a second electrode connected to the first control node (Figure 5, T16-1 and respective connections), and a second sub-transistor including a control electrode connected to the reset signal line, a first electrode connected to the first low voltage line and a second electrode connected to the first intermediate node (Figure 5, T16-2 and respective connections).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide T16 or unit 260 as taught by In with the benefit that the reset unit 260 may reset the first node Q, based on the reset signal ESR supplied to the reset terminal RS.
Consider claim 9, Park and In teach all the limitations of claim 1. In addition, Park teaches wherein: the plurality of stages comprises a first stage, a second stage, a third stage and a fourth stage which are sequentially disposed (Figure 10, STG1-STG4), a carry signal of the first stage is connected to the second stage, a carry signal of the second stage is connected to the third stage, a carry signal of the third stage is connected to the fourth stage (Figure 10, Carry), the first clock signal line is connected to a first clock terminal of the first stage and a second clock signal line is connected to a second clock terminal of the first stage (Figure 10, GCK1, GCK2, CT1, CT2 and STG1), the second clock signal line is connected to a first clock terminal of the second stage and the first clock signal line is connected to a second clock terminal of the second stage (Figure 10, GCK1, GCK2, CT1, CT2 and STG2), the first clock signal line is connected to a first clock terminal of the third stage and the second clock signal line is connected to a second clock terminal of the third stage (Figure 10, GCK1, GCK2, CT1, CT2 and STG(n-1)), and the second clock signal line is connected to a first clock terminal of the fourth stage and the first clock signal line is connected to a second clock terminal of the fourth stage (Figure 10, GCK1, GCK2, CT1, CT2 and STGn).
Consider claim 16, it includes limitations mentioned in claim 1 and thus these limitations are rejected by the same reasoning. In addition, Park teaches an electronic device comprising: a display panel comprising a pixel (Figure 1, 1000 and PX); a gate driver configured to output a gate signal to the pixel (Figure 1, 200); and a data driver configured to output a data voltage to the pixel (Figure 1, 300).
Consider claim 17, it includes limitations mentioned in claim 2 and thus these limitations are rejected by the same reasoning.
Consider claim 18, it includes limitations mentioned in claim 3 and thus these limitations are rejected by the same reasoning.
Consider claim 20, Park and In teach all the limitation of claim 16. In addition, Park teaches a display apparatus and further comprising: a driving controller configured to control the gate driver and the data driver (Figure 1, 400 and 200-300); and a processor configured to output input image data to the driving controller ([0049], the controller 400 may receive input image data DATA and control signals CNT from outside of the display device 1000 (e.g., a system board).
Claim(s) 4-5 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and In as applied to claim 1 above, and further in view of Yoon et al. U.S. Patent Publication No. 2008/0278214 (hereinafter Yoon).
Consider claim 4, Park and In teach all the limitations of claim 1.
Park does not appear to specifically disclose wherein the stage of the plurality of stages further comprises: a ninth transistor comprising a first sub-transistor including a control electrode connected to the high voltage line, a first electrode connected to a first node and a second electrode connected to a ninth intermediate node, and a second sub-transistor including a control electrode to the high voltage line, a first electrode connected to the ninth intermediate node and a second electrode connected to the high voltage line; and a tenth transistor including a control electrode connected to the first node, a first electrode connected to the high voltage line and a second electrode connected to the third control node.
However, in a related field of endeavor, Yoon teaches a gate driving circuit in figure 3 and further teaches a ninth transistor T1 and tenth transistor T3. Thus, the combination of Park and Yoon teach wherein the stage of the plurality of stages further comprises: a ninth transistor comprising a first sub-transistor including a control electrode connected to the high voltage line, a first electrode connected to a first node and a second electrode connected to a ninth intermediate node, and a second sub-transistor including a control electrode to the high voltage line, a first electrode connected to the ninth intermediate node and a second electrode connected to the high voltage line (Park teaches in [0107], a plurality of transistors that are connected to each other in series in order to reduce leakage current. Thus, if two transistors are connected in series in T1, Yoon’s Figure 3, as suggested by Park. Then Park and Yoon meet this limitation. In addition, CLK1 comprises a high voltage as shown in Yoon’s figure 5); and a tenth transistor including a control electrode connected to the first node, a first electrode connected to the high voltage line and a second electrode connected to the third control node (Yoon’s figure 3, T3).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide T1-T4 and C2 as a switching section with the benefit that the switching section 250 controls on/off switching of the fourth holding section 248 as suggested in [0073].
Consider claim 5, Park, In and Yoon teach all the limitations of claim 4. In addition, Yoon teaches wherein the stage of the plurality of stages further comprises a third capacitor including a first electrode connected to the first node and a second electrode connected to the third control node (Figure 3, C2 and respective connections, see motivation to combine in claim 4).
Consider claim 19, it includes limitations mentioned in claim 4 and thus these limitations are rejected by the same reasoning.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, In and Yoon as applied to claim 5 above, and further in view of Minwoo EP4539031A1 (hereinafter Minwoo).
Consider claim 6, Park, In and Yoon teach all the limitations of claim 5.
Yoon does not appear to specifically disclose an eleventh transistor including a control electrode connected to the first control node, a first electrode connected to the first low voltage line and a second electrode connected to the first node; and a twelfth transistor including a control electrode connected to the first control node, a first electrode connected to the second low voltage line and a second electrode connected to the third control node.
However, in a related field of endeavor, Minwoo teaches a stage of a gate driver in figure 3 and further teaches an eleventh transistor including a control electrode connected to the first control node, a first electrode connected to the first low voltage line and a second electrode connected to the first node (Figure 3, T12 and respective connections); and a twelfth transistor including a control electrode connected to the first control node, a first electrode connected to the second low voltage line and a second electrode connected to the third control node (Figure 3, T13 and respective connections).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide T12 and T13 as taught by Minwoo with the benefit that T12 applies low voltage VGL to the control electrode of the tenth transistor T10 in response to the signal of the Q node. In addition, T13 applies second low voltage VGL2 to the QB node in response to the signal of the Q node as suggested in [0082] and [0095].
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and In as applied to claim 9 above, and further in view of Han U.S. Patent Publication No. 2011/0102398 (hereinafter Han).
Consider claim 10, Park and In teach all the limitations of claim 9. In addition, Park teaches a gate driver 200d in figure 10
Park does not appear to specifically disclose wherein: a cycle of a first clock signal of the first clock signal line is two horizontal periods, a cycle of a second clock signal of the second clock line signal is two horizontal periods, and a high period of a pulse of a output signal is two horizontal periods.
However, in a related field of endeavor, Han teaches stages 321-325 and further teaches wherein: a cycle of a first clock signal of the first clock signal line is two horizontal periods (Figure 5, CLK1), a cycle of a second clock signal of the second clock line signal is two horizontal periods (Figure 5, CLk2), and a high period of a pulse of a output signal is two horizontal periods (Figure 5, E1-E5).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide 2H periods as taught by Han with the benefit that the start pulse SP is supplied, e.g., has a low level, during two horizontal periods 2H, and thus, the emission control signal respectively to the emission control lines E1 to E5 is supplied, e.g., has a high level, during two horizontal periods 2H. In the exemplary embodiment of FIG. 8, the start pulse SP is supplied, e.g., has a low level, during four horizontal periods 4H, and thus, the emission control signal respectively to the emission control lines E1 to E5 is supplied, e.g., has a high level, during four horizontal periods 4H. Therefore, it is possible to arbitrarily adjust a width of the emission control signal EMI by controlling a width of the start signal SP supplied from the timing controller 60 as suggested in [0118].
Consider claim 11, Park, In and Han teach all the limitations of claim 10. In addition, Park teaches wherein a high period of the first clock signal does not overlap a high period of the second clock signal (Figure 5, CLK1-CLK2), see motivation to combine in claim 10.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park and In as applied to claim 1 above, and further in view of Park et al. U.S. Patent Publication No. 2021/0082346 (hereinafter Park2).
Consider claim 12, Park and In teach all the limitations of claim 1.
Park does not appear to specifically disclose wherein: the plurality of stages comprises a first stage, a second stage, a third stage and a fourth stage which are sequentially disposed, a carry signal of the first stage is connected to the third stage, a carry signal of the second stage is connected to the fourth stage, the first clock signal is applied to a first clock terminal of the first stage and a second clock signal is applied to a second clock terminal of the first stage, a third clock signal is applied to a first clock terminal of the second stage and a fourth clock signal is applied to a second clock terminal of the second stage, the second clock signal is applied to a first clock terminal of the third stage and the first clock signal is applied to a second clock terminal of the third stage, and the fourth clock signal is applied to a first clock terminal of the fourth stage and the third clock signal is applied to a second clock terminal of the fourth stage.
However, in a related field of endeavor, Park2 teaches a gate driver 110 in figure 6 and further teaches wherein: the plurality of stages comprises a first stage, a second stage, a third stage and a fourth stage which are sequentially disposed (Figure 6, ST1-ST4), a carry signal of the first stage is connected to the third stage, a carry signal of the second stage is connected to the fourth stage (Figure 6, see carry signal corresponding to ST1-ST2), the first clock signal is applied to a first clock terminal of the first stage and a second clock signal is applied to a second clock terminal of the first stage (Figure 6, CLK1, CLK3 and ST1), a third clock signal is applied to a first clock terminal of the second stage and a fourth clock signal is applied to a second clock terminal of the second stage (Figure 6, CLK2, CLK4 and ST2), the second clock signal is applied to a first clock terminal of the third stage and the first clock signal is applied to a second clock terminal of the third stage (Figure 6, CLK3, CLK1 and ST3), and the fourth clock signal is applied to a first clock terminal of the fourth stage and the third clock signal is applied to a second clock terminal of the fourth stage (Figure 6, CLK4, CLK2 and ST4).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a gate driver as shown in figure 6 with the benefit that a gate start pulse GSP is supplied to the first input terminals 101 of the first stage ST1 and the second stage ST2. In addition, the first input terminal 101 of each of the other stages ST3 to STn except the first stage ST1 and the second stage ST2 is supplied with a sampling pulse SP (or a scan signal) of a previous stage as suggested in [0113].
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, In and Park2 as applied to claim 12 above, and further in view of Han
Consider claim 13, Park, In and Park2 teach all the limitations of claim 12. In addition, Park2 teaches wherein: a cycle of the first clock signal is four horizontal periods, a cycle of the second clock signal is four horizontal periods, a cycle of the third clock signal is four horizontal periods, a cycle of the fourth clock signal is four horizontal periods (Figure 7, CLK1-CLK4), and a high period of a pulse of a gate output signal (Figure 7, SS1).
Park2 does not appear to specifically disclose a high period of a pulse of output signal is four horizontal periods.
However, Han teaches a high period of a pulse of output signal is four horizontal periods (Figure 8, E1-E5).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a gate with 4H periods as taught by Han with the benefit that the start pulse SP is supplied, e.g., has a low level, during two horizontal periods 2H, and thus, the emission control signal respectively to the emission control lines E1 to E5 is supplied, e.g., has a high level, during two horizontal periods 2H. In the exemplary embodiment of FIG. 8, the start pulse SP is supplied, e.g., has a low level, during four horizontal periods 4H, and thus, the emission control signal respectively to the emission control lines E1 to E5 is supplied, e.g., has a high level, during four horizontal periods 4H. Therefore, it is possible to arbitrarily adjust a width of the emission control signal EMI by controlling a width of the start signal SP supplied from the timing controller 60 as suggested in [0118].
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Prior arts do not appear to disclose the overlap periods of the clocks in combination to other limitations of the base claim and any intervening claims
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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