DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been examined.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(a)-(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application claims priority to U.S. Provisional Application 63/532,941, filed August 16, 2023.
Information Disclosure Statement
The Applicant's submission of the Information Disclosure Statement dated July 18, 2025 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending. A copy of the PTOL-1449 initialed and dated by the Examiner is attached to the instant office action.
Specification
The disclosure is objected to because of the following informalities.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Double Patenting
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims of U.S. Patent No. 12,373,216. Although the claims at issue are not identical, they are not patentably distinct from each other because corresponding claims of the reference patent include all features of the claims of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 6,851,046 by Delvaux et al. (hereinafter referred to as “Delvaux”) in view of US Patent No. 11,132,200 by Chavan et al. (hereinafter referred to as “Chavan”).
Regarding claim 1, Delvaux discloses:
a system comprising: a memory adapted to store a first instruction, wherein the first instruction specifies two or more destinations, and wherein each destination of the two or more destinations corresponds to a respective condition of two or more conditions (Delvaux discloses, at col. 4, line 45-col. 5, line 5, an instruction that specifies multiple destinations that each correspond to a respective condition.); and
circuitry coupled to the memory and adapted to: fetch the first instruction from the memory (Delvaux discloses at col. 5, lines 58-63, the instruction is retrieved from memory.); and
compare an …[value] to each condition of the two or more conditions (Delvaux discloses, at col. 4, line 45-col. 5, line 5, comparing a value to evaluate the conditions.);
select a destination of the two or more destinations based on comparing of the …[value] to each condition of the two or more conditions (Delvaux discloses, at col. 4, line 45-col. 5, line 14, selecting one of the targets based on the evaluation of the conditions.); and
fetch a second instruction from the memory using the selected destination (Delvaux discloses, at col. 4, line 45-col. 5, line 14, jumping to the selected target, which discloses fetching an instruction from memory using the selected destination.).
Delvaux does not explicitly disclose the aforementioned value is an iteration count.
However, in the same field of endeavor (e.g., branches) Chavan discloses:
using an iteration count as a condition for branching (Chavan discloses, at col. 7, lines 10-14, a count of remaining iterations determines whether to branch or not.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux’s conditional branch to use an iteration count, as disclosed by Chavan, using loops is a common mechanism that allows for efficient processing of repetitive tasks, and loop (iteration) counts are a simple way to control loops. See Chavan, col. 1, lines 15-25.
Regarding claim 2, Delvaux, as modified, discloses the elements of claim 1, as discussed above. Delvaux also discloses:
the circuitry is adapted to compare the …[value] to a first condition of the two or more conditions (Delvaux discloses, at col. 4, line 45-col. 5, line 5, comparing a value to evaluate the conditions.),
wherein the first condition corresponds to a first destination of the two or more destinations (Delvaux discloses, at col. 4, line 45-col. 5, line 14, selecting one of the targets based on the evaluation of the conditions.),
wherein the circuitry is adapted to compare the …[value] to a second condition of the two or more conditions (Delvaux discloses, at col. 4, line 45-col. 5, line 5, comparing a value to evaluate the conditions.), and
wherein the second condition corresponds to a second destination of the two or more destinations (Delvaux discloses, at col. 4, line 45-col. 5, line 14, selecting one of the targets based on the evaluation of the conditions.).
Delvaux does not explicitly disclose the aforementioned value is an iteration count.
However, in the same field of endeavor (e.g., branches) Chavan discloses:
using an iteration count as a condition for branching (Chavan discloses, at col. 7, lines 10-14, a count of remaining iterations determines whether to branch or not.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux’s conditional branch to use an iteration count, as disclosed by Chavan, using loops is a common mechanism that allows for efficient processing of repetitive tasks, and loop (iteration) counts are a simple way to control loops. See Chavan, col. 1, lines 15-25.
Regarding claim 3, Delvaux, as modified, discloses the elements of claim 1, as discussed above. Delvaux also discloses:
Regarding claim 4, Delvaux, as modified, discloses the elements of claim 3, as discussed above. Delvaux does not explicitly disclose the iteration count relates to a number of remainder operations after performing a loop instruction a number of times.
However, in the same field of endeavor (e.g., branches) Chavan discloses:
using an iteration count that corresponds to a remaining number of iterations (Chavan discloses, at col. 7, lines 10-14, a count of remaining iterations determines whether to branch or not.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux’s conditional branch to use an iteration count, as disclosed by Chavan, using loops is a common mechanism that allows for efficient processing of repetitive tasks, and loop (iteration) counts are a simple way to control loops. See Chavan, col. 1, lines 15-25.
Regarding claim 5, Delvaux, as modified, discloses the elements of claim 3, as discussed above. Delvaux does not explicitly disclose the circuitry is adapted to: perform the loop instruction the number of times, and decrement the iteration count each time the circuitry performs the loop instruction.
However, in the same field of endeavor (e.g., branches) Chavan discloses:
performing a loop a number of times and decrementing the loop counter (Chavan discloses, at col. 7, performing a loop a number of times and decrementing the loop counter.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to include the looping mechanism disclosed by Chavan because using loops is a common mechanism that allows for efficient processing of repetitive tasks, and loop (iteration) counts are a simple way to control loops. See Chavan, col. 1, lines 15-25.
Regarding claim 9, Delvaux discloses:
a method comprising: fetching a first instruction, wherein the first instruction specifies two or more destinations, and wherein each destination of the two or more destinations corresponds to a respective condition of two or more conditions (Delvaux discloses, at col. 4, line 45-col. 5, line 5, an instruction that specifies multiple destinations that each correspond to a respective condition. Delvaux discloses at col. 5, lines 58-63, fetching the instruction from memory.); and
comparing …[a value] to each condition of the two or more conditions (Delvaux discloses, at col. 4, line 45-col. 5, line 5, comparing a value to evaluate the conditions.),
selecting a destination of the two or more destinations based on comparing of the …[value] to each condition of the two or more conditions (Delvaux discloses, at col. 4, line 45-col. 5, line 14, selecting one of the targets based on the evaluation of the conditions.); and
fetching a second instruction using the selected destination (Delvaux discloses, at col. 4, line 45-col. 5, line 14, jumping to the selected target, which discloses fetching an instruction from memory using the selected destination.).
Delvaux does not explicitly disclose the aforementioned value is an iteration count.
However, in the same field of endeavor (e.g., branches) Chavan discloses:
using an iteration count as a condition for branching (Chavan discloses, at col. 7, lines 10-14, a count of remaining iterations determines whether to branch or not.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux’s conditional branch to use an iteration count, as disclosed by Chavan, using loops is a common mechanism that allows for efficient processing of repetitive tasks, and loop (iteration) counts are a simple way to control loops. See Chavan, col. 1, lines 15-25.
Regarding claim 10, Delvaux, as modified, discloses the elements of claim 9, as discussed above. Delvaux also discloses:
comparing the …[value] to each condition of the two or more conditions includes: comparing the …[value] to a first condition (Delvaux discloses, at col. 4, line 45-col. 5, line 5, comparing a value to evaluate the conditions.), and
comparing the …[value] to a second condition (Delvaux discloses, at col. 4, line 45-col. 5, line 5, comparing a value to evaluate the conditions.),
wherein the first condition corresponds to a first destination of the two or more destinations (Delvaux discloses, at col. 4, line 45-col. 5, line 14, selecting one of the targets based on the evaluation of the conditions.), and
wherein the second condition corresponds to a second destination of the two or more destinations (Delvaux discloses, at col. 4, line 45-col. 5, line 14, selecting one of the targets based on the evaluation of the conditions.).
Regarding claim 11, Delvaux, as modified, discloses the elements of claim 9, as discussed above. Delvaux does not explicitly disclose the iteration count relates to a number of remainder operations after performing a loop instruction a number of times.
However, in the same field of endeavor (e.g., branches) Chavan discloses:
using an iteration count that corresponds to a remaining number of iterations (Chavan discloses, at col. 7, lines 10-14, a count of remaining iterations determines whether to branch or not.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux’s conditional branch to use an iteration count, as disclosed by Chavan, using loops is a common mechanism that allows for efficient processing of repetitive tasks, and loop (iteration) counts are a simple way to control loops. See Chavan, col. 1, lines 15-25.
Regarding claim 12, Delvaux, as modified, discloses the elements of claim 11, as discussed above. Delvaux also discloses:
fetching the loop instruction (Delvaux discloses at col. 5, lines 58-63, instructions are retrieved from memory.).
Regarding claim 13, Delvaux, as modified, discloses the elements of claim 11, as discussed above. Delvaux does not explicitly disclose performing the loop instruction the number of times, and decrementing the iteration count each time the loop instruction is performed.
However, in the same field of endeavor (e.g., branches) Chavan discloses:
performing a loop a number of times and decrementing the loop counter (Chavan discloses, at col. 7, performing a loop a number of times and decrementing the loop counter.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to include the looping mechanism disclosed by Chavan because using loops is a common mechanism that allows for efficient processing of repetitive tasks, and loop (iteration) counts are a simple way to control loops. See Chavan, col. 1, lines 15-25.
Claims 6-8 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 6,851,046 by Delvaux et al. (hereinafter referred to as “Delvaux”) in view of US Patent No. 11,132,200 by Chavan et al. (hereinafter referred to as “Chavan”).
Regarding claim 6, Delvaux, as modified, discloses the elements of claim 3, as discussed above. Delvaux does not explicitly disclose the first instruction specifies the number of times for performing the loop instruction.
However, in the same field of endeavor (e.g., loops) Ould discloses:
an instruction specifies the number of times for performing the loop instruction (Ould discloses, at ¶ [0070], an instruction that specifies a register that stores a number of iterations in a loop, which specifies the number of times for performing the loop instruction.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to specify a loop count in an instruction, as disclosed by Ould, because doing so provides quick access to control information.
Regarding claim 7, Delvaux, as modified, discloses the elements of claim 1, as discussed above. Delvaux does not explicitly disclose the first instruction specifies the iteration count.
However, in the same field of endeavor (e.g., loops) Ould discloses:
an instruction specifies the iteration count (Ould discloses, at ¶ [0070], an instruction that specifies a register that stores an iteration count, which specifies the iteration count.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to specify an iteration count in an instruction, as disclosed by Ould, because doing so provides quick access to control information.
Regarding claim 8, Delvaux, as modified, discloses the elements of claim 1, as discussed above. Delvaux does not explicitly disclose the first instruction specifies a location where the iteration count is stored.
However, in the same field of endeavor (e.g., loops) Ould discloses:
an instruction that specifies a location where the iteration count is stored (Ould discloses, at ¶ [0070], an instruction that specifies a register that stores an iteration count, which specifies a location where the iteration count is stored.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to specify a location of an iteration count in an instruction, as disclosed by Ould, because doing so provides quick access to control information.
Regarding claim 14, Delvaux, as modified, discloses the elements of claim 11, as discussed above. Delvaux also discloses:
Delvaux does not explicitly disclose the first instruction specifies the number of times for performing the loop instruction.
However, in the same field of endeavor (e.g., loops) Ould discloses:
an instruction specifies the number of times for performing the loop instruction (Ould discloses, at ¶ [0070], an instruction that specifies a register that stores a number of iterations in a loop, which specifies the number of times for performing the loop instruction.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to specify a loop count in an instruction, as disclosed by Ould, because doing so provides quick access to control information.
Regarding claim 15, Delvaux, as modified, discloses the elements of claim 9, as discussed above. Delvaux also discloses:
Delvaux does not explicitly disclose the first instruction specifies the iteration count.
However, in the same field of endeavor (e.g., loops) Ould discloses:
an instruction specifies the iteration count (Ould discloses, at ¶ [0070], an instruction that specifies a register that stores an iteration count, which specifies the iteration count.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to specify an iteration count in an instruction, as disclosed by Ould, because doing so provides quick access to control information.
Regarding claim 16, Delvaux, as modified, discloses the elements of claim 9, as discussed above. Delvaux also discloses:
Delvaux does not explicitly disclose the first instruction specifies a location where the iteration count is stored.
However, in the same field of endeavor (e.g., loops) Ould discloses:
an instruction that specifies a location where the iteration count is stored (Ould discloses, at ¶ [0070], an instruction that specifies a register that stores an iteration count, which specifies a location where the iteration count is stored.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to specify a location of an iteration count in an instruction, as disclosed by Ould, because doing so provides quick access to control information.
Regarding claim 17, Delvaux discloses:
a device comprising: a memory… (Delvaux discloses, at Figure 1D, a processor having memory to store control information, e.g., a jump address register and program counter storage.); and
circuitry coupled to the memory and adapted to: fetch a first instruction, wherein the first instruction specifies … two or more destinations (Delvaux discloses, at col. 4, line 45-col. 5, line 5, an instruction that specifies multiple destinations that each correspond to a respective condition. Delvaux discloses at col. 5, lines 58-63, fetching the instruction from memory.); and
select a destination of the two or more destinations based on the iteration count (Delvaux discloses, at col. 4, line 45-col. 5, line 14, selecting one of the targets based on the evaluation of the conditions.); and
fetch a second instruction using the selected destination (Delvaux discloses, at col. 4, line 45-col. 5, line 14, jumping to the selected target, which discloses fetching an instruction from memory using the selected destination.).
Delvaux does not explicitly disclose the aforementioned memory is adapted to store an iteration count at a location, wherein the iteration count relates to a number of remainder operations after performing a loop instruction a number of times and the aforementioned instruction includes the location.
However, in the same field of endeavor (e.g., branches) Chavan discloses:
using an iteration count that corresponds to a remaining number of iterations (Chavan discloses, at col. 7, lines 10-14, a count of remaining iterations determines whether to branch or not, which discloses storing the iteration count at a location.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux’s conditional branch to use an iteration count, as disclosed by Chavan, using loops is a common mechanism that allows for efficient processing of repetitive tasks, and loop (iteration) counts are a simple way to control loops. See Chavan, col. 1, lines 15-25.
Also in the same field of endeavor (e.g., loops) Ould discloses:
an instruction that specifies a location where the iteration count is stored (Ould discloses, at ¶ [0070], an instruction that specifies a register that stores an iteration count, which specifies a location where the iteration count is stored.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to specify a location of an iteration count in an instruction, as disclosed by Ould, because doing so provides quick access to control information.
Regarding claim 18, Delvaux, as modified, discloses the elements of claim 17, as discussed above. Delvaux also discloses:
Delvaux does not explicitly disclose performing the loop instruction the number of times, and decrementing the iteration count each time the loop instruction is performed.
However, in the same field of endeavor (e.g., branches) Chavan discloses:
performing a loop a number of times and decrementing the loop counter (Chavan discloses, at col. 7, performing a loop a number of times and decrementing the loop counter.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to include the looping mechanism disclosed by Chavan because using loops is a common mechanism that allows for efficient processing of repetitive tasks, and loop (iteration) counts are a simple way to control loops. See Chavan, col. 1, lines 15-25.
Regarding claim 19, Delvaux, as modified, discloses the elements of claim 17, as discussed above. Delvaux also discloses:
Delvaux does not explicitly disclose the first instruction specifies the number of times for performing the loop instruction.
However, in the same field of endeavor (e.g., loops) Ould discloses:
an instruction specifies the number of times for performing the loop instruction (Ould discloses, at ¶ [0070], an instruction that specifies a register that stores a number of iterations in a loop, which specifies the number of times for performing the loop instruction.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Delvaux to specify a loop count in an instruction, as disclosed by Ould, because doing so provides quick access to control information.
Regarding claim 20, Delvaux, as modified, discloses the elements of claim 17, as discussed above. Delvaux also discloses:
the memory is a first memory, and wherein the device further comprises a second memory adapted to store the first instruction and the second instruction (It is inherent that the memory is a first memory. Delvaux also discloses, at col. 5, lines 58-63, the instruction is retrieved from memory, which discloses a second memory.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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