DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 21, 2026 has been entered.
Response to Arguments
RE: the objection to claim 7, Applicant’s arguments and amendments have been fully considered and have resolved the typographical issue in this claim. Accordingly, the objection to claim 7 is withdrawn.
RE: the rejection of claims 1, 3-10, 12-13 under 35 USC 103, Applicant’s arguments and amendments have been fully considered but are not persuasive.
As further discussed below, in claim 1, the word “contact” in the limitation “the body of source material and the source carrier reservoir each being in contact with the metal-oxide semiconductor channel material” is interpreted to mean “indirect contact” under a broad reasonable interpretation. This interpretation is consistent with dependent claim 7 which includes a source-channel interface at the body of source material and contacting the channel material as such source-channel interface would prevent the body of source material from directly contacting the channel material.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-4, 7, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2023/285936A1 (“Barlage”) in view of US 20140021481 A1 (“Lee”), further in view of US 20110116310 A1 (“Yamazaki”).
RE Claim 1, Barlage discloses A method of making a thin-film transistor (200a in FIG. 2a), the method comprising:
forming a structure of layers (204, 203, 222, 214, 216) between and over a source (source 206 includes source contact 207 and source electrode 208, [0068]) and a drain (drain 210 includes drain contact 211 and drain electrode 212, [0068]; Please note as claimed, the structure of layers, and not necessarily each layer of the structure of layers, is required to be between and over the source and drain; In FIG. 2a, portions of 216 are between and over 207, 211; Accordingly, the structure of layers that includes 204, 203, 222, 214, 216 is between and over 207, 211), the source including a body of source material (source contact 207 can be a metal or doped semiconductor, [0073]),
the structure of layers including a layer of metal-oxide semiconductor channel material (216 includes zinc oxide, tin oxide, indium gallium zinc oxide, gallium oxide, [0070]; channel is formed in 216, [0074]), a layer of dielectric material (214 is a dielectric layer, [0069]), and a layer of gate material (203, 204; 203 is a gate contact, [0068]; 204 is a gate electrode, [0068]),
the body of source material being in contact with the metal-oxide semiconductor channel material (FIG. 2a shows source contact 207 being in indirect contact with 216 through interfacial member 250, see further discussion of the interpretation of “contact” below).
Barlage does not explicitly disclose:
the source (206 including 207, 208) includes a source carrier reservoir that overlies the body of source material;
the source carrier reservoir being in contact with the metal-oxide semiconductor channel material;
planarizing the structure to remove portions of the layers that overlie the source and the drain; and
stopping planarizing at the source carrier reservoir.
However, Barlage discloses source electrode 208 can be selected from a material better suited to connection to other components of a circuit, [0068].
In the same field of endeavor, Lee discloses the source electrode 294, the drain electrode 295 may be made of, e.g., Nickel (Ni), aluminum (Al), titanium (Ti), titanium nitride (TiN), platinum (Pt), gold (Au), ruthenium oxide (RuO.sub.2), vanadium (V), tungsten (W), tungsten nitride (WN), hafnium (HO, hafnium nitride (HfN), molybdenum (Mo), nickel silicide (NiSi), cobalt silicide (CoSi.sub.2), tungsten silicide (WSi), platinum silicide (PtSi), iridium (Ir), zirconium (Zr), tantalum (Ta), tantalum nitride (TaN), copper (Cu), ruthenium (Ru), cobalt (Co), and/or combinations thereof, [0076].
Accordingly, there was a need to select a material of the source electrode 208 before the effective filing date of the claimed invention.
It would have been obvious to use titanium nitride as the material for the source electrode 208 as this would have been obvious to try since titanium nitride is one solution for the material in a source electrode identified by Lee and this would have had a reasonable expectation of success, see MPEP 2143.
As the instant specification discloses “other examples of materials that may be used for the source carrier reservoir 46 include titanium nitride”, [0041], the material titanium nitride is considered a source carrier reservoir material.
Accordingly, as modified, the source electrode 208 made of titanium nitride would correspond to the claimed source carrier reservoir that overlies the body of source material 207.
Note the word “contact” is not defined in the instant specification.
However, the reference US20210343661 A1 discloses Among the layers 202 discussed herein, adjacent ones of the layers 202 may be in direct contact with each other, which means there are no intervening layers (not shown), or in indirect contact with each other, which means there are one or more intervening layers, [0039].
The reference US20160233210 A1 discloses As used herein, a layer that is “on” an underlying layer can be in direct contact with the underlying layer or in indirect contact with the underlying layer wherein one or more intervening layers are between the layer and the underlying layer, [0073].
The reference US20180337743A1 states One layer “over”, “spanning”, or “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers, [0015].
Accordingly, under a broad reasonable interpretation, the term “contact” is interpreted to mean “indirect contact” where one or more intervening layers are present. Accordingly, the source contact 207, source electrode 208 are each in indirect contact with the channel 216.
In the same field of endeavor, Yamazaki discloses openings that reach the metal compound regions 124 are formed in the interlayer insulating layers, and the source and drain electrodes 130 a and 130 b are formed in the openings (see FIG. 3H). The source and drain electrodes 130 a and 130 b can be formed in such a manner, for example, that a conductive layer is formed in a region including the openings by a PVD method, a CVD method, or the like and then part of the conductive layer is removed by etching, CMP, or the like, [0099], see FIG. 3H.
Yamazaki further discloses where the source and drain electrodes 130 a and 130 b are formed by removing part of the conductive layer, the process is preferably performed so that the surfaces are planarized. For example, when a thin titanium film or a thin titanium nitride film is formed in a region including the openings and then a tungsten film is formed so as to be embedded in the openings, an unnecessary part of the tungsten film, the titanium film, the titanium nitride film, or the like is removed and the planarity of the surface can be improved by subsequent CMP. By planarizing the surface including the source and drain electrodes 130 a and 130 b in such a manner, an electrode, a wiring, an insulating layer, a semiconductor layer, and the like can be favorably formed in later steps, [0100].
FIG. 3H shows the source and drain electrodes 130a, 130b are formed in interlayer insulating layers 126, 128, [0098].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form source and drain electrodes 208, 212 within interlayer insulating layers and to planarize the surfaces of the source and drain electrodes 208, 212 as taught by Yamazaki in order to more favorably or easily form wiring or insulating layers in later steps as further taught by Yamazaki.
As a result, the interlayer insulating layers would be included in the claimed structure of layers, and portions of the interlayer insulating layers that overlie the source and drain 206, 210 in Barlage would be removed during planarization by etching or CMP (see Yamazaki, [0099]-[0100]); further, uppermost portions of the source and drain electrodes 208, 212 of the structure of layers that overlie lower portions of source and drain 206, 210 and/or overlie source and drain contacts 207, 211 would be removed during the planarization by etching or CMP, and planarization would stop at the source carrier reservoir 208.
RE: Claim 3, Barlage in view of Lee, Yamazaki discloses The method of claim 1, wherein the planarizing includes etching (Yamazaki discloses source and drain electrodes 130 a and 130 b can be formed in such a manner, for example, that a conductive layer is formed in a region including the openings by a PVD method, a CVD method, or the like and then part of the conductive layer is removed by etching, [0099]; Accordingly, as modified, planarization would include etching the conductive material of the source and drain electrodes 208, 212).
RE: Claim 4, Barlage in view of Lee, Yamazaki discloses The method of claim 1, wherein the planarizing includes chemical mechanical polishing (Yamazaki discloses the planarization of the conductive layer of the source and drain electrodes includes CMP, [0099]; the planarity of the source and drain electrodes can be improved by subsequent CMP, [0100]; the reference US 20240015985 A1 (“Young”) identifies CMP as chemical mechanical polishing, [0039]; Accordingly, one of ordinary skill in the art would understand CMP to mean chemical mechanical polishing).
RE: Claim 7, Barlage in view of Lee, Yamazaki discloses The method of claim 1, further comprising forming a source-channel interface (In Barlage FIG. 2a: the left portion of 250 adjacent to 207 and in direct contact with 216) at the body of source material of the source, the source-channel interface contacting the metal-oxide semiconductor channel material and being operable to deplete a region of the metal-oxide semiconductor channel material when the thin-film transistor is off (Barlage discloses 250 is provided to create a repository of complimentary excess negative charge that functions to deplete the channel in at least the region of semiconductor layer 216 adjacent source contact 207. In this manner, source-channel interfacial member 250 serves as an electron transport barrier, resulting in substantially no current flow through semiconductor layer 216 when TFT 200 a is in a ‘OFF’ state, [0074], [0085]).
RE: Claim 9, Barlage in view of Lee, Yamazaki discloses The method of claim 7, further comprising forming a drain-channel interface (In Barlage FIG. 2a: the right portion of 250 adjacent to 211 and in direct contact with 216) at a body of drain material (drain contact 211, [0068]) of the drain, the drain-channel interface being formed in the same manner as the source-channel interface (Barlage discloses source-channel interfacial member 250 has been formed as a continuous member extending from source contact 207 to drain contact 211, [0078]; Accordingly, both left and right portions of 250 were formed in the same continuous manner and as part of the same layer 250).
Claim 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Barlage in view of Lee, further in view of Yamazaki as applied to claim 1, further in view of US 20200083259 A1 (“Huang”).
RE: Claim 5, Barlage in view of Lee, Yamazaki does not explicitly disclose The method of claim 1, further comprising:
forming an adhesion layer of tin oxide on a substrate; and
forming bodies of source and drain material on the adhesion layer;
wherein the adhesion layer promotes adhesion of the bodies of source and drain material to the substrate.
However, Barlage discloses insulation layer 218 is made of silicon dioxide (SiO2), [0083].
Barlage further discloses source contact 207, drain contact 211 are made of copper, [0073].
In the same field of endeavor, Huang discloses buffer layer 7 is coated on the surface of the source-drain electrode 5, and the buffer layer 7 is configured for improving the adhesion between the source-drain electrode 5 and the passivation layer 6, [0073].
Huang further discloses passivation layer 6 is silicon oxide, source electrode 5 is copper, and buffer layer 7 is ITO, [0060], [0062], [0064].
Huang teaches ITO is indium tin oxide, [0062].
Huang further teaches The oxide conductor ITO layer is added on the surface of Cu to solve the problem of poor adhesion between Cu and silicon oxide, [0064].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce a buffer layer of indium tin oxide between the insulation layer 218 and the source/drain contacts 207, 211 as taught by Huang in order to improve adhesion between the insulation layer 218 and the source/drain contacts 207, 211.
Barlage, in view of Lee, Yamazaki, and further in view of Huang discloses:
forming an adhesion layer of tin oxide on a substrate (buffer layer of ITO would be formed on Barlage’s insulation layer 218 in FIG. 2a of Barlage); and
forming bodies of source and drain material on the adhesion layer (Barlage’s source/drain 207, 211 would be formed on the ITO);
wherein the adhesion layer promotes adhesion of the bodies of source and drain material to the substrate (the buffer layer would improve adhesion between the insulation layer 218 and the source/drain contacts 207, 211).
RE: Claim 6, Barlage in view of Lee, Yamazaki, Huang discloses The method of claim 5, wherein the substrate is an interlayer dielectric (As modified, the insulation layer 218 is made of silicon dioxide, see [0083] in Barlage).
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Barlage in view of Lee, further in view of Yamazaki as applied to claim 7, further in view of US20090321731A1 (“Jeong”).
RE: Claim 8, Barlage in view of Lee, Yamazaki does not explicitly disclose The method of claim 7, further comprising doping the source-channel interface with nitrogen, chlorine, fluorine, or a combination of two or more of such.
However, Barlage teaches Examples of suitable materials for semiconductor layer 216 include, without limitation, zinc oxide, [0070].
Barlage further teaches source-channel interfacial member 250 can consist of an oxide or a sulfide, [0076].
In the same field of endeavor, Jeong discloses the interfacial stability layer 35 disposed between the active layer 34 and the source and drain electrodes 36 a and 36 b is formed to have, for example, a thickness of 10 to 20 Å, so that contact resistance between the active layer 34 and the source and drain electrodes 36 a and 36 b can be low, [0047], see FIGs. 4-5.
Jeong further teaches The interfacial stability layer 35 is an oxide having a band gap equal to or greater than that of the active layer 34, e.g., a band gap of 3.0 to 8.0 eV. The interfacial stability layer 35 may include any one selected from the group consisting of SiOx, SiN, SiOxNy, SiOxCy, SiOxCyHz, SiOxFy, GeOx, GdOx, AlOx, GaOx, SbO, ZrOx, HfOx, TaOx, YOx, VOx, MgOx, CaOx, BaOx, SrOx, and SOG, [0047].
Jeong further teaches Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented, [0020].
Jeong further teaches The active layer 34 may contain zinc oxide (ZnO), [0046].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the material SiOxFy in the source-channel interfacial member 250 and to make the source-channel interfacial member 250 have a bandgap greater than that of the channel 216 as taught by Jeong in order to prevent charge trapping while keeping contact resistance between the source and channel low as also taught by Jeong. Since the source-channel interfacial member 250 would have a bandgap greater than that of the channel 216, the source-channel interfacial member 216 would still serve as an electron transport barrier. As a result, the source-channel interfacial member 216 would be doped with fluorine.
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Barlage in view of Lee, further in view of Yamazaki as applied to claim 1, further in view of US 20210183913 A1 (“Lee-2”).
RE: Claim 10, Barlage in view of Lee, Yamazaki does not explicitly disclose The method of claim 1, further comprising forming a layer of intermediate contact material over the source and drain to provide ohmic contact to an electrode.
However, Barlage discloses source contact 207 and drain contact 211 can be a degenerate (highly doped) semiconductor, [0073].
In FIG. 2A, Yamazaki discloses electrodes 136a, 136b in direct contact with source and drain electrodes 130a, 130b.
Yamazaki further discloses By planarizing the surfaces of the insulating layer 132, the electrodes 136 a, 136 b, and 136 c, and the gate electrode 136 d in such a manner, an electrode, a wiring, an insulating layer, a semiconductor layer, and the like can be favorably formed in later steps, [0107].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide other electrodes connected to the source and drain electrodes 208, 212 as taught by Yamazaki in order to more easily form additional connections to the source and drain electrodes 208, 212.
In the same field of endeavor, Lee-2 discloses The source electrode 145 branches off and protrudes from the data line 140 to be located in the source region of the semiconductor layer 130. The drain electrode 147 is spaced apart from the source electrode 145 and located in the drain region of the semiconductor layer 130, [0081], see FIG. 4.
Lee-2 further discloses The ohmic contact layers 135 and 136 may be disposed between the source electrode 145 and the semiconductor layer 130 and between the drain electrode 147 and the semiconductor layer 130, respectively, to lower the contact resistance, [0083].
FIG. 4 shows an electrode 160 connected to the drain electrode 147, [0076].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to introduce ohmic contact layers between the source/drain contacts 207, 211 and the source/drain electrodes 208, 212 as taught by Lee-2 in order to lower contact resistance as further taught by Lee-2. As a result, the ohmic contact layers would be formed over the source and drain contacts 207, 211 to provide ohmic contact to the other electrodes connected to the source and drain electrodes 208, 212.
Claim 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Barlage in view of Lee, further in view of Yamazaki as applied to claim 1, further in view of US20120168754A1 (“Le Neel”).
RE: Claim 12, Barlage in view of Lee, Yamazaki discloses The method of claim 1, further comprising:
forming a substrate over a planar surface formed by the planarizing (Yamazaki FIG. 2A shows insulating layer 132 formed over a planar surface of 128 formed by the planarizing, [0079]; Yamazaki discloses 128 is planarized, [0098]); and
forming another transistor (162, [0078]) over the substrate, including forming and planarizing another structure of layers (oxide semiconductor layer 140, source/drain electrodes 140a, 140b, insulating layer 146, [0080]; insulating layer 146 is planarized with CMP, [0156]; 146 is silicon oxide, [0156]).
Barlage in view of Lee, Yamazaki does not explicitly disclose the another transistor is a thin film transistor.
In the same field of endeavor, Le Neel discloses in FIG. 2B:
forming a substrate (passivation layer 52a, [0054]) over a planar surface (surface of 46b); and
forming another thin-film transistor over the substrate, including forming another structure of layers (layers over 52a in FIG. 2B including 46b, thin film transistor 30b, 52b, 46c, thin film transistor 30c, 52c, [0054]-[0056]).
Le Neel teaches the trandsconductance characteristics of transistors allows them to be used as signal amplifiers. A small change in voltage at one terminal of a transistor can lead to a relatively large change in current flowing between other terminals of the transistor. Transistors are used in circuits with passive analog circuit elements such as resistors, capacitors, and inductors to form powerful and complex analog electronic devices, [0006].
Le Neel further teaches passivation layer 52 is SiO2, [0043].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form additional thin-film transistors over the thin film transistor 200a in Barlage including passivation layers 52a, 52b, 52c and dielectric layers 46b, 46c as taught by Le Neel in order provide a more powerful circuit with more amplification. As a result, Le Neel’s dielectric layer 46b corresponding to the claimed substrate would be formed over the planar surface of Yamazaki’s insulating layer 128 formed by the planarizing, and another thin film transistor would be formed over Le Neel’s dielectric layer 46b, including forming another structure of passivation layers 52b, 52c and dielectric layer 46c.
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to planarize the Le Neel’s uppermost passivation layer 52c as taught by Yamazaki in order to in order to more favorably or easily form wiring or insulating layers in later steps as further taught by Yamazaki.
RE: Claim 13, Barlage in view of Lee, Yamazaki, Le Neel discloses The method of claim 12, wherein the substrate is an interlayer dielectric (As modified, Le Neel’s dielectric layer 46b would correspond to the claimed substrate, see Le Neel [0055], FIG. 2B).
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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