DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0164509 to Yoshida et al..
As per claim 1, Yoshida et al. teach a drive circuit (Fig. 6) comprising:
multiple unit circuits (Fig. 6, SR1 - SRn), each of the multiple unit circuits being configured to output a drive signal to at least a scanning signal line of a group of scanning signal lines (Figs. 4 and 6, signal GOUT is output to scan lines),
wherein a drive period (Fig. 9(b), period during which netB is low) during which the drive signal is supplied to the group of scanning signal lines (Fig. 9(b), paragraph 91, “In the selection. period, the low potential Vgl2 is supplied to the node netB”; paragraph 96, “TFT 47 … In the selection period … the source potential is Vgh”) in response to input of a clock signal and a stop period (Fig. 9(b), signal netB fluctuates between Vgh and Vgl2, the high level period (Vgh) will be construed as the stop period) during which supply of the drive signal to the group of scanning signal lines is stopped (Fig. 9, GOUT is low when netB is high) are provided within one cycle of a vertical synchronization signal (Fig. 10B, gate start pulse GSP is provided once per active period),
a unit circuit of the multiple unit circuits includes
a first node (Fig. 9(a), node netA),
a first transistor (Fig. 9(a), transistor 47) configured to output the drive signal (Figs. 9(a)-9(b), GOUT) to the scanning signal line, the first node (Fig. 9(a), node netA) being connected to a gate electrode of the first transistor, the clock signal being applied to one of a source electrode and a drain electrode of the first transistor (Fig. 9(a), CLK is directly applied to the drain of transistor 47), and the other of the source electrode and the drain electrode of the first transistor being connected to the scanning signal line (Fig. 9(a), source of transistor 47 is directly connected to GOUT),
a second transistor (Fig. 9(a), transistor 41) to which a set signal (Figs. 9(a)-9(b), SET signal) for the unit circuit is input, the set signal being input to a gate electrode of the second transistor, and one of a source electrode and a drain electrode of the second transistor being connected to the first node (Fig. 9(a), source of transistor 41 is directly connected to node netA),
a third transistor (Fig. 9A, transistor 42) to which a reset signal (Fig. 9, RESET) for the unit circuit is input, the reset signal being input to a gate electrode of the third transistor, and one of a source electrode and a drain electrode of the third transistor being connected to the first node (Fig. 9(a), the drain of transistor 42 is at least indirectly connected to node netA, via transistor 41 when said transistor 41 is enabled),
a second node (Fig. 9(a), node netE),
a fourth transistor (Fig. 9(a), transistor 44), the first node being connected to one of a source electrode and a drain electrode of the fourth transistor (Fig. 9(a), the drain of transistor 44 is at least indirectly connected to node netA, via transistors 41 ad 43 when said transistor 41 is enabled), and the second node being connected to the other of the source electrode and the drain electrode of the fourth transistor (Fig. 9(a), the source of transistor 44 is directly connected to node netE), and
a fifth transistor (Fig. 9(a), transistor 43), the first node being connected to a gate electrode of the fifth transistor (Fig. 9(a), the gate of transistor 43 is at least indirectly connected to node netA, via transistor 41 when said transistor 41 is enabled), a gate-on voltage being applied to one of a source electrode and a drain electrode of the fifth transistor (Fig. 9(a), VDD is applied to the drain of transistor 43), and the second node being connected to the other of the source electrode and the drain electrode of the fifth transistor (Fig. 9(a), the source of transistor 43 is at least indirectly connected to node netE, via transistor 44 when said transistor 44 is enabled), and
a stop period signal (Fig. 9, signal at node netB) configured to be the gate-on voltage during the stop period (Fig. 9(b), signal netB fluctuates between Vgh and Vgl2, the high level period (Vgh) of netB is being construed as the stop period, during said stop period, Figs. 9(a)-9(b) imply that signal Vgh = VDD (gate-on voltage), because when voltage VDD is input to node netA during the SET period, said node netA becomes Vgh, see also paragraph 86, “when the set signal SET is turned ON, … the node netA is pre-charged to a high level”) and configured to be a gate- off voltage during the drive period (Fig. 9(b), paragraph 91, “In the selection. period, the low potential Vgl2 is supplied to the node netB”; paragraph 96, “TFT 47 … In the selection period … the source potential is Vgh”) is input to the other of the source electrode and the drain electrode of the third transistor (Fig. 9A, the source of transistor 42 is directly connected to node netB and its corresponding Vgh/Vgl2 signal).
As per claim 4, Yoshida et al. teach the drive circuit according to claim 1, wherein a clock signal input to another unit circuit different from the unit circuit itself is input to the gate electrode of the third transistor as the reset signal (Figs. 6 and 9, the GOUT signal of a next stage is used as the RESET signal of a previous stage, said RESET signal is applied to the gate of transistor T42 at the previous stage).
As per claim 5, Yoshida et al. teach a display device comprising: the drive circuit according to claim 1; and
a substrate provided with the group of scanning signal lines (Fig. 4, paragraph 122, “active matrix substrate”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0164509 to Yoshida et al..; in view of US 2023/0104048 to Kitagawa et al.
As per claim 6, Yoshida et al. teach a display device comprising: the drive circuit according to claim 1 and being configured to output scanning signals during the drive period (paragraph 96, “TFT 47 … In the selection period … the source potential is Vgh”).
Yoshida et al. do not teach the display device having a touch detection function and further comprising, displaying an image during the output of scanning signals, a touch panel provided with the group of scanning signal lines, and being configured to detect a touch by a pointer during the stop period.
Kitagawa et al. teach the display device having a touch detection function and further comprising, displaying an image during the output of scanning signals (Fig. 5, paragraph 37, “sequentially supplies a gate signal (scanning signal) to each of the plurality of gate lines 16 in a period DP (see FIG. 5) for displaying an image”), a touch panel provided with the group of scanning signal lines (paragraph 5, “an in-cell touch panel device including an in-cell touch panel that performs both of display of an image and detection of a touch position”), and being configured to detect a touch by a pointer during the stop period (paragraph 39, “the timing controller 21 causes the touch panel controller 22 to perform display of an image on the in-cell touch panel 1 and detection of a touch position by the in-cell touch panel 1 in a time division manner”, a stop period further comprises a touch detection period).
It would have been obvious to one of ordinary skill in the art, to modify the device of Yoshida et al., so that the display device has a touch detection function and further comprises, displaying an image during the output of scanning signals, a touch panel provided with the group of scanning signal lines, and is configured to detect a touch by a pointer during the stop period, such as taught by Kitagawa et al., for the purpose of controlling a device with touchscreen inputs.
Allowable Subject Matter
Claims 2 and 3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R SOTO LOPEZ whose telephone number is (571)270-5689. The examiner can normally be reached Monday-Friday, from 8 am - 5 pm.
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/JOSE R SOTO LOPEZ/Primary Examiner, Art Unit 2622
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