Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
The amendment filed 30 September 2026 has been entered.
Claims 1 and 9 are amended.
Claims 1–20 are pending; claims 1–17 are examined; claims 18–20 remain withdrawn.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 3 and 6 are objected to because of the following informalities:
In claim 3, “disposed on a same layer the first gate electrode” should read disposed on a same layer as the first gate electrode; and
in claim 6, the series in “a fourth transistor including a fourth gate electrode which receives the compensating scan signal, the second semiconductor pattern, and electrically connected between the second electrode and the first gate electrode” is not parallel, and
should read, for example, a fourth transistor including the second semiconductor pattern and a fourth gate electrode which receives the compensating scan signal, and electrically connected between the second electrode and the first gate electrode.
Appropriate correction is required.
Claims 4-5 and 7-8 are objected to as being dependent upon objected base claims 3 and 6.
Claim Interpretation
The following reading is applied under the broadest reasonable interpretation consistent with the specification. A resistance of the write scan line is less than a resistance of the first gate electrode (claim 1) is read as reciting that the conductive layer in which the write scan line is formed has a lower resistance (sheet resistance) than the conductive layer in which the first gate electrode is formed.
The specification compares the resistances of the two layers [e.g., Instant Specification Paragraph 251: A first resistance of the first data pattern layer SD1 may be lower than a second resistance of the first gate pattern layer GAT1.],
which include the write scan line and the first gate electrode respectively [e.g., Instant Specification Paragraph 239: The first data pattern layer SD1 may include a horizontal connecting line H_DCL, a green initializing voltage line VAIL-G, the connecting pattern CP, a write scan line SWL, and a plurality of first connecting electrode patterns C_CNE1.; Instant Specification Paragraph 206: The first gate pattern layer GAT1 may include a black scan line SBL, a first gate electrode GE1, a second gate electrode GE2, and a first initializing voltage line VIL.].
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a resistance of the write scan line is less than a resistance of the first gate electrode”.
The phrase renders the claim indefinite because it is open to more than one reasonable interpretation and the interpretations differ in scope.
It may be read as comparing the resistances of the conductive layers in which the write scan line and the first gate electrode are formed, which is the comparison the specification makes [e.g., Instant Specification Paragraph 251: A first resistance of the first data pattern layer SD1 may be lower than a second resistance of the first gate pattern layer GAT1.].
It may also be read as comparing the resistance of the write scan line itself, of which the specification also speaks [e.g., Instant Specification Paragraph 252: since the first data pattern layer SD1 may include the write scan line SWL, the resistance of the write scan line SWL may be reduced, and the delay of the write scan signal SWj may be reduced],
a line extending in the first direction [e.g., Instant Specification Paragraph 245: The write scan line SWL may extend in the first direction DR1.], with the resistance of the first gate electrode itself, an island-shaped electrode [e.g., Instant Specification Paragraph 209: The first gate electrode GE1 may be formed in an island shape.]:
the claim identifies no terminals or dimensions between which either resistance is taken, and the specification states no resistance of the first gate electrode.
Which of the two is claimed cannot be determined from the claim. For the purpose of applying the prior art, the phrase is interpreted as set out in paragraph 7 above.
See MPEP § 2173.06.
Claims 2-17 are rejected as being dependent upon rejected base claim 1 and incorporating its indefiniteness.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9–15 and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Feng et al. (US 2025/0089489 A1).
Regarding claim 1, Feng discloses an electronic device [e.g., Paragraph 78: An exemplary embodiment also provides a display device including the display panel as described above.; Paragraph 78: The display device may be a display device such as a mobile phone, a tablet computer, a television, and the like.] comprising:
a light emitting element [e.g., Paragraph 52: The pixel driving circuit may be used to drive a light-emitting unit OLED to emit light; Fig. 1: OLED];
a data line [e.g., Paragraph 70: the fifth conductive layer may include a data line Da, a first power line VDD1; Fig. 11: Da]
configured to provide a data signal [e.g., Paragraph 55: the data signal terminal Da outputs a data signal to write a compensating voltage Vdata+Vth to the gate electrode of the driving transistor; Paragraph 70: The data line Da may be used to provide the data signal terminal of FIG. 1; Fig. 1: Da];
a pixel circuit connected to the light emitting element [e.g., Paragraph 51: The pixel driving circuit may include a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a capacitor C.; Paragraph 52: a first electrode of the light-emitting unit OLED is connected to the second electrode of the sixth transistor T6; Fig. 1: T1–T9, C, OLED]; and
a plurality of scan lines connected to the pixel circuit, wherein the plurality of scan lines include: [e.g., Fig. 19: 2G2, 3G2, 4G1, 4Re1, 4Re2, EM]
an initializing scan line [e.g., Paragraph 67: the third conductive layer may include the second gate line 3G2 and the third initial signal line Vinit3; Paragraph 67: The second gate line 3G2 is used to provide the second gate driving signal terminal in FIG. 1, the orthographic projection of the second gate line 3G2 on the base substrate may cover an orthographic projection of the eighth active part 88 on the base substrate, and a portion of the second gate line 3G2 may be used to form a top gate of the eighth transistor T8.; Fig. 19: 3G2]
extending in a first direction [e.g., Paragraph 67: an orthographic projection of the second gate line 3G2 on the base substrate and an orthographic projection of the third initial signal line Vinit3 on the base substrate may extend along the first direction X; Paragraph 64: the first direction X may be a row direction and the second direction Y may be a column direction; Fig. 19: X] and
providing an initializing scan signal [e.g., Paragraph 54: In the reset stage t2, the second gate driving signal terminal G2 outputs a high level; Paragraph 55: the eighth transistor T8, the first transistor T1, the seventh transistor T7, and the ninth transistor T9 are turned on, the first initial signal terminal Vinit1 inputs a first initial signal to the gate electrode of the driving transistor T3 through the first transistor T1 and the eighth transistor T8; Fig. 1: G2, T8, T1, Vinit1; Fig. 2: G2, t2]; and
a write scan line [e.g., Paragraph 68: the fourth conductive layer may include a first reset connection line 4Re1, a second reset connection line 4Re2, a first gate connection line 4G1, a power connection line 4VD; Paragraph 68: The first gate connection line 4G1 may be connected to a plurality of first gate line sections G11 in a same first gate line G1 respectively through via holes.; Fig. 10: 4G1; Fig. 19: 4G1]
extending in the first direction [e.g., Paragraph 68: an orthographic projection of the first gate connection line 4G1 on the base substrate, and an orthographic projection of the power connection line 4VD on the base substrate may all extend along the first direction X; Fig. 10: X] and
providing a write scan signal [e.g., Paragraph 63: The first gate line G1 may be used to provide the first gate driving signal terminal in FIG. 1; Paragraph 55: In the data writing stage t4, the second gate driving signal terminal G2 outputs a high level, the first gate driving signal terminal G1 outputs a low level signal, the eighth transistor T8, the second transistor T2, and the fourth transistor T4 are turned on, and the data signal terminal Da outputs a data signal; Paragraph 68: the first gate connection line 4G1 may improve the response speed of the second transistor T2 and the fourth transistor T4, as well as improve the display uniformity of the display panel; Fig. 1: G1, T4; Fig. 2: G1, t4],
wherein the pixel circuit includes:
a first transistor [e.g., Fig. 1: T3] including
a first semiconductor pattern [e.g., Paragraph 61: the third active part 63 is used to form a channel region of the driving transistor T3; Paragraph 61: the twelfth active part 612 is connected between the third active part 63 and the fifth active part 65; Fig. 5: 63, 612]
which includes a first electrode and a second electrode [e.g., Paragraph 64: a region in the first active layer covered by the first conductive layer may form a channel region of a transistor, and a region in the first active layer not covered by the first conductive layer forms a conductive structure; Paragraph 68: The seventh bridging part 47 may be connected to the twelfth active part 612 and the fifteenth active part 615 respectively through via holes to connect the second electrode of the ninth transistor T9 and the first electrode of the driving transistor T3.; Paragraph 52: a second electrode of the second transistor T2 is connected to a second electrode of the driving transistor T3; Fig. 5: 63, 612] and
includes a first material [e.g., Paragraph 62: The first active layer may be formed from a polysilicon material], and a first gate electrode [e.g., Paragraph 63: the first conductive part 11 may be used to form the gate electrode of the driving transistor T3 and the first electrode of the capacitor C; Fig. 6: 11];
a second transistor [e.g., Fig. 1: T4]
including a second gate electrode which receives the write scan signal [e.g., Paragraph 63: A portion of the first gate line section G11 may be used to form the gate electrode of the second transistor T2, and another portion of the first gate line section G11 may be used to form the gate electrode of the fourth transistor T4.; Fig. 6: G11], and
connected between the first electrode and the data line [e.g., Paragraph 52: A first electrode of the fourth transistor T4 is connected to a data signal terminal Da, a second electrode of the fourth transistor T4 is connected to a first electrode of the driving transistor T3, and a gate electrode of the fourth transistor T4 is connected to the first gate driving signal terminal G1.; Fig. 1: Da, T4, T3]; and
a third transistor [e.g., Fig. 1: T8] including
a second semiconductor pattern [e.g., Paragraph 66: the second active layer may include a plurality of sub-active parts 8; Paragraph 66: the eighth active part 88 is used to form a channel region of the eighth transistor; Fig. 8: 8, 88, 819, 820]
including a second material different from the first material [e.g., Paragraph 66: The second active layer may be formed from indium gallium zinc oxide, and accordingly, the eighth transistor T8 may be an N-type metal oxide thin film transistor.], receiving the initializing scan signal [e.g., Paragraph 52: a gate electrode of the eighth transistor T8 is connected to a second gate driving signal terminal G2; Paragraph 56: the display panel can reset the first electrode of the driving transistor T3 through the ninth transistor T9, and reset the gate electrode of the driving transistor T3 through the eighth transistor T8 and the first transistor T1; Fig. 1: T8, G2] and
connected to the first gate electrode [e.g., Paragraph 52: A first electrode of the eighth transistor T8 is connected to a gate electrode of the driving transistor T3; Paragraph 68: The fourth bridging part 44 may be connected to the twentieth active part 820 through a first via hole H1 and to the first conductive part 11 through a second via hole H2 to connect the gate electrode of the driving transistor T3 and the first electrode of the eighth transistor T8.; Fig. 19: 44, H1, H2], and
wherein the initializing scan line, the write scan line, and the first gate electrode are disposed on different layers from each other [e.g., Paragraph 59: a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and an electrode layer which are stacked in that order; Paragraph 59: An insulating layer may be provided between any adjacent layers described above.; Paragraph 63: the first conductive layer may include the first reset signal line Re1, the first gate line G1, the enable signal line EM, the second reset signal line Re2, and a first conductive part 11; Paragraph 67: the third conductive layer may include the second gate line 3G2 and the third initial signal line Vinit3; Paragraph 68: the fourth conductive layer may include a first reset connection line 4Re1, a second reset connection line 4Re2, a first gate connection line 4G1, a power connection line 4VD; Fig. 19: 3G2, 4G1], and
a resistance of the write scan line is less than a resistance of the first gate electrode [e.g., Paragraph 68: In an exemplary embodiment, the square resistance of the first conductive layer is greater than the square resistance of the fourth conductive layer.; Paragraph 68: the first gate connection line 4G1 may improve the response speed of the second transistor T2 and the fourth transistor T4, as well as improve the display uniformity of the display panel; Paragraph 76: The square resistance of any one of the first conductive layer, the second conductive layer, and the third conductive layer may be greater than the square resistance of any one of the fourth conductive layer, the fifth conductive layer and the sixth conductive layer.]. (e.g., see Paragraphs 51–76)
The initializing scan line is Feng’s second gate line 3G2 in the third conductive layer (the third gate line 2G2, which carries the same signal, lies in the second conductive layer), the write scan line is the first gate connection line 4G1 in the fourth conductive layer, and the first gate electrode is the first conductive part 11 in the first conductive layer. The resistance limitation is met under the reading of paragraph 7 above.
Regarding claim 9, Feng discloses the plurality of scan lines further include: a light emitting control line [e.g., Paragraph 63: The enable signal line EM is used to provide the enable signal terminal in FIG. 1, and an orthographic projection of the enable signal line EM on the base substrate may extend along the first direction X; Fig. 6: EM; Fig. 19: EM]
extending in the first direction and providing a light emitting control signal [e.g., Paragraph 55: In the light-emitting stage t6, the enable signal terminal EM outputs a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on; Fig. 2: EM, t6], and
wherein the pixel circuit further includes:
a fifth transistor connected to the first electrode and receiving the light emitting control signal [e.g., Paragraph 52: A first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and a gate electrode of the fifth transistor T5 is connected to an enable signal terminal EM.; Fig. 1: T5, EM, T3].
Regarding claim 10, Feng discloses the light emitting control line is disposed on a different layer from the write scan line [e.g., Paragraph 63: the first conductive layer may include the first reset signal line Re1, the first gate line G1, the enable signal line EM, the second reset signal line Re2, and a first conductive part 11; Paragraph 68: the fourth conductive layer may include a first reset connection line 4Re1, a second reset connection line 4Re2, a first gate connection line 4G1, a power connection line 4VD; Fig. 19: EM, 4G1].
Regarding claim 11, Feng discloses the pixel circuit further includes: a connecting pattern disposed on a same layer as the write scan line [e.g., Paragraph 68: The first bridging part 41 is connected to the power connection line 4VD and is connected to the thirteenth active part 613 through a via hole, and the power connection line 4VD is connected to a plurality of second conductive parts 22 arranged in the first direction X through via holes to connect the first electrode of the fifth transistor and the second electrode of the capacitor.; Paragraph 68: the fourth conductive layer may include a first reset connection line 4Re1, a second reset connection line 4Re2, a first gate connection line 4G1, a power connection line 4VD; Fig. 10: 4VD, 41, 4G1]; and
a capacitor electrode overlapped with the first gate electrode, when viewed in a plan view [e.g., Paragraph 65: An orthographic projection of the second conductive part 22 on the base substrate may be overlapped with the orthographic projection of the first conductive part 11 on the base substrate, and the second conductive part 22 may be used to form the second electrode of the capacitor C.; Fig. 7: 22; Fig. 19: 22].
The connecting pattern is Feng’s power connection line 4VD with its first bridging part 41, in the fourth conductive layer, and the capacitor electrode is the second conductive part 22.
Regarding claim 12, Feng discloses a first driving voltage line extending in a second direction crossing the first direction and providing a first driving voltage [e.g., Paragraph 70: the first power line VDD1 may be used to provide the first power supply terminal of FIG. 1; Paragraph 70: An orthographic projection of the data line Da on the base substrate and an orthographic projection of the first power line VDD1 on the base substrate may extend in the second direction Y.; Fig. 11: VDD1, Y; Fig. 20: VDD1],
wherein the connecting pattern is connected to the first driving voltage line through a contact hole [e.g., Paragraph 70: the first power line VDD1 may be connected to the first bridging part 41 through a via hole to connect the first power supply terminal, the second electrode of the capacitor C, and the first electrode of the fifth transistor T5; Fig. 10: 41, 4VD; Fig. 20: VDD1, 4VD].
Regarding claim 13, Feng discloses the first driving voltage line is disposed on a same layer as the data line [e.g., Paragraph 70: the fifth conductive layer may include a data line Da, a first power line VDD1; Fig. 11: Da, VDD1].
Regarding claim 14, Feng discloses the connecting pattern is overlapped with the capacitor electrode, when viewed in the plan view [e.g., Paragraph 68: the power connection line 4VD is connected to a plurality of second conductive parts 22 arranged in the first direction X through via holes; Fig. 19: 4VD, 22].
Regarding claim 15, Feng discloses the write scan line is spaced apart from the connecting pattern in a second direction crossing the first direction, when viewed in the plan view [e.g., Paragraph 64: The second direction Y and the first direction X may be intersected with each other; Fig. 10: 4G1, 4VD, 41, Y; Fig. 19: 4G1, 4VD, Y].
Regarding claim 17, Feng discloses the second gate electrode is disposed on a same layer as the first gate electrode [e.g., Paragraph 63: the first conductive layer may include the first reset signal line Re1, the first gate line G1, the enable signal line EM, the second reset signal line Re2, and a first conductive part 11; Paragraph 63: another portion of the first gate line section G11 may be used to form the gate electrode of the fourth transistor T4; Fig. 6: G11, 11], and
wherein the second gate electrode is connected to the write scan line through a contact hole [e.g., Paragraph 68: The first gate connection line 4G1 may be connected to a plurality of first gate line sections G11 in a same first gate line G1 respectively through via holes.; Fig. 19: 4G1].
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3–15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (US 2022/0310736 A1) in view of Ono et al. (US 2021/0305353 A1);
or, in the alternative, under 35 U.S.C. 103 as being unpatentable over Seo et al. (US 2022/0310736 A1) in view of Ono et al. (US 2021/0305353 A1) and Feng et al. (US 2025/0089489 A1).
Please note: strikethrough marks claim subject matter not disclosed by the named reference.
Regarding claim 1, Seo discloses an electronic device [e.g., Paragraph 57: A display apparatus described with reference to the drawings may include an apparatus for displaying moving images or still images and may be used as a display screen of various products including televisions, notebook computers, monitors, advertisement boards, Internet of things (IoT) as well as portable electronic apparatuses including mobile phones] comprising:
a light emitting element [e.g., Paragraph 118: the pixel circuit PC1 may be connected to signal lines and an organic light-emitting diode OLED; Fig. 6: OLED1];
a data line [e.g., Fig. 6: DL] configured to provide a data signal [e.g., Paragraph 124: a data signal Dm to a first node N1, the data signal Dm being transferred through the data line DL; Fig. 6: Dm];
a pixel circuit connected to the light emitting element [e.g., Paragraph 119: the first pixel circuit PC1 may include first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, and first to third storage capacitors Cst1, Cst2, and Cbt; Fig. 6: PC1]; and
a plurality of scan lines connected to the pixel circuit, wherein the plurality of scan lines include: [e.g., Paragraph 119: The signal lines may include a data line DL, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and an emission control line EL.]
an initializing scan line [e.g., Fig. 6: SL3; Fig. 7: SL3, 143, 163]
extending in a first direction [e.g., Paragraph 121: The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, the first initialization voltage line VIL1, and second initialization voltage line VIL2 may extend in the first direction (the x-direction) and be spaced apart from each other in each row.; Fig. 7: x] and
providing an initializing scan signal [e.g., Paragraph 126: transferred through the third scan line SL3 to initialize the voltage of a gate electrode of the first transistor T1 by transferring the first initialization voltage Vint1 to the gate electrode of the first transistor T1]; and
a write scan line [e.g., Fig. 6: SL1; Fig. 7: SL1(SL2)]
extending in the first direction and providing a write scan signal [e.g., Paragraph 124: The second transistor T2 may be turned on in response to a first scan signal Sn transferred through the first scan line SL1 and may perform a switching operation to transfer a data signal Dm to a first node N1; Paragraph 121: The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, the first initialization voltage line VIL1, and second initialization voltage line VIL2 may extend in the first direction (the x-direction) and be spaced apart from each other in each row.; Fig. 6: Sn; Fig. 7: x],
wherein the pixel circuit includes:
a first transistor [e.g., Fig. 6: T1] including
a first semiconductor pattern which includes a first electrode and a second electrode [e.g., Paragraph 151: The first semiconductor layer may include a first channel region A1, a first source region S1, and a first drain region D1; Paragraph 150: A source region and a drain region may respectively correspond to a source electrode and a drain electrode.; Fig. 7: A1, S1, D1] and includes
a first material [e.g., Paragraph 149: the semiconductor layer may include polycrystalline silicon as an active layer], and
a first gate electrode [e.g., Paragraph 151: The first gate electrode G1 may be an island type electrode and may overlap the first channel region A1 with a first gate insulating layer 112 (see FIG. 8) therebetween.; Fig. 7: G1; Fig. 8: G1, 112];
a second transistor [e.g., Fig. 6: T2] including
a second gate electrode which receives the write scan signal [e.g., Paragraph 157: The second gate electrode G2 may be provided as a portion of the first scan line SL1.; Fig. 7: G2], and
connected between the first electrode and the data line [e.g., Paragraph 157: The second source region S2 may be electrically connected to a data line (see FIG. 6), and the second drain region D2 may be electrically connected to the first node; Paragraph 124: The second transistor T2 may be connected to the first scan line SL1 and the data line DL; Fig. 6: DL, T2, N1, T1]; and
a third transistor [e.g., Fig. 6: T4] including
a second semiconductor pattern including a second material different from the first material [e.g., Paragraph 166: The fourth transistor T4 may include a fourth semiconductor layer and a fourth gate electrode G4, the fourth semiconductor layer including an oxide semiconductor.; Fig. 7: A4, S4, D4; Fig. 8: AO4],
receiving the initializing scan signal [e.g., Paragraph 167: The fourth gate electrode G4 may be provided as a portion of the third scan line SL3.] and
connected to the first gate electrode [e.g., Paragraph 167: The fourth drain region D4 may be bridge-connected to the first gate electrode G1 through the node connection line 171.; Fig. 8: D4, 61, 171, 62, 161, 63, G1], and
wherein the initializing scan line, the third scan line SL3 may include a lower scan line 143 and an upper scan line 163 arranged in different layers; Paragraph 173: The lower scan line 143 may be arranged in the same layer as the second electrode CE2 of the first storage capacitor Cst1 and may include the same material as that of the second electrode CE2.; Paragraph 173: The upper scan line 163 may be arranged on the third gate insulating layer 115 (see FIG. 8).; Paragraph 183: The first gate electrode G1 of the first transistor T1, the second gate electrode G2 of the second transistor T2, the fifth gate electrode G5 of the fifth transistor T5, the sixth gate electrode G6 of the sixth transistor T6, and the seventh gate electrode G7 of the seventh transistor T7 may be arranged on the first gate insulating layer 112.; Fig. 8: G1, 112, CE2, 113, 115]
Seo does not expressly disclose the write scan line disposed on a different layer from the first gate electrode G1 itself, or a resistance of the write scan line less than a resistance of the first gate electrode: the first scan line SL1 is arranged in the layer of the first gate electrode G1 [e.g., Seo, Paragraph 172: In an embodiment, the first scan line SL1, the second scan line SL2, and the emission control line EL may be arranged in the same layer as the first gate electrode G1 and may include the same material as that of the first gate electrode G1.].
Ono discloses an organic light-emitting diode display pixel having silicon transistors and a semiconducting-oxide transistor [e.g., Ono, Paragraph 29: display pixel 22 may include a storage capacitor Cst and associated pixel transistors such as a semiconducting-oxide transistor Toxide, a drive transistor Tdrive, a data loading transistor Tdata, a first emission transistor Tem1, second emission transistor Tem2, and an anode reset transistor Tar],
in which the gate conductor of a silicon transistor is formed in a first gate metal layer GE1 and is coupled through a conductive via to a routing conductor in a first source-drain metal layer SD1 above it [e.g., Ono, Paragraph 38: The first metal layer may be patterned and etched to form the gate conductor of transistor 350.; Paragraph 43: the GE1 gate conductor of silicon transistor 350 may be coupled to a corresponding SD1 conductor through conductive via 371; Fig. 3: GE1, 371, SD1, 350],
the row control line of that gate conductor being routed across the display in the SD1 layer [e.g., Ono, Paragraph 50: gate line signals such as scan control signals, emission control signals, reset signals, initialization signals, reference signals, enable signals, power supply signals (e.g., positive power supply voltages or ground power supply voltages), and/or other row control signals may be routed across the face of the display using low resistance material such as the SD1 metal routing layer; Fig. 5: SD1, GE1], and
in which the SD1 conductors have less resistance than the gate metal conductors [e.g., Ono, Paragraph 47: The GE1 gate conductor of a display pixel silicon transistor, the GE2 capacitor terminal of a display pixel capacitor, and the OGE gate conductor of a display pixel semiconducting-oxide transistor are typically formed using a high resistance material such as molybdenum, titanium, some combination of high resistance materials, or other suitable metal.; Paragraph 48: Formed in this way, the SD1/SD2 conductors may exhibit substantially higher conductivity and less resistance than the GE1/GE2/OGE conductors.; Paragraph 48: In general, the resistivity of GE1/GE2/OGE metal structures may be at least 5×, at least 10×, at least 100× the resistivity of the SD1/SD2 metal structures.].
Seo and Ono are analogous art because they are from the same field of endeavor as the claimed invention, organic light-emitting diode display pixels having silicon transistors and oxide semiconductor transistors.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to route Seo’s first scan line SL1 across the display as a row line in Seo’s conductive layer on the second interlayer insulating layer 116, a layer of high-conductivity material [e.g., Seo, Paragraph 204: The first power voltage line 172, the second initialization voltage line VIL2, the node connection line 171, and the connection electrodes may include a material having a high conductivity such as metal and a conductive oxide.; Paragraph 204: the first power voltage line 172, the second initialization voltage line VIL2, the node connection line 171, and the connection electrodes may include a triple layer of Ti/Al/Ti in which titanium, aluminum, and titanium are sequentially arranged],
coupled through a contact hole to the portions of the first scan line that form the second gate electrode G2 and the fourth electrode CE4, and any other gate electrode formed by a portion of that line, which are left on the first gate insulating layer 112 with the first gate electrode G1 [e.g., Seo, Paragraph 169: The fourth electrode CE4 of the third storage capacitor Cbt may be provided as a portion of the first scan line SL1 and connected to the second gate electrode G2.], as
Ono teaches for the scan line feeding the gate conductor of a silicon transistor, the gate conductor remaining in the gate metal layer and the row line in the source-drain layer being coupled to it,
because Ono teaches that a scan line routed in the gate metal layer can be loaded to the point that data can no longer be properly sampled onto the pixels of large, high-refresh-rate displays [e.g., Ono, Paragraph 49: the scan line feeding the gate terminal of the silicon transistor is routed in the GE1 metal layer; Paragraph 49: the amount of loading on the high resistance scan lines can be so elevated that the resulting rise and fall times of the gate line signals are increased to the point where data can no longer be properly sampled onto the display pixels], and
that routing the line in the lower-resistance source-drain layer reduces its resistance, can reduce its rise and fall times and can improve brightness uniformity [e.g., Ono, Paragraph 51: Configured and operated in this way, the resistance of the gate lines being routed across the display panel will be drastically reduced; Paragraph 51: which can reduce the rise and fall times of the gate line signals so that data signals can be properly loaded into large display panels operating at high refresh rates; Paragraph 51: By reducing the loading on the gate lines, brightness uniformity of the display can also be improved.].
As so modified, the write scan line lies in the layer on the second interlayer insulating layer 116, the initializing scan line SL3 in the layers on the second gate insulating layer 113 and the third gate insulating layer 115, and the first gate electrode G1 on the first gate insulating layer 112, and the write scan line, routed in that layer and formed, as Ono teaches, of source-drain metal of lower resistance than the gate metal, has a resistance less than that of the first gate electrode formed of the gate metal (paragraph 7 above).
Seo’s layer on the second interlayer insulating layer 116 is of the construction Ono describes for the source-drain conductors, a low resistance material between liners [e.g., Ono, Paragraph 48: the SD1/SD2 routing conductor may include a low resistance material 404 that is optionally sandwiched between two high resistance liners 402; Paragraph 48: Liners 402 may be formed using molybdenum, titanium, some combination of high resistivity material, or other suitable metal.], and
Seo’s gate electrodes may be formed of the gate metals Ono names [e.g., Seo, Paragraph 186: The gate electrodes of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) and may include a single layer or a multi-layer including the above materials.].
Seo’s layer on the second interlayer insulating layer 116 already carries a row line, the second initialization voltage line VIL2, among the first power voltage line 172, the node connection line 171 and the connection electrodes [e.g., Seo, Paragraph 175: The second initialization voltage line VIL2 may be arranged in the same layer as the first power voltage line 172 and may include the same material as that of the first power voltage line 172.; Fig. 7: VIL2, 172, 171], and the first scan line is routed among them in the same way.
The modification applies a known technique to a similar device with predictable results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
In the alternative, under 35 U.S.C. 103 over Seo in view of Ono and Feng:
Should it be shown that Seo in view of Ono discloses the initializing scan line, the write scan line and the first gate electrode disposed on different layers from each other with insufficient specificity, in that
Ono’s FIG. 5 routes the row control lines of the silicon transistor and of the semiconducting-oxide transistor alike in the SD1 layer [e.g., Ono, Paragraph 50: a first row control line coupled to the GE1 metal conductor in pixel 22, a second row control line coupled to the GE2 metal conductor in pixel 22, and a third row control line coupled to the OGE metal conductor in pixel 22 are all routed across the face of the display using the low resistance SD1 routing layer; Fig. 5: SD1, GE1, GE2, OGE]:
Feng discloses a pixel driving circuit having polysilicon transistors and an oxide transistor connected to the gate electrode of the driving transistor [e.g., Feng, Paragraph 62: The first active layer may be formed from a polysilicon material; Paragraph 66: The second active layer may be formed from indium gallium zinc oxide, and accordingly, the eighth transistor T8 may be an N-type metal oxide thin film transistor.; Paragraph 52: A first electrode of the eighth transistor T8 is connected to a gate electrode of the driving transistor T3; Fig. 1: T3, T4, T8],
in which the gate line of the data writing transistor is formed of gate line sections in the first conductive layer, the layer of the gate electrode of the driving transistor, connected through via holes to a gate connection line extending in the row direction in a fourth conductive layer of lower square resistance [e.g., Feng, Paragraph 63: the first conductive layer may include the first reset signal line Re1, the first gate line G1, the enable signal line EM, the second reset signal line Re2, and a first conductive part 11; Paragraph 68: The first gate connection line 4G1 may be connected to a plurality of first gate line sections G11 in a same first gate line G1 respectively through via holes.; Paragraph 68: In an exemplary embodiment, the square resistance of the first conductive layer is greater than the square resistance of the fourth conductive layer.; Fig. 6: G11, 11; Fig. 19: 4G1],
the gate line sections and the conductive part attached to them that couples to the gate of the driving transistor remaining in the first conductive layer [e.g., Feng, Paragraph 69: the first conductive layer may also include a third conductive part 13, and the third conductive part 13 is connected to the first gate line section G11; Paragraph 69: the voltage of the first conductive part electrically connected to the twentieth active part 820 is pulled up by the effect of the coupling of parasitic capacitance between the third conductive part 13 and the twentieth active part 820; Fig. 6: G11, 13],
while the gate lines of the oxide transistor remain in the second and third conductive layers and the enable signal line remains in the first conductive layer [e.g., Feng, Paragraph 65: the second conductive layer may include the third gate line 2G2, the first initial signal line Vinit1, the second initial signal line Vinit2, and a second conductive part 22; Paragraph 67: the third conductive layer may include the second gate line 3G2 and the third initial signal line Vinit3; Paragraph 63: The enable signal line EM is used to provide the enable signal terminal in FIG. 1, and an orthographic projection of the enable signal line EM on the base substrate may extend along the first direction X; Fig. 6: EM; Fig. 19: 2G2, 3G2, EM, 4G1].
Seo, Ono and Feng are analogous art because they are from the same field of endeavor as the claimed invention, organic light-emitting diode display pixels having silicon transistors and oxide semiconductor transistors.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, in routing Seo’s first scan line SL1 in the lower-resistance layer as set out above,
to leave Seo’s third scan line SL3 and fourth scan line SL4 in the layers in which they form the lower and upper gate electrodes of the oxide semiconductor transistors T4 and T3, and the emission control line EL in the layer of the first gate electrode G1,
as Feng does, because Feng teaches that connecting the gate line sections by a connection line in the layer of lower square resistance may improve the response speed of the transistors gated by that line, and the display uniformity [e.g., Feng, Paragraph 68: the first gate connection line 4G1 may improve the response speed of the second transistor T2 and the fourth transistor T4, as well as improve the display uniformity of the display panel], and
Seo’s third and fourth scan lines already lie apart from the layer of the first gate electrode [e.g., Seo, Paragraph 191: The lower scan line 143 of the third scan line SL3 and the lower scan line 145 of the fourth scan line SL4 may be arranged on the second gate insulating layer 113; Paragraph 199: The third gate insulating layer 115 may be arranged between the semiconductor layer AO, and the upper scan line 163 of the third scan line SL3 and the upper scan line 165 of the fourth scan line SL4.].
KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Regarding claim 3, Seo discloses a first initializing voltage line [e.g., Fig. 6: VIL1; Fig. 7: VIL1]
disposed on a same layer the first gate electrode [e.g., Paragraph 175: The first initialization voltage line VIL1 may be arranged in the same layer as the first electrode CE1 of the first storage capacitor Cst1 and may include the same material as that of the first electrode CE1; Paragraph 153: the first gate electrode G1 and the first electrode CE1 may be formed as one body],
extending in the first direction [e.g., Paragraph 121: The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, the first initialization voltage line VIL1, and second initialization voltage line VIL2 may extend in the first direction (the x-direction) and be spaced apart from each other in each row.], and
providing a first initializing voltage [e.g., Paragraph 120: The first initialization voltage line VIL1 may be configured to transfer a first initialization voltage Vint1 to the first pixel circuit PC1, the first initialization voltage Vint1 initializing the first transistor T1.; Fig. 6: Vint1].
Regarding claim 4, Seo discloses the first initializing voltage line is electrically connected to the second semiconductor pattern [e.g., Paragraph 166: The fourth source region S4 may be electrically connected to the first initialization voltage line VIL1.; Fig. 6: T4, VIL1; Fig. 7: S4, VIL1].
Regarding claim 5, the claim recites the first initializing voltage line is disposed on a different layer from the write scan line.
Seo arranges the first initialization voltage line VIL1, in the arrangement applied to claim 3, in the layer of the first electrode CE1 on the first gate insulating layer 112 [e.g., Paragraph 175: The first initialization voltage line VIL1 may be arranged in the same layer as the first electrode CE1 of the first storage capacitor Cst1; Paragraph 153: the first gate electrode G1 and the first electrode CE1 may be formed as one body; Paragraph 183: The first gate electrode G1 of the first transistor T1, the second gate electrode G2 of the second transistor T2, the fifth gate electrode G5 of the fifth transistor T5, the sixth gate electrode G6 of the sixth transistor T6, and the seventh gate electrode G7 of the seventh transistor T7 may be arranged on the first gate insulating layer 112.],
which is the layer of the first scan line SL1, and does not expressly disclose the first initialization voltage line VIL1 on a different layer from the write scan line.
With the first scan line SL1 routed in the layer on the second interlayer insulating layer 116 as set out for claim 1 above, in view of Ono and, in the alternative, of Ono and Feng, the first initialization voltage line VIL1 is disposed on a different layer from the write scan line, for the reasons given for claim 1.
Regarding claim 6, Seo discloses the plurality of scan lines further include: a compensating scan line [e.g., Fig. 6: SL4; Fig. 7: SL4, 145, 165]
extending in the first direction and providing a compensating scan signal [e.g., Paragraph 125: The third transistor T3 may be turned on in response to a fourth scan signal Sn′ transferred through the fourth scan line SL4 to diode-connect the first transistor T1.; Paragraph 121: The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, the first initialization voltage line VIL1, and second initialization voltage line VIL2 may extend in the first direction (the x-direction) and be spaced apart from each other in each row.], and
wherein the pixel circuit further includes:
a fourth transistor [e.g., Fig. 6: T3] including
a fourth gate electrode which receives the compensating scan signal [e.g., Paragraph 165: The third gate electrode G3 may be provided as a portion of the fourth scan line SL4.; Fig. 7: G3],
the second semiconductor pattern [e.g., Paragraph 162: The semiconductor layer of the third transistor T3 and the fourth transistor T4 may be arranged in the same layer and may include the same material.; Paragraph 196: the channel regions, the source regions, and the drain regions of the third transistor T3 and the fourth transistor T4 may be partial regions of the semiconductor layer AO; Fig. 7: A3, S3, D3], and
electrically connected between the second electrode and the first gate electrode [e.g., Paragraph 164: The third source region S3 may be bridge-connected to the first gate electrode G1 through the node connection line 171.; Paragraph 208: One end of the connection electrode 176 may be connected to the first drain region D1 of the first transistor T1 and the sixth source region S6 of the sixth transistor T6 through a contact hole 67.; Paragraph 208: Another end of the connection electrode 176 may be connected to the third drain region D3 of the third transistor T3 through a contact hole 68.; Fig. 7: 171, 176, 67, 68].
Regarding claim 7, Seo discloses the compensating scan line is disposed on a same layer as the initializing scan line [e.g., Paragraph 191: The lower scan line 143 of the third scan line SL3 and the lower scan line 145 of the fourth scan line SL4 may be arranged on the second gate insulating layer 113; Paragraph 199: The third gate insulating layer 115 may be arranged between the semiconductor layer AO, and the upper scan line 163 of the third scan line SL3 and the upper scan line 165 of the fourth scan line SL4.; Fig. 7: 143, 163, 145, 165], and
the compensating scan line and the initializing scan line are spaced apart from each other in a second direction crossing the first direction [e.g., Paragraph 121: The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, the first initialization voltage line VIL1, and second initialization voltage line VIL2 may extend in the first direction (the x-direction) and be spaced apart from each other in each row.; Paragraph 121: The data line DL and the power voltage line PL may extend in the second direction (a y-direction) and be spaced apart from each other in each column.; Fig. 7: SL3, SL4, y].
Regarding claim 8, Seo discloses the compensating scan line is disposed on a different layer from the write scan line [e.g., Paragraph 174: the fourth scan line SL4 may include a lower scan line 145 and an upper scan line 165 arranged in different layers; Paragraph 174: The upper scan line 165 may be arranged on the third gate insulating layer 115 (see FIG. 8).; Paragraph 183: The first scan line SL1 and the emission control line EL may be arranged on the first gate insulating layer 112.; Fig. 8: 145, 165, 113, 115].
The same holds with the first scan line SL1 routed in the layer on the second interlayer insulating layer 116 as set out for claim 1 above, in either alternative.
Regarding claim 9, Seo discloses the plurality of scan lines further include: a light emitting control line [e.g., Fig. 6: EL; Fig. 7: EL]
extending in the first direction and providing a light emitting control signal [e.g., Paragraph 127: The fifth transistor T5 and the sixth transistor T6 may be connected to the emission control line EL and simultaneously turned on in response to an emission control signal En transferred through the emission control line EL; Paragraph 121: The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, the first initialization voltage line VIL1, and second initialization voltage line VIL2 may extend in the first direction (the x-direction) and be spaced apart from each other in each row.; Fig. 6: En], and
wherein the pixel circuit further includes:
a fifth transistor connected to the first electrode and receiving the light emitting control signal [e.g., Paragraph 158: the fifth drain region D5 may be connected to the first source region S1; Paragraph 184: The fifth gate electrode G5 of the fifth transistor T5 and the sixth gate electrode G6 of the sixth transistor T6 may be portions of the emission control line EL crossing the semiconductor layer AS.; Fig. 6: T5, N1, T1; Fig. 7: D5, G5].
Regarding claim 10, the claim recites the light emitting control line is disposed on a different layer from the write scan line.
Seo arranges the emission control line EL on the first gate insulating layer 112 [e.g., Seo, Paragraph 183: The first scan line SL1 and the emission control line EL may be arranged on the first gate insulating layer 112.],
in the layer of the first scan line SL1, and does not expressly disclose the emission control line on a different layer from the write scan line.
With the first scan line SL1 routed in the layer on the second interlayer insulating layer 116 as set out for claim 1 above, the emission control line EL, on the first gate insulating layer 112, is disposed on a different layer from the write scan line, for the reasons given for claim 1.
In the alternative, Feng leaves the enable signal line in the first conductive layer while the gate connection line of the data writing transistor lies in the fourth conductive layer [e.g., Feng, Paragraph 63: the first conductive layer may include the first reset signal line Re1, the first gate line G1, the enable signal line EM, the second reset signal line Re2, and a first conductive part 11; Paragraph 68: the fourth conductive layer may include a first reset connection line 4Re1, a second reset connection line 4Re2, a first gate connection line 4G1, a power connection line 4VD; Fig. 19: EM, 4G1], and the arrangement would have been obvious for the reasons given for claim 1.
Regarding claim 11, Seo discloses the pixel circuit further includes:
a connecting pattern [e.g., Paragraph 202: The first power voltage line 172, the second initialization voltage line VIL2, the node connection line 171, and the connection electrodes may be arranged on the second interlayer insulating layer 116.; Fig. 7: 172; Fig. 8: 172, 116]
a capacitor electrode overlapped with the first gate electrode, when viewed in a plan view [e.g., Paragraph 188: The second electrode CE2 may be arranged on the second gate insulating layer 113 to overlap the first electrode CE1.; Paragraph 185: The first gate electrode G1 of the first transistor T1 may serve as the first electrode CE1 of the first storage capacitor Cst1 as well as a control electrode of the first transistor T1.; Fig. 7: CE1, CE2; Fig. 8: CE1, CE2].
The connecting pattern is Seo’s first power voltage line 172, arranged on the second interlayer insulating layer 116.
Seo does not expressly disclose the connecting pattern disposed on a same layer as the write scan line, the first scan line SL1 being arranged on the first gate insulating layer 112 [e.g., Paragraph 183: The first scan line SL1 and the emission control line EL may be arranged on the first gate insulating layer 112.].
With the first scan line SL1 routed in the layer on the second interlayer insulating layer 116 as set out for claim 1 above, in either alternative, the first power voltage line 172 is disposed on the same layer as the write scan line, for the reasons given for claim 1.
Regarding claim 12, Seo discloses a first driving voltage line extending in a second direction crossing the first direction and providing a first driving voltage [e.g., Paragraph 171: A data line and a second power voltage line (not shown) may be arranged on the first planarization layer 118.; Paragraph 121: The data line DL and the power voltage line PL may extend in the second direction (a y-direction) and be spaced apart from each other in each column.; Paragraph 120: The power voltage line PL may be configured to transfer the first power voltage ELVDD to the first transistor T1.; Fig. 6: PL, ELVDD],
wherein the connecting pattern is connected to the first driving voltage line through a contact hole [e.g., Paragraph 213: The second power voltage line (not shown) may be connected to the first power voltage line 172 through a contact hole defined in the first planarization layer 118.].
The first driving voltage line is Seo’s second power voltage line on the first planarization layer 118, to which the first power voltage line 172 is connected through a contact hole; Seo’s power voltage line PL, which transfers the first power voltage, extends in the second direction.
To the extent Seo does not expressly disclose that the second power voltage line is the part of the power voltage line that extends in the second direction:
Ono discloses the positive power supply line routed in the column direction in the second source-drain layer, perpendicular to the row lines of the first source-drain layer [e.g., Ono, Paragraph 50: the data line (DL), the positive power supply (VDD) line, and the ground power supply (VSS) line may be routed in the column direction using routing lines formed in the SD2 metal routing layer; Paragraph 50: The SD2 routing lines may be perpendicular to the SD1 routing lines.; Fig. 5: SD2 : VDD/VSS, SD1], and,
in the alternative, Feng discloses the first power line extending in the second direction in the layer of the data line and connected through a via hole to the bridging part of the power connection line in the layer below [e.g., Feng, Paragraph 70: An orthographic projection of the data line Da on the base substrate and an orthographic projection of the first power line VDD1 on the base substrate may extend in the second direction Y.; Paragraph 70: the first power line VDD1 may be connected to the first bridging part 41 through a via hole to connect the first power supply terminal, the second electrode of the capacitor C, and the first electrode of the fifth transistor T5; Fig. 20: VDD1, 4VD].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to extend Seo’s second power voltage line in the second direction, above the layer in which the first scan line SL1 is routed as set out for claim 1 above,
because Seo’s power voltage line extends in the second direction column by column and Ono routes the column lines in the upper source-drain layer, perpendicular to the row lines of the lower one, and, in the alternative,
because Feng teaches that the power connection line and the first power line crossing it may form a grid structure of lower resistance that reduces the voltage difference between the power supply terminals at different locations and improves display uniformity [e.g., Feng, Paragraph 70: the power connection line 4VD and the first power line VDD1 may form a grid structure, which has a lower resistance, thereby reducing the voltage difference between the first power supply terminals at different locations of the display panel, and thereby improving the display uniformity of the display panel].
KSR, 550 U.S. 398.
Regarding claim 13, Seo discloses the first driving voltage line is disposed on a same layer as the data line [e.g., Paragraph 211: the data line DL, the second power voltage line, and the connection electrodes may be arranged on the first planarization layer 118].
Regarding claim 14, Seo discloses the connecting pattern is overlapped with the capacitor electrode, when viewed in the plan view [e.g., Paragraph 205: The first power voltage line 172 may be electrically connected to the second electrode CE2 of the first storage capacitor Cst1 through a contact hole 64 (see FIG. 7) defined in the first interlayer insulating layer 114, the third gate insulating layer 115, and the second interlayer insulating layer 116.; Fig. 7: 172, 64, CE2; Fig. 8: 172, CE2].
Regarding claim 15, Seo discloses the write scan line is spaced apart from the connecting pattern in a second direction crossing the first direction, when viewed in the plan view [e.g., Paragraph 121: The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, the first initialization voltage line VIL1, and second initialization voltage line VIL2 may extend in the first direction (the x-direction) and be spaced apart from each other in each row.; Fig. 7: SL1(SL2), 172, VIL2, SL4, y].
In the plan view of FIG. 7 the second gate electrode G2 and the row of the first scan line SL1 lie on the far side of the second initialization voltage line VIL2 and the fourth scan line SL4 from the first power voltage line 172 in the y-direction.
With the first scan line SL1 routed in the layer on the second interlayer insulating layer 116 as set out for claim 1 above, in either alternative, the line serves the second gate electrode G2 in that row and lies in the layer of the first power voltage line 172 and of the second initialization voltage line VIL2, which is the row line of that layer lying between the two, and so remains spaced apart from the first power voltage line 172 in the y-direction.
Regarding claim 17, Seo discloses the second gate electrode is disposed on a same layer as the first gate electrode [e.g., Seo, Paragraph 183: The first gate electrode G1 of the first transistor T1, the second gate electrode G2 of the second transistor T2, the fifth gate electrode G5 of the fifth transistor T5, the sixth gate electrode G6 of the sixth transistor T6, and the seventh gate electrode G7 of the seventh transistor T7 may be arranged on the first gate insulating layer 112.]
Seo does not expressly disclose the second gate electrode connected to the write scan line through a contact hole, the second gate electrode G2 being a portion of the first scan line SL1 [e.g., Seo, Paragraph 184: The second gate electrode G2 of the second transistor T2 may be a portion of the first scan line SL1 crossing the semiconductor layer AS of the second gate electrode G2.].
Ono discloses the gate conductor of the silicon transistor, in the first gate metal layer, coupled through a conductive via to its row control line in the SD1 layer [e.g., Ono, Paragraph 43: the GE1 gate conductor of silicon transistor 350 may be coupled to a corresponding SD1 conductor through conductive via 371; Fig. 3: GE1, 371, SD1; Fig. 5: GE1, SD1], and
in the alternative Feng discloses the gate line sections that form the gate electrode of the data writing transistor, in the layer of the gate electrode of the driving transistor, connected to the gate connection line through via holes [e.g., Feng, Paragraph 68: The first gate connection line 4G1 may be connected to a plurality of first gate line sections G11 in a same first gate line G1 respectively through via holes.; Fig. 19: 4G1].
With the first scan line SL1 routed in the layer on the second interlayer insulating layer 116 as set out for claim 1 above, the second gate electrode G2 remains on the first gate insulating layer 112 with the first gate electrode G1 and is connected to the line through a contact hole, for the reasons given for claim 1.
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (US 2025/0089489 A1) as applied to claims 1 and 11 above, and further in view of Toya et al. (US 2013/0257698 A1);
or, in the alternative, under 35 U.S.C. 103 as being unpatentable over Seo et al. (US 2022/0310736 A1) in view of Ono et al. (US 2021/0305353 A1) as applied to claims 1 and 11 above, and further in view of Toya et al. (US 2013/0257698 A1);
or, in the alternative, under 35 U.S.C. 103 as being unpatentable over Seo et al. (US 2022/0310736 A1) in view of Ono et al. (US 2021/0305353 A1) and Feng et al. (US 2025/0089489 A1) as applied to claims 1 and 11 above, and further in view of Toya et al. (US 2013/0257698 A1).
Claim 2 depends from claim 1, and claim 16 depends from claim 11, which depends from claim 1.
Each of claims 2 and 16 therefore includes every limitation of the claims from which it depends (35 U.S.C. 112(d)), including the limitation added to claim 1 by the amendment filed 30 September 2026, “a resistance of the write scan line is less than a resistance of the first gate electrode”, which is met in each alternative as set out for claim 1 above.
Regarding claim 2, the claim recites the write scan line is overlapped with at least a portion of the first gate electrode, when viewed in a plan view.
Feng discloses the first gate connection line 4G1 in the fourth conductive layer, above the first conductive part 11 in the stack, extending in the first direction beside the second conductive part 22 that overlaps the first conductive part 11 [e.g., Feng, Paragraph 65: An orthographic projection of the second conductive part 22 on the base substrate may be overlapped with the orthographic projection of the first conductive part 11 on the base substrate, and the second conductive part 22 may be used to form the second electrode of the capacitor C.; Fig. 19: 4G1, 22], and does not expressly disclose the first gate connection line 4G1 overlapping the first conductive part 11 when in a plan orientation.
Toya discloses an organic light-emitting diode pixel circuit in which the scanning line that is connected to the gate of the write-in transistor is formed in a wiring layer above the gate electrodes, is connected to the gate electrode of the write-in transistor through a contact hole, and overlaps the gate electrode of the drive transistor when viewed in plan view [e.g., Toya, Paragraph 115: a first interlayer insulation layer L1 is formed to cover the gate electrodes G1 to G5 and the gate insulation layers L0; Paragraph 116: In addition to a scanning line 12, a feed line 116 and control lines 143 to 145 being respectively formed on the surface of the first interlayer insulation layer L1 for each row through patterning of a conductive wiring layer made of aluminum or the like; Paragraph 118: As shown in FIG. 5, the scanning line 12 is provided to intersect the gate electrode G1 and the gate electrode G2 when viewed in plan view in addition to extending in the X direction.; Paragraph 118: That is, when viewed in plan view, at least a portion of the scanning line 12 and at least a portion of the gate electrode G1 overlap.; Paragraph 118: In addition, the scanning line 12 is electrically connected to the gate electrode G2 through a contact hole Ha5.; Paragraph 110: the transistor 122 has the gate electrode G2; Paragraph 93: the transistor 122 is electrically connected between the transistor 121 and the data line 14 and functions as a write-in transistor; Paragraph 109: the transistor 121 has the gate electrode G1; Paragraph 94: This transistor 121 functions as a drive transistor that flows a current that depends on the voltage between the gate and the source of the transistor 121.; Fig. 5: 12, G1, G2, Ha5; Fig. 6: 12, L1, G1],
the scanning line passing over the gate electrode in the wiring layer that also carries, over the same gate electrode, the relay node connected to that gate electrode and the second electrode of the storage capacity [e.g., Toya, Paragraph 121: the relay node N11 is electrically connected to the P-type diffusion layer P4 through a contact hole Ha6 in addition to being electrically connected to the gate electrode G1 through a contact hole Ha2; Paragraph 122: The relay node N16 is provided so that the relay node N16 and a portion of the gate electrode G1 mutually overlap when viewed in plan view.; Fig. 5: 12, N11, N16, G1].
Feng and Toya are analogous art because they are from the same field of endeavor as the claimed invention, organic light-emitting diode pixel circuits and the routing of their scan lines; Toya’s circuit may be formed on a glass substrate using a polysilicon process [e.g., Toya, Paragraph 216: the electro-optical device 1 may be formed on a glass substrate or the like using a polysilicon process or the like; Paragraph 99: the transistors may be thin film transistors or electric field effect transistors].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to route Feng’s first gate connection line 4G1 so that it overlaps at least a portion of the first conductive part 11 when viewed in a plan view, passing over it beside the fourth bridging part 44 as Toya’s scanning line passes over the gate electrode beside the relay node N11,
because Toya teaches that wiring the scanning line on the gate of the drive transistor relaxes the restrictions on space in providing the scanning line and permits pixel circuits of higher density and a display of higher definition [e.g., Toya, Paragraph 8: since the scanning line is wired on the gate of the drive transistor, in comparison with a case in which the scanning line is wired not to intersect the gate of the drive transistor, the restrictions on space can be relaxed when providing the scanning line; Paragraph 8: it is possible to dispose a plurality of pixel circuits at a higher density, and a higher definition of display and a smaller display size are possible], and
Feng likewise arranges its row lines to reduce the size of the pixel driving circuit in the second direction [e.g., Feng, Paragraph 64: which arrangement may reduce the size of the pixel driving circuit in the second direction Y].
Toya recognizes that a parasitic capacity exists between the scanning line and the gate electrode that it crosses, and exists as well between a row line and the gate electrode that it does not cross [e.g., Toya, Paragraph 176: Therefore, there is a parasitic capacity between the scanning line 12 and the gate electrode G1.; Paragraph 210: Even in a case in which the control line is provided not to intersect the gate electrode G1, there is a parasitic capacity between the control line and the gate electrode G1.], and
in Feng the signal of the first gate line is already coupled to the gate electrode of the driving transistor through the third conductive part 13 [e.g., Feng, Paragraph 69: the voltage of the first conductive part electrically connected to the twentieth active part 820 is pulled up by the effect of the coupling of parasitic capacitance between the third conductive part 13 and the twentieth active part 820; Fig. 6: G11, 13], so the routing of the line over at least a portion of the gate electrode would have been made with a reasonable expectation of success.
KSR, 550 U.S. 398; Graham, 383 U.S. 1.
In the alternative, over Seo in view of Ono as applied to claim 1 above and further in view of Toya, and over Seo in view of Ono and Feng as applied to claim 1 above and further in view of Toya:
Seo discloses the first scan line SL1 extending in the first direction in a row apart from the first gate electrode G1 [e.g., Seo, Fig. 7: SL1(SL2), G1] and does not expressly disclose the write scan line overlapping the first gate electrode when in a plan orientation; neither does Ono, whose Fig. 5 is schematic [e.g., Ono, Fig. 5: SD1, GE1], nor, in the second of these alternatives, Feng, as set out above.
Toya discloses the scanning line of the write-in transistor, in a wiring layer above the gate electrodes, overlapping the gate electrode of the drive transistor when viewed in plan view, as set out above.
Seo, Ono and Toya, and in the second of these alternatives Feng, are analogous art because they are from the same field of endeavor as the claimed invention, organic light-emitting diode pixel circuits and the routing of their scan lines.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, in routing Seo’s first scan line SL1 in the layer on the second interlayer insulating layer 116 as set out for claim 1 above, in either alternative, to route it so that it overlaps at least a portion of the first gate electrode G1 when viewed in a plan view, passing over the first gate electrode among the first power voltage line 172 and the node connection line 171 as Toya’s scanning line passes over the gate electrode among the relay nodes N11 and N16, the portions of the first scan line that form the second gate electrode G2 and the fourth electrode CE4 being left on the first gate insulating layer 112 and connected to the line through a contact hole as set out for claim 1,
because Toya teaches that wiring the scanning line on the gate of the drive transistor relaxes the restrictions on space in providing the scanning line and permits pixel circuits of higher density and a display of higher definition [e.g., Toya, Paragraph 8: since the scanning line is wired on the gate of the drive transistor, in comparison with a case in which the scanning line is wired not to intersect the gate of the drive transistor, the restrictions on space can be relaxed when providing the scanning line; Paragraph 8: it is possible to dispose a plurality of pixel circuits at a higher density, and a higher definition of display and a smaller display size are possible], and
Seo is likewise directed to a high-resolution display [e.g., Seo, Paragraph 282: because the first pixel circuit PC1 and the second pixel circuit PC2 may be provided in the same size, a high-resolution display apparatus may be implemented].
Toya recognizes that a parasitic capacity exists between the scanning line and the gate electrode that it crosses, and exists as well between a row line and the gate electrode that it does not cross [e.g., Toya, Paragraph 176: Therefore, there is a parasitic capacity between the scanning line 12 and the gate electrode G1.; Paragraph 210: Even in a case in which the control line is provided not to intersect the gate electrode G1, there is a parasitic capacity between the control line and the gate electrode G1.], and
in Seo the first scan signal is already coupled to the gate electrode of the first transistor through the third storage capacitor [e.g., Seo, Paragraph 207: when a first scan signal Sn having a turn-off level is supplied to the first scan line, the third storage capacitor Cbt may raise the voltage of the node N2 (see FIG. 6) to securely turn-off the first transistor T1 to clearly express a black grayscale], so the routing of the line over at least a portion of the gate electrode would have been made with a reasonable expectation of success.
KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Regarding claim 16, the claim recites the write scan line is overlapped with at least a portion of the capacitor electrode, when viewed in the plan view.
Neither Feng, nor Seo, nor Ono, nor Toya expressly discloses the write scan line overlapping the capacitor electrode when in the plan orientation.
In Feng the capacitor electrode, the second conductive part 22, overlaps the first conductive part 11 except at the opening in which the first conductive part is contacted [e.g., Feng, Paragraph 65: An orthographic projection of the second conductive part 22 on the base substrate may be overlapped with the orthographic projection of the first conductive part 11 on the base substrate; Paragraph 68: an opening 221 is formed in the second conductive part 22, and an orthographic projection of the second via hole H2 on the base substrate is within an orthographic projection of the opening 221 on the base substrate to insulate the second via hole H2 from the second conductive part 22; Fig. 7: 22, 221; Fig. 15: 11; Fig. 16: 22], and
in Seo the capacitor electrode, the second electrode CE2, overlaps the first gate electrode G1 except at the opening in which the first gate electrode is contacted [e.g., Seo, Paragraph 188: The second electrode CE2 may be arranged on the second gate insulating layer 113 to overlap the first electrode CE1.; Paragraph 188: The second electrode CE2 may include an opening SOP.; Paragraph 188: The opening SOP is formed by removing a portion of the second electrode CE2 and may have a closed shape.; Paragraph 207: In addition, the third electrode CE3 may be electrically connected to the first gate electrode G1 through the contact hole 63.; Fig. 8: G1, CE2, SOP, 63].
With the write scan line routed over a portion of the first gate electrode in view of Toya as set out for claim 2 above, in each alternative, the line, extending in the first direction across the first gate electrode, passes over the capacitor electrode that covers the first gate electrode around that opening, and the write scan line is overlapped with at least a portion of the capacitor electrode, for the reasons given for claim 2.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1–17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues that “Seo is totally silent with regard to a resistance of the fourth electrode CE4 and a resistance of the first gate electrode G1, the connection electrode 161, the node connection line 171 or the fifth electrode CE5” and that “neither Lee, Kim nor Lee2 cures the deficiency in Seo” (Remarks, page 7).
The limitation added to claim 1 by the amendment is met by Feng in the rejections of paragraphs 11 and 13 above and by Ono, and in the alternative by Ono and Feng, in the rejections of paragraphs 12 and 13 above; Seo is not relied upon for it.
Election/Restrictions
Claims 18–20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to at least a nonelected species/invention, there being no allowable generic or linking claim.
Election was made without traverse in the reply filed on 24 June 2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Park Junhyun et al. (US 2022/0270542 A1) relates to a display in which a horizontal line of the pixel is formed of the source-drain metal layer, which has a resistance lower than that of the gate metal layer.
Qing (US 2024/0185780 A1) relates to a pixel in which a gate line in a third conductive layer of lower sheet resistance than the first conductive layer is connected through a via to the gate of the writing transistor.
Kim Myeong Ho et al. (US 2023/0090058 A1) relates to a pixel having silicon and oxide transistors in which a scan line in a data conductive layer is connected through a contact hole to a gate electrode in a gate layer.
Kim Seong-Min et al. (US 2022/0028944 A1) relates to a pixel in which a scan line in a data conductive layer is connected through an opening to an island-shaped gate electrode.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
1 October 2026
