DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102 / 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-17 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Seo et al (US 2022/0310736 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Seo et al (US 2022/0310736 A1) in view of Lee et al (US 2023/0107292 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Seo et al (US 2022/0310736 A1) in view of Lee et al (US 2023/0107292 A1) and Kim et al (US 2021/0367209 A1);
or, in the alternative, under 35 U.S.C. 103 as obvious over Seo et al (US 2022/0310736 A1) in view of Lee et al (US 2023/0107292 A1) and Lee (US 2020/0243017 A1).
Regarding claim 1, Seo discloses an electronic device comprising:
a light emitting element [e.g., Fig. 6: OLED];
a data line [e.g., Fig. 6: DL] configured to provide a data signal [e.g., Fig. 6: Dm];
a pixel circuit connected to the light emitting element; and
a plurality of scan lines connected to the pixel circuit, wherein the plurality of scan lines include:
an initializing scan line [e.g., Fig. 6: SL3; Paragraph 173: the third scan line SL3 may include a lower scan line 143 and an upper scan line 163 arranged in different layers. The lower scan line 143 may be arranged in the same layer as the second electrode CE2 of the first storage capacitor Cst1. The upper scan line 163 may be arranged on the third gate insulating layer 115] extending in a first direction [e.g., Fig. 6, 8: horizontally; Paragraph 121: x-direction] and providing an initializing scan signal [e.g., Fig. 6: Sn-1]; and
a write scan line [e.g., Fig. 6: SL1; Paragraph 169: The fourth electrode CE4 of the third storage capacitor Cbt may be provided as a portion of the first scan line SL1; Paragraph 183: A portion of the first scan line SL1 may be the fourth electrode CE4] extending in the first direction and providing a write scan signal [e.g., Fig. 6: Sn],
wherein the pixel circuit includes:
a first transistor [e.g., Fig. 6: T1] including a first semiconductor pattern [e.g., Fig. 8: AS1] which includes a first electrode [e.g., Fig. 8: S1] and a second electrode [e.g., Fig. 7: D1] and includes a first material [e.g., Paragraph 161: silicon semiconductor], and a first gate electrode [e.g., Fig. 6: G1 or 161 or 171 or CE5];
a second transistor [e.g., Fig. 6: T2] including a second gate electrode [e.g., Fig. 7: G2] which receives the write scan signal, and connected between the first electrode and the data line (e.g., see Fig. 6); and
a third transistor [e.g., Fig. 6: T4] including a second semiconductor pattern [e.g., Fig. 8: AO1] including a second material [e.g., Paragraph 161: oxide semiconductor] different from the first material, receiving the initializing scan signal and connected to the first gate electrode (e.g., see Fig. 6), and
wherein the initializing scan line, the write scan line, and the first gate electrode are disposed on different layers [e.g., Fig. 6: “initializing scan line” = (“same layer as the second electrode CE2” or “arranged on the third gate insulating layer 115”) is on a 1st layer; “write scan line” = CE4 is on a 2nd layer; “first gate electrode” = (G1 or 161 or 171 or CE5) is on a 3rd layer] from each other (e.g., see Paragraphs 58-288).
Should it be shown Seo discloses the initializing scan line and the write scan line being disposed on different layers from each other, as instantly claimed, with insufficient specificity:
Lee (‘292) discloses the initializing scan line [e.g., Fig. 9B: Gwi in layer MP1], the write scan line [e.g., Fig. 9C: GI i in layer MP2] are disposed on different layers from each other (e.g., see Fig. 7; Paragraphs 51-248).
Seo and Lee (‘292) are analogous art, because they are from the shared inventive field of light emitting diode display devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Lee (‘292)’s different layered scan lines with Seo’s scan lines, so to as prevent damage due to an external impact or stress.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Lee (‘292)’s different layered scan lines with Seo’s scan lines as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Should it be shown Seo and Lee (‘292) discloses the initializing scan line, the write scan line, and the first gate electrode are disposed on different layers from each other, as instantly claimed, with insufficient specificity:
Kim discloses the initializing scan line [e.g., Fig. 1: GI line = Fig. 2: SL2; Paragraph 61], the write scan line [e.g., Fig. 1: GW = Fig. 2: SL1; Paragraph 60], and the first gate electrode [e.g., Fig. 1: TR gate = Fig. 2: GE1; Paragraph 63] are disposed on different layers from each other [e.g., Paragraph 65: at least one of the first gate electrode GE1 or the first to third scan lines SL1, SL2 or SL3 may be formed or located in a different layer from others].
Seo, Lee (‘292) and Kim are analogous art, because they are from the shared inventive field of light emitting diode display devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Kim’s different layers with Seo’s and Lee (‘292)’s scan lines and gate electrode, so to as to improve display quality.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Kim’s different layers with Seo’s and Lee (‘292)’s scan lines and gate electrode as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Alternatively, should it be shown Seo and Lee (‘292) discloses the initializing scan line, the write scan line, and the first gate electrode are disposed on different layers from each other, as instantly claimed, with insufficient specificity:
Lee (‘017) discloses the initializing scan line [e.g., Fig. 3: SL[j-1] ], the write scan line [e.g., Fig. 3: SL[j] ], and the first gate electrode [e.g., Fig. 3: G1] are disposed on different layers from each other [e.g., Paragraph 115: the first scan line (SLi), the first scan line (SLi-1), the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, the fourth gate electrode G4, the fifth gate electrode G5, the sixth gate electrode G6, and the seventh gate electrode G7 may be selectively provided on different layers and may be formed of different materials].
Seo, Lee (‘292) and Lee (‘017) are analogous art, because they are from the shared inventive field of light emitting diode display devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Lee (‘017)’s different layers with Seo’s and Lee (‘292)’s scan lines and gate electrode, so that resolution of the display device may be increased and display quality of the display device may be improved.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Lee (‘017)’s different layers with Seo’s and Lee (‘292)’s scan lines and gate electrode as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Regarding claim 2, Seo discloses the write scan line is overlapped with at least a portion of the first gate electrode, when viewed in a plan view (e.g., see Fig. 8; Paragraphs 151-174).
Regarding claim 3, Seo discloses a first initializing voltage line [e.g., Fig. 6: VIL1] disposed on a same layer the first gate electrode, extending in the first direction, and providing a first initializing voltage [e.g., Fig. 6: Vint1] (e.g., see Paragraphs 119-121, 126, 136, 166, 175, 191, 196, 217, 223).
Regarding claim 4, Seo discloses the first initializing voltage line is electrically connected to the second semiconductor pattern (e.g., see Fig. 6; Paragraphs 119-121, 126, 136, 166, 175, 191, 196, 217, 223).
Regarding claim 5, Seo discloses the first initializing voltage line is disposed on a different layer from the write scan line (e.g., see Figs. 6, 8; Paragraphs 119-121, 126, 136, 166, 175, 191, 196, 217, 223).
Regarding claim 6, Seo discloses the plurality of scan lines further include:
a compensating scan line [e.g., Fig. 6: SL4] extending in the first direction and providing a compensating scan signal [e.g., Fig. 6: Sn’], and
wherein the pixel circuit further includes: a fourth transistor [e.g., Fig. 6: T3] including a fourth gate electrode which receives the compensating scan signal, the second semiconductor pattern, and electrically connected between the second electrode and the first gate electrode (e.g., see Figs. 6-8; Paragraphs 117-174).
Regarding claim 7, Seo discloses the compensating scan line is disposed on a same layer as the initializing scan line, and the compensating scan line and the initializing scan line are spaced apart from each other in a second direction crossing the first direction (e.g., see Figs. 6-8; Paragraphs 119, 121, 125, 137, 145, 165, 174, 191, 192, 198-200, 217, 223).
Regarding claim 8, Seo discloses the compensating scan line is disposed on a different layer from the write scan line (e.g., see Figs. 6-8; Paragraphs 119, 121, 125, 137, 145, 165, 174, 191, 192, 198-200, 217, 223).
Regarding claim 9, Seo discloses the plurality of scan lines further include:
a light emitting control line [e.g., Fig. 6: EL] extending in the first direction and providing a light emitting control signal [e.g., Fig. 6: En], and
wherein the pixel circuit further includes: a fifth transistor [e.g., Fig. 6: T5] connected to the first electrode receiving the light emitting control signal (e.g., see Paragraphs 119-283).
Regarding claim 10, Seo discloses the light emitting control line is disposed on a different layer from the write scan line (e.g., see Figs. 7-8; Paragraphs 119-283).
Regarding claim 11, Seo discloses the pixel circuit further includes:
a connecting pattern [e.g., Fig. 6: 161 or 171] disposed on a same layer as the write scan line; and
a capacitor electrode [e.g., Fig. 6: CE2] overlapped with the first gate electrode, when viewed in a plan view (e.g., see Figs. 7-8; Paragraphs 119-283).
Regarding claim 12, Seo discloses a first driving voltage line [e.g., Fig. 7: 172] extending in a second direction [e.g., Fig. 7: Y] crossing the first direction and providing a first driving voltage [e.g., Paragraph 156: ELVDD],
wherein the connecting pattern is connected to the first driving voltage line through a contact hole [e.g., Fig. 6: 61, 62, 63] (e.g., see Figs. 7-8; Paragraphs 106, 120, 137-138, 156, 227).
Regarding claim 13, Seo discloses the first driving voltage line is disposed on a same layer as the data line (e.g., see Figs. 6-8; Paragraphs 106, 119-124, 137-138, 156-157, 171, 211-213, 217, 227).
Regarding claim 14, Seo discloses the connecting pattern is overlapped with the capacitor electrode, when viewed in the plan view (e.g., see Figs. 7-8; Paragraphs 106, 120, 137-138, 156, 227).
Regarding claim 15, Seo discloses the write scan line is spaced apart from the connecting pattern in a second direction [e.g., Fig. 7: Y, Fig. 8: Z, diagonals] crossing the first direction, when viewed in the plan view (e.g., see Figs. 7-8; Paragraphs 106, 119-124, 133-138, 145-148, 156, 169-172, 183-184, 217-236).
Regarding claim 16, Seo discloses the write scan line is overlapped with at least a portion of the capacitor electrode, when viewed in the plan view (e.g., see Figs. 7-8; Paragraphs 106, 119-124, 133-138, 145-148, 156, 169-172, 183-184, 217-236).
Regarding claim 17, Seo discloses the second gate electrode is disposed on a same layer as the first gate electrode, and wherein the second gate electrode is connected to the write scan line through a contact hole (e.g., see Figs. 7-8; Paragraphs 157, 169, 183-184, 228, 230, 286).
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 24 June 2026 is acknowledged.
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to at least a nonelected species/invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 24 June 2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The documents listed on the attached 'Notice of References Cited' are cited to further evidence the state of the art pertaining to electronic devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached on Monday - Friday (7:30AM - 4PM). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
27 June 2026
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