DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 12 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8 and 16 of U.S. Patent No. 12, 401,359. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of the instant application differ from the claim of US patent only in that the gate terminal is biased using a bias generator circuit rather than being connected directly to the source node. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the device of US Patent application to utilize bias generator circuit to bias the gate terminal of the circuit for a direct source connection does not yield any unpredictable results. In the absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Accordingly, the claims of the instant application are not patentably distinct from the claims of the Patent application.
Regarding claims 12 and 18 see table below.
Instant Application No. 19/278, 617
US Patent No. 12, 401,359
12. An electronic device, comprising: a semiconductor substrate; a bidirectional transistor formed on the semiconductor substrate and including a first source node, a second source node and a common drain node;
a first transistor formed on the semiconductor substrate and including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the semiconductor substrate, the first drain terminal connected to the first source node and the first gate terminal connected directly to a bias generator circuit; and
a second transistor formed on the semiconductor substrate and including a second source terminal, a second drain terminal and a second gate terminal, the second source terminal connected to the semiconductor substrate, wherein the second transistor is arranged to couple the second source node to the semiconductor substrate when a voltage at the first source node is greater than a voltage at the semiconductor substrate.
8. An electronic device, comprising: a semiconductor substrate; a switch formed on the semiconductor substrate and including a first source node, a second source node and a common drain node;
a first transistor formed on the semiconductor substrate and including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the semiconductor substrate, the first drain terminal connected to the first source node and the first gate terminal connected directly to the second source node; and
a second transistor formed on the semiconductor substrate and including a second source terminal, a second drain terminal and a second gate terminal, wherein the second transistor is arranged to couple the second source node to the semiconductor substrate when a voltage at the first source node is greater than a voltage at the semiconductor substrate.
18. A method of forming a circuit, the method comprising: forming a semiconductor substrate; forming a bidirectional transistor on the semiconductor substrate, the bidirectional transistor including a first source node, a second source node and a common drain node; forming a first transistor on the semiconductor substrate, the first transistor including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the semiconductor substrate, the first drain terminal connected to the first source node and the first gate terminal connected directly to a bias generator circuit; and forming a second transistor on the semiconductor substrate, the second transistor including a second source terminal, a second drain terminal and a second gate terminal, the second source terminal connected to the semiconductor substrate, the second drain terminal connected to the second source node, wherein the second transistor is arranged to transition from an off state to an on state when a voltage at the first source node is greater than a voltage at the semiconductor substrate.
16. A method of forming a circuit, the method comprising: forming a semiconductor substrate; forming a bidirectional transistor on the semiconductor substrate, the bidirectional transistor including a first source node, a second source node and a common drain node; forming a first transistor on the semiconductor substrate, the first transistor including a first source terminal, a first drain terminal and a first gate terminal, the first source terminal connected to the semiconductor substrate, the first drain terminal connected to the first source node and the first gate terminal connected directly to the second source node; and forming a second transistor on the semiconductor substrate, the second transistor including a second source terminal, a second drain terminal and a second gate terminal, the second source terminal connected to the semiconductor substrate, the second drain terminal connected to the second source node, wherein the second transistor is arranged to transition from an off state to an on state when a voltage at the first source node is greater than a voltage at the semiconductor substrate.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a) (1) as being anticipated by
Imam et al. (US 2019/0326280 and Imam hereinafter).
Regarding claim 1, Imam discloses an electronic device [figs. 2, 6-7 and 9-11B], comprising: a gallium nitride (GaN) [fig. 9] based top layer [202, fig. 9, par. 0038] attached to a semiconductor substrate [200, figs. 9-10B]; a transistor [100, figs. 2 and 9] formed on the GaN-based top layer and including a first source node [S1, figs. 2 and 9], a second source node [S2, figs. 2 and 9] and a common drain node [node between Q1 and Q2, figs. 2 and 9]; and a circuit [102, fig. 2 ] having a first terminal [terminal D3] and a second terminal [terminal D4], the first terminal connected to the first source node and the second terminal connected to the second source node; and wherein the circuit is arranged to connect the second source node [S2] to the semiconductor substrate when a voltage at the first source node [Vss2] is greater than a voltage at the semiconductor substrate [para. 0029-0032].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5-9 and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Imam et al. in view of Kinoshita et al. (US 2019/0006499 and Kinoshita hereinafter).
Regarding claim 2, Imam discloses all the features with respect to claim 1 as outlined above. Imam further discloses wherein the transistor is a bidirectional transistor [100, fig. 2, para. 0038], and wherein the circuit comprises: a first transistor [Q3] formed on the GaN-based top layer and including a first source terminal [S3], a first drain terminal [drain Q3] and a first gate terminal [G3], the first source terminal connected to the semiconductor substrate, the first drain terminal connected to the first source node [S1] and the first gate terminal [G3], and a second transistor [Q4] formed on the GaN-based top layer and including a second source terminal [S4], a second drain terminal [drain Q4] and a second gate terminal [G4], the second source terminal connected to the semiconductor substrate, the second drain terminal connected to the second source node [S2] and the second gate terminal [G4]. Imam does not explicitly disclose wherein the first gate terminal and the second gate terminal connected directly to a bias generator circuit.
However, Kinoshita discloses [fig. 9] first gate terminal [G12] and second gate terminal [G11] connected directly to a bias generator circuit [102]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Imam by incorporating bias generator circuit as taught in Kinoshita in order to provide a bias voltage to the circuit.
Regarding claim 3, Imam in view of Kinoshita discloses [fig. 2] further comprising: a first diode [Sb1] including a first anode and a first cathode, the first anode connected to the semiconductor substrate and the first cathode connected to the first source node; and a second diode [Sb2] including a second anode and a second cathode, the second anode connected to the semiconductor substrate and the second cathode connected to the second source node.
Regarding claim 5, Imam in view of Kinoshita discloses wherein the first and second diodes are monolithically formed on the GaN-based top layer [par. 20].
Regarding claim 6, Imam in view of Kinoshita discloses wherein the semiconductor first and second diodes are silicon carbide (SiC)-based [par. 20].
Regarding claim 7, Imam in view of Kinoshita discloses [see fig. 22] wherein the GaN-based top layer attached to the semiconductor substrate is formed on a first die [400], and the first and second diodes are formed on a second die [die Sb1 and Sb2 mounted], wherein the first and second die are co-packaged in a unitary semiconductor package.
Regarding claim 8, Imam in view of Kinoshita discloses wherein the first and second transistors are enhancement-mode field effect transistors (FETs) [par. 0038-0039].
Regarding claim 9, Imam in view of Kinoshita discloses [fig. 2] wherein the first and the second transistors each comprise two or more field effect transistors (FETs) connected in series.
Regarding claim 12, Imam discloses an electronic device [see figs. 2 and 9], comprising: a semiconductor substrate [200/SUB, fig. 9]; a bidirectional transistor [100, fig. 2] formed on the semiconductor substrate and including a first source node [node S1], a second source node [node Vss2] and a common drain node [node between Q1 and Q2]; a first transistor [Q3] formed on the semiconductor substrate and including a first source terminal [S3], a first drain terminal [D3] and a first gate terminal [G3], the first source terminal connected to the semiconductor substrate, the first drain terminal connected to the first source node [S1] and the first gate terminal [S3]; and a second transistor [Q4] formed on the semiconductor substrate and including a second source terminal [S4], a second drain terminal [D4] and a second gate terminal [G4], the second source terminal connected to the semiconductor substrate, wherein the second transistor is arranged to couple the second source node [S2] to the semiconductor substrate when a voltage at the first source node [Vss1] is greater than a voltage at the semiconductor substrate [para. 0029-0032]. Imam does not explicitly disclose wherein the first gate terminal connected directly to a bias generator circuit.
However, Kinoshita discloses [fig. 9] first gate terminal [G12] and second gate terminal [G11] connected directly to a bias generator circuit [102]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Imam by incorporating bias generator circuit as taught in Kinoshita in order to provide a bias voltage to the circuit.
Regarding claim 13, Imam in view of Kinoshita [see fig. 2] wherein the second drain terminal [D4] is connected to the second source node [node at Vss2] and the second gate terminal [G4] is connected directly to the bias generator circuit.
Regarding claim 14, Imam in view of Kinoshita [see fig. 2] wherein the first transistor [Q3] is arranged to couple the first source node to the semiconductor substrate in response to a voltage of the second source node [Vss2] being at a voltage that is higher than a voltage of the semiconductor substrate [para. 0029-0032].
Regarding claim 15, Imam in view of Kinoshita [see fig. 2] further comprising: a first diode [Sb1] including a first anode and a first cathode, the first anode connected to the semiconductor substrate and the first cathode connected to the first source node; and a second diode [Sb2] including a second anode and a second cathode, the second anode connected to the substrate and the second cathode connected to the second source node.
Regarding claim 16, Imam in view of Kinoshita wherein the first and second diodes are monolithically formed on the semiconductor substrate [par. 20].
Regarding claim 17, Imam in view of Kinoshita wherein the first and second diodes are formed on one or more silicon carbide (SiC) substrates [par. 20].
Regarding claim 18, Imam discloses a method of forming a circuit [figs. 2 and 9], the method comprising: forming a semiconductor substrate [200/SUB, fig. 9]; forming a bidirectional transistor [100, fig. 2] on the semiconductor substrate, the bidirectional transistor including a first source node [node S1], a second source node [node S2] and a common drain node [node between Q1 and Q2]; forming a first transistor [Q3] on the semiconductor substrate, the first transistor including a first source terminal [S3], a first drain terminal [D3] and a first gate terminal [G3], the first source terminal connected to the semiconductor substrate, the first drain terminal connected to the first source node and the first gate terminal; and forming a second transistor [Q4] on the semiconductor substrate, the second transistor including a second source terminal [S4], a second drain terminal [D4] and a second gate terminal [G4], the second source terminal connected to the semiconductor substrate, the second drain terminal connected to the second source node, wherein the second transistor is arranged to transition from an off state to an on state when a voltage at the first source node is greater than a voltage at the semiconductor substrate [para. 0029-0032]. Imam does not explicitly disclose wherein the first gate terminal connected directly to a bias generator circuit.
However, Kinoshita discloses [fig. 9] first gate terminal [G12] and second gate terminal [G11] connected directly to a bias generator circuit [102]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Imam by incorporating bias generator circuit as taught in Kinoshita in order to provide a bias voltage to the circuit.
Regarding claim 19, Imam in view of Kinoshita [see fig. 2] further comprising: forming a first diode [Sb1] including a first anode and a first cathode, the first anode connected to the semiconductor substrate and the first cathode connected to the first source node; and forming a second diode [Sb2] including a second anode and a second cathode, the second anode connected to the semiconductor substrate and the second cathode connected to the second source node.
Regarding claim 20, Imam in view of Kinoshita [see fig. 2] wherein the second drain terminal [D4] is connected to the second source node and the second gate terminal [G4] is connected directly to the bias generator circuit.
Allowable Subject Matter
Claims 4 and 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the closest prior art Imam and Kinoshita [see fig. 2], does not disclose wherein the bias generator circuit comprises a third transistor formed on the GaN-based top layer and including a third drain, a third source and a third gate, the third gate connected to a voltage source, the third drain connected to the first source node and the third source connected to the second gate terminal, and a fourth transistor formed on the GaN-based top layer and including a fourth drain, a fourth source and a fourth gate, the fourth gate connected to the voltage source, the fourth drain connected to the second source node, and the fourth source connected to the first gate terminal.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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