DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is made in response to applicant’s amendment submitted on 06/24/2026. Claims 1, 3-4 and 7 have been amended. Claim 2 has been cancelled. Claim 14 has been newly added. Claims 1 and 3-14 are currently pending in the application.
Response to Argument
Applicant’s argument filed on 06/24/2026 has been fully considered but it is not persuasive.
Applicant submits “However, none of cited references including Moon and Zhou teaches "wherein the gate lines includes an odd gate line and an even gate line; and wherein the first pixel unit is connected to the odd gate line and the second pixel unit is connected to the even gate line" recited in amended claim 1.” (Remarks, page 9, the first paragraph)
Examiner respectfully disagrees with Applicant’s premises and conclusions. Zhou teaches the gate lines include an odd gate line and an even gate line as seen in figure 10. There are odd gate lines S1, S3, S5, etc. and there are even gate lines S2, S4, S6, etc.. Also as seen in figure 10, first pixel unit (Pixel 1) is connected to the odd gate line S1; and second pixel unit (Pixel 2) is connected to the even gate line S2. Therefore, Zhou teaches the amended claim limitation “wherein the gate lines includes an odd gate line and an even gate line; and wherein the first pixel unit is connected to the odd gate line and the second pixel unit is connected to the even gate line”. As above, if Applicant believes that the current invention is different from Examiner’s interpretation of the prior art, the claim language should be amended to reflect the difference and more clearly define Applicant’s invention. However, based on the currently pending claim language, Examiner maintains the rejections of the independent claim 1.
Claim Objections
Claim 1 is objected to because of the following informalities: the limitation “wherein the gate lines includes an odd gate line and an even line” in line 18 should be “wherein the gate lines include an odd gate line and an even line”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. (US. Pub. No. 2011/0032249, hereinafter “Moon”) in view of Zhou et al. (US. Pub. No. 2017/0061872, hereinafter “Zhou”).
As to claim 1, (Currently Amended) Moon discloses a display device [figure 1, display device] comprising:
a data drive integrated circuit (IC) [figure 1, data driver 4 includes a plurality of data ICs, paragraph 9, The data driver includes a plurality of data ICs for converting digital data signals to analog data signals and providing the analog data signals to the data lines of the liquid crystal panel] configured to output a data voltage through a data channel;
data lines arranged in a first direction [figure 1, data lines DLm arranged in a first direction, transmitting the data signals to the subpixels RGB], the data lines transmitting the data voltage to subpixels;
a gate drive IC configured to output a gate signal [figure 1, a gate drive IC to output a gate signal GL, paragraph 8, the gate driver includes a plurality of gate ICs for sequentially driving the gate lines];
gate lines arranged in a second direction, the gate lines transmitting the gate signal to the subpixels [figure 1, gate lines GL arranged in a second direction, transmitting gate signals to the subpixels RGB, paragraph 8, the gate driver includes a plurality of gate ICs for sequentially driving the gate lines];
pixel units [figure 1, pixel units RGB to share one data line DL1 from the data lines DLm] configured to share one data line from the data lines, each pixel unit comprising a first color subpixel, a second color subpixel, and a third color subpixel that are sequentially arranged in a same direction as a direction of the one data line [figure 1, first color subpixel, second color subpixel and third color subpixel RGB are sequentially arranged in a same direction as a direction of the data line DL1];
wherein the gate lines includes an odd gate line and an even gate line [figure 1, the gate lines GL includes an odd gate line GL1 and an even gate line GL2].
Moon does not expressly disclose a first multiplexer configured to transmit a data voltage output from a first data channel to a first data line from the data lines to which a first pixel unit is connected; and
a second multiplexer configured to transmit a data voltage output from the first data
channel to a second data line from the data lines to which a second pixel unit is connected;
wherein the first pixel unit is connected to the odd gate line and the second pixel unit is connected to the even gate line.
Zhou teaches a display device comprising a first multiplexer configured to transmit a data voltage output from a first data channel to a first data line from data lines to which a first pixel unit is connected [figure 10, a first multiplexer (most left transistor) configured to transmit a data voltage output (source) from a first data channel to a first data line (first data line on the left side) from data lines to which a first pixel unit Pixel 1 is connected]; and
a second multiplexer configured to transmit a data voltage output from the first data channel to a second data line from the data lines to which a second pixel unit is connected [figure 10, a second multiplexer (second left transistor) configured to transmit a data voltage output (source) from the first data channel to a second data line (second left data line) from the data lines to which a second pixel unit (Pixel 2) is connected];
wherein the gate lines includes an odd gate line and an even gate line [figure 10, gate lines include an odd gate line Sn1 and an even gate line Sn2];
wherein the first pixel unit is connected to the odd gate line and the second pixel unit is connected to the even gate line [figure 10, first pixel unit Pixel 1 is connected to the odd gate line Sn1 and the second pixel unit Pixel 2 is connected to the even gate line Sn2].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Moon to comprise a first multiplexer configured to transmit a data voltage output from a first data channel to a first data line from the data lines to which a first pixel unit is connected; and a second multiplexer configured to transmit a data voltage output from the first data channel to a second data line from the data lines to which a second pixel unit is connected; wherein the first pixel unit is connected to the odd gate line and the second pixel unit is connected to the even gate line, as taught by Zhou, in order to greatly reduce the number of the ICs and thereby the IC costs are lowered (Zhou, paragraph 57).
As to claim 3, (Currently Amended) Moon, as modified by Zhou, discloses the display device according to claim [[2]] 1, wherein the gate drive IC comprises a first gate drive IC arranged at one end of the gate lines and a second gate drive IC arranged at another end of the gate lines [Moon, figure 1, gate driver 6 includes a plurality of gate ICs (inherently a first gate drive IC arranged at one end of the gate lines and a second gate drive IC arranged at another end of the gate lines), Zhou, figure 7, a plurality of gate ICs (GOA1-GOA6), a first gate drive IC arranged at one end of the gate lines and a second gate drive IC arranged at another end of the gate lines]. In addition, the same rationale is used as in rejection for claim 1.
As to claim 4, (Currently Amended) Moon, as modified by Zhou, discloses the display device according to claim 3, wherein the first gate drive IC outputs a gate signal to [[an]] the odd gate line among the gate lines and the second gate drive IC outputs a gate signal to [[an]] the even gate line among the gate lines [Zhou, figure 7, the first gate drive IC GOA1 outputs a gate signal to an odd gate line Sn1 and second gate driver IC GOA6 outputs a gate signal to an even gate line Sn6]. In addition, the same rationale is used as in rejection for claim 1.
As to claim 5, (Original) Moon, as modified by Zhou, discloses the display device according to claim 3, wherein the first gate drive IC outputs a gate signal to subpixels included in the first pixel unit and the second gate drive IC outputs a gate signal to subpixels included in the second pixel unit [Moon, figure 1, first gate drive IC outputs a gate signal GL1 to subpixels included in the first pixel unit and the second gate drive IC outputs a gate signal to subpixels included in the second pixel unit].
As to claim 6, (Original) Moon, as modified by Zhou, discloses the display device according to claim 1, wherein the data drive IC outputs a data voltage corresponding to writing data to the first color subpixel, the second color subpixel, and the third color subpixel of the first pixel unit [Moon, figure 1, DL1 to write data to R, G and B of the first pixel unit], and a data voltage corresponding to writing data to the first color subpixel, the second color subpixel, and the third color subpixel of the second pixel unit to the first data channel [Moon, paragraph 37, a plurality of Red (R), Green (G) or Blue (B) color subpixels arranged on each horizontal line are commonly connected to at least one adjacent data line, and on at least one horizontal line basis, a plurality of R, G or B color subpixels are connected to their adjacent data line through their Thin Film Transistors (TFTs) in the same direction with respect to the data line, a data driver 4 for driving a plurality of data lines DL1 to DLm, a gate driver 6 for driving a plurality of gate lines GL1 to GLn, and a timing controller 8 for arranging externally received RGB image data according to the arrangement of subpixel columns commonly connected to each data line, providing the arranged RGB image data to the data driver 4, generating a gate control signal GCS and a data control signal DCS, and controlling the gate driver 6 and the data driver 4 with the gate control signal GCS and the data control signal DCS].
As to claim 7, (Currently Amended) Moon, as modified by Zhou, discloses the display device according to claim [[2]] 1, further comprising:
a timing controller [Moon, figure 1, timing controller 8 to output a control signal that controls the data drive IC 4 and the gate drive IC 6] configured to output a control signal that controls the data drive IC and the gate drive IC.
As to claim 8, (Original) Moon, as modified by Zhou, discloses the display device according to claim 7, wherein the timing controller outputs a first multiplexer signal that turns on and off the first multiplexer and a second multiplexer signal that turns on and off the second multiplexer, and performs a control operation such that the first multiplexer and the second multiplexer are alternately turned on [Zhou, figures 5-6, a first multiplexer signal SW1 that turns on and off the first multiplexer and a second multiplexer signal SW2 that turns on and off the second multiplexer, and performs a control operation such that the first multiplexer and the second multiplexer are alternately turned on as shown in figure 6]. In addition, the same rationale is used as in rejection for claim 1.
As to claim 14, (New) Moon, as modified by Zhou, discloses the display device according to claim 1, wherein:
a first color subpixel in the first pixel unit is connected to the odd gate line [Moon, figure 1, a first color subpixel R in the first pixel unit (first column of RGB) is connected to odd line GL1], and
a first color subpixel in the second pixel unit is connected to the even gate line [Moon, figure 1, a first color subpixel R in the second pixel unit (third column of RGB) is connected to odd line GL2].
Allowable Subject Matter
Claims 9-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, made of record, singularly or in combination, teaches or fairly suggests the features presented in the combination limitations of dependent claims 9-11, such as “a first switching transistor configured to store the data voltage in the storage capacitor
in response to an Nth scan signal; a second switching transistor configured to connect the driving transistor such that the driving transistor is in a diode-connected state in response to the Nth scan signal; a light emitting transistor configured to connect the driving transistor to the light emitting element in response to an emission signal; a first initialization transistor configured to initialize an anode of the light emitting element to a reference voltage in response to an (N-1)th scan signal; and a second initialization transistor configured to initialize a gate electrode of the driving transistor to the reference voltage in response to the (N-1)th scan signal”, recited by claim 9; “a first switching transistor having a first electrode connected to a data line from the data lines and a second electrode connected to a second capacitor electrode of the storage capacitor in response to an Nth scan signal; a second switching transistor configured to interconnect a gate electrode of the driving transistor and a second electrode of the driving transistor such that the driving transistor is in a diode-connected state in response to the Nth scan signal; a third switching transistor configured to connect a reference voltage to the second capacitor electrode of the storage capacitor in response to an emission signal; a fourth switching transistor configured to connect the driving transistor to the light emitting element in response to the emission signal; a fifth switching transistor configured to connect the reference voltage to an anode of the light emitting element in response to an (N-1)th scan signal; and a sixth switching transistor configured to connect the reference voltage to the gate electrode of the driving transistor in response to the (N-1)th scan signal”, recited by claim 10; and “wherein the first gate drive IC sequentially applies an odd scan signal corresponding to an on level for 1/3 of a horizontal period through the odd gate line, and the second gate drive IC sequentially applies an even scan signal corresponding to the on level for 1/3 of the horizontal period through the even gate line”, recited by claim 11.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAN-YING YANG whose telephone number is (571)272-2211. The examiner can normally be reached Monday-Friday, 8am-5pm, EST.
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/NAN-YING YANG/Primary Examiner, Art Unit 2629
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