DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the Applicant’s communication filed on July 28, 2025. In virtue of this communication, claims 1-20 are currently presented in the instant application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/28/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-2, 12, 14 and 17-18 are objected to because of the following informalities:
Claim 1, in line 13, --the-- should be inserted between “in” and “DCM,”
Claim 2, in line 5, --the-- should be inserted between “in” and “DCM,”
Claim 12, in line 7, --the-- should be inserted between “in” and “DCM,”
Claim 14, in line 1, --the-- should be inserted between “in” and “DCM,”
Claim 17, in line 19, --the-- should be inserted between “in” and “DCM:”
Claim 18, in line 1, --the-- should be inserted between “in” and “DCM,”
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,376,211.
Although the claims at issue are not identical, they are not patentably distinct from each other because the above indicated claims of the instant application are either anticipated by, or would have been obvious over, the above identified claims of the above patent, including:
As claim 1: A circuit comprising: first, second, third, and fourth transistors coupled in series; and a control circuit coupled to the first, second, third, and fourth transistors, the control circuit including a clock generator, a current sense circuit, and a zero current differentiation zone (ZC_DF) circuit, in which: the clock generator is configured to generate first and second clocks, in which the second clock is in quadrature with the first clock; the current sense circuit is configured to sense a current flowing through the first transistor; the ZC_DF circuit is configured to define a ZC_DF interval starting at an edge of the second clock and ending at turn-on of the fourth transistor; and the control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and, in DCM, turn off the first transistor during the ZC_DF interval responsive to the current flowing through the first transistor being negative (see claim 1 of the above patent).
As claim 2: The circuit of claim 1, wherein: the current sense circuit is a first current sense circuit; the control circuit include a second current sense circuit configured to detect a current flowing through the fourth transistor; and the control circuit is configured to, in DCM, turn off the second transistor during the ZC_DF interval responsive to the current flowing through the fourth transistor being negative (see claim 2 of the above patent).
As claim 3: The circuit of claim 2, wherein the control circuit is configured to, in DCM, turn off the second transistor, not in the ZC_DF interval, responsive to the current flowing through the first transistor being negative (see claim 3 of the above patent).
As claim 4: The circuit of claim 2, wherein: the first current sense circuit is configured to generate a first sense signal representing the current flowing through the first transistor; the second current sense circuit is configured to generate a second sense signal representing the current flowing through the fourth transistor; and the control circuit is configured to turn off the second transistor responsive to the first sense signal being less than the second clock, or the second sense signal being less than the second clock (see claim 4 of the above patent).
As claim 5: The circuit of claim 1, wherein: the current sense circuit is configured to generate a sense signal representing the current flowing through the first transistor; and the control circuit is configured to turn off the first transistor responsive to the sense signal being less than the first clock (see claim 5 of the above patent).
As claim 6: The circuit of claim 1, wherein the control circuit is configured to: operate the first, second, third, and fourth transistors in a pulse frequency modulation (PFM) mode; define a pre-PFM zone based on the current flowing through the fourth transistor being zero at an edge of the second clock; and in the pre-PFM zone: disable turn-on of the fourth transistor; and exit the pre-PFM zone responsive to the current flowing through the fourth transistor not being zero at an edge of the second clock (see claim 6 of the above patent).
As claim 7: The circuit of claim 6, wherein the control circuit is configured to: define the pre-PFM zone based on the current flowing through the fourth transistor being zero at an edge of the first clock; in the pre-PFM zone: disable turn-on of the third transistor; and exit the pre-PFM zone responsive to the current flowing through the fourth transistor not being zero at an edge of the first clock (see claim 7 of the above patent).
As claim 8: The circuit of claim 6, wherein the control circuit is configured to: in the pre-PFM zone: disable turn-on of the first transistor and the second transistor based on turn-on of the third and fourth transistors being disabled (see claim 8 of the claim patent).
As claim 9: A circuit comprising: first, second, third, and fourth transistors coupled in series; and a control circuit coupled to the first, second, third, and fourth transistor, the control circuit including a clock generator, a first current sense circuit, and a second current sense circuit, in which: the clock generator is configured to generate first and second clocks, in which the second clock is in quadrature with the first clock; the first current sense circuit is configured to sense a current flowing through the first transistor; the second current sense circuit is configured to sense a current flowing through the fourth transistor; and the control circuit is configured to: operate the first, second, third, and fourth transistors in a pulse frequency modulation (PFM) mode; define a pre-PFM zone based on the current flowing through the fourth transistor being zero at an edge of the second clock; and in the pre-PFM zone: disable turn-on of the fourth transistor; and exit the pre-PFM zone responsive to the current flowing through the fourth transistor not being zero at an edge of the second clock (see claim 9 of the above patent).
As claim 10: The circuit of claim 9, wherein the control circuit is configured to: define the pre-PFM zone based on the current flowing through the fourth transistor being zero at an edge of the first clock; in the pre-PFM zone: disable turn-on of the third transistor; and exit the pre-PFM zone responsive to the current flowing through the fourth transistor not being zero at an edge of the first clock (see claim 10 of the above patent).
As claim 11: The circuit of claim 9, wherein the control circuit is configured to: in the pre-PFM zone: disable turn-on of the first transistor and the second transistor based on turn-on of the third and fourth transistors being disabled (see claim 11 of the above patent).
As claim 12: The circuit of claim 9, wherein: the control circuit includes: a zero current differentiation zone (ZC_DF) circuit configured to define a ZC_DF interval starting at an edge of the second clock and ending at turn-on of the fourth transistor; and the control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and, in DCM, turn off the first transistor during the ZC_DF interval responsive to the current flowing through the first transistor being negative (see claim 12 of the above patent).
As claim 13: The circuit of claim 12, wherein the control circuit is configured to, in DCM, turn off the second transistor during the ZC_DF interval responsive to the current flowing through the fourth transistor being negative (see claim 13 of the above patent).
As claim 14: The circuit of claim 13, wherein the control circuit is configured to, in DCM, turn off the second transistor, not in the ZC_DF interval, responsive to the current flowing through the first transistor being negative (see claim 14 of the above patent).
As claim 15: The circuit of claim 13, wherein: the first current sense circuit is configured to generate a first sense signal representing the current flowing through the first transistor; the second current sense circuit is configured to generate a second sense signal representing the current flowing through the fourth transistor; and the control circuit is configured to turn off the second transistor responsive to the first sense signal being less than the second clock, or the second sense signal being less than the second clock (see claim 15 of the above patent).
As claim 16: The circuit of claim 13, wherein: The first current sense circuit is configured to generate a sense signal representing the current flowing through the first transistor; and the control circuit is configured to turn off the first transistor responsive to the sense signal being less than the first clock (see claim 16 of the above patent).
As claim 17: A backlight system comprising: a light emitting diode (LED); and a three-level switching converter coupled to the LED, the three-level switching converter including: first, second, third, and fourth transistors coupled in series; and a control circuit coupled to the first, second, third, and fourth transistors, the control circuit including a clock generator, a first current sense circuit, a second current sense circuit, and a zero current differentiation zone (ZC_DF) circuit, in which: the clock generator is configured to generate first and second clocks, in which the second clock is in quadrature with the first clock; the first current sense circuit is configured to sense a current flowing through the first transistor; the ZC_DF circuit is configured to define a ZC_DF interval starting at an edge of the second clock and ending at turn-on of the fourth transistor; and the control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and, in DCM: turn off the first transistor during the ZC_DF interval responsive to the current flowing through the first transistor being negative; and turn off the second transistor during the ZC_DF interval responsive to the current flowing through the fourth transistor being negative (see claim 17 of the above patent 17).
As claim 18: The backlight system of claim 17, wherein the control circuit is configured to, in DCM, turn off the second transistor, not in the ZC_DF interval, responsive to the current flowing through the first transistor being negative (see claim 18 of the above patent).
As claim 19: The backlight system of claim 17, wherein: the first current sense circuit is configured to generate a first sense signal representing the current flowing through the first transistor; the second current sense circuit is configured to generate a second sense signal representing the current flowing through the fourth transistor; the control circuit is configured to: turn off the second transistor responsive to the first sense signal being less than the second clock, or the second sense signal being less than the second clock; and turn off the first transistor responsive to the first sense signal being less than the first clock (see claim 19 of the above patent).
As claim 20: The backlight system of claim 17, wherein the control circuit is configured to: operate the first, second, third, and fourth transistors in a pulse frequency modulation (PFM) mode; define a pre-PFM zone based on the current flowing through the fourth transistor being zero at an edge of the second clock or the current flowing through the fourth transistor being zero at an edge of the first clock; and in the pre-PFM zone: disable turn-on of the fourth transistor; responsive to initiation of the pre-PFM zone at the current flowing through the fourth transistor being zero at an edge of the second clock, exit the pre-PFM zone responsive to the current flowing through the fourth transistor not being zero at an edge of the second clock; disable turn-on of the third transistor; responsive to initiation of the pre-PFM zone at the current flowing through the fourth transistor being zero at an edge of the first clock, exit the pre- PFM zone responsive to the current flowing through the fourth transistor not being zero at an edge of the first clock; and disable turn-on of the first transistor and the second transistor based on turn- on of the third and fourth transistors being disabled (see claim 20 of the above patent).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Prior art Szczeszynski – US 2023/0136027
Prior art Liu et al. – US 2018/0026518
Prior art Modepalli et al. – US 2017/0245339
Prior art Sanders et al. – US 2014/0346962
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/TUNG X LE/Primary Examiner, Art Unit 2845 August 10, 2026
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