DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 06/18/2026 has been considered by Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10-11, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al (US 2020/0105843 A1) in view of Rhe et al (US 2023/0006183 A1).
Claim 1, Baek (Fig. 1-18) discloses a display panel (10; Fig. 1; wherein discloses a display panel) comprising:
a first pixel circuit (PX_R; Fig. 12; wherein discloses a red pixel circuit), a second pixel circuit (PX_G; Fig. 12; wherein discloses a green pixel circuit), and a third pixel circuit (PX_B; Fig. 12; wherein discloses a blue pixel circuit) each including a driving transistor (TR1; Fig. 5) and a capacitor (Cst; Fig. 5) on a substrate (100; Fig. 6A or 6B; wherein discloses a substrate), and arranged along a first direction (D1; Fig. 12);
a first light-emitting element (OLED; Fig. 5; PX_R; Fig. 12), a second light-emitting element (OLED; Fig. 5; PX_G; Fig. 12), and a third light-emitting element (OLED; Fig. 5; PX_B; Fig. 12), electrically connected to the first pixel circuit (Fig. 5; PX_R; Fig. 12), the second pixel circuit (Fig. 5; PX_G; Fig. 12), and the third pixel circuit (Fig. 5; PX_B; Fig. 12), respectively (Fig. 12; wherein figure shows respective color pixels); and
a pixel defining layer (126; Fig. 6B; wherein discloses a pixel definition film 126) including a first pixel opening (TA) defining a first light-emitting area of the first light-emitting element (OLED; Fig. 5; PX_R; and Fig. 12; EMA; Fig. 6B; EMA_R; Fig. 13 and 14), a second pixel opening (TA) defining a second light-emitting area of the second light-emitting element (OLED; Fig. 5; PX_G; Fig. 12; EMA; Fig. 6B; EMA_G; Fig. 13 and 14), a third pixel opening defining a third light-emitting area of the third light-emitting element (OLED; Fig. 5; PX_B; Fig. 12; EMA; Fig. 6B; EMA_B; Fig. 13 and 14), and an opening defining a hole area (TA and OP; Fig. 6B; wherein discloses a light transmission region, [0071]),
wherein, in a plan view (Fig. 12; wherein figure shows a plan view), the first light-emitting area (PX_R; Fig. 12) and the second light-emitting area (PX_G; Fig. 12) are arranged along a second direction (D2; Fig. 12) perpendicular to the first direction (D1; Fig. 12), and the third light-emitting area (PX_B; Fig. 12) is arranged along the first direction (D1; Fig. 12) from each of the first light-emitting area (PX_R; Fig. 12) and the second light-emitting area (PX_G; Fig. 12),
wherein, in the plan view (Fig. 12; wherein figure shows a plan view), the hole area (TA; Fig. 12; TA and OP; Fig. 6B) is spaced apart from circuit elements (PX; Fig. 6B; Fig. 5) constituting the first pixel circuit (PX_R; Fig. 12), wires electrically connected to the first pixel circuit (SL_R; Fig. 17; ELVDDL_RB and DL_RB; Fig. 18), circuit elements (PX; Fig. 6B; Fig. 5) constituting the second pixel circuit (PX_G; Fig. 12), wires electrically connected to the second pixel circuit (SL_G; Fig. 17; ELVDDL_G and DL_G; Fig. 18), circuit elements (PX; Fig. 6B; Fig. 5) constituting the third pixel circuit (PX_B; Fig. 12), and wires electrically connected to the third pixel circuit (SL_B; Fig. 17; ELVDDL_RB and DL_RB; Fig. 18), and
wherein, in the plan view (Fig. 12; wherein figure shows a plan view), a center of the hole area (TA; Fig. 12; wherein the lettering TA is shown in be at the approximate center of the light transmission region TA; Paragraph [0030]; wherein discloses “the respective color pixels PX of the second display region DPA_T are not adjacent to each other and are distributed so as to be spaced apart from each other with a light transmission region TA therebetween”) is located within an imaginary triangle (See Baek’s Figure 12 below as compared to Applicant’s figure 6) defined by connecting a center of the first light-emitting area (PX_R; Fig. 12), a center of the second light-emitting area (PX_G; Fig. 12), and a center of the third light-emitting area (PX_B; Fig. 12).
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Baek does not expressly disclose wherein, in the plan view, the hole area has a closed curve shape.
Rhe (Fig. 1-12) discloses wherein, in the plan view (Fig. 7; wherein figure shows a plan view of area AA2 in from figure 3), the hole area (H; Fig. 7; wherein the figure shows a hole arranged between red subpixel SP_R, green subpixel SP_G, and blue subpixel SP_B) has a closed curve shape (Fig. 7; wherein figure shows a hole H with a closed curve shape).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek’s display panel by applying a hole shape, as taught by Rhe, so to use a display panel with a hole shape for provide a display device capable of improving a detecting performance of a sensor which is disposed on an area overlapping an area displaying an image and detecting an object positioned in front of a display panel (Paragraph [0007]).
Claim 11, Baek (Fig. 1-18) discloses a display panel (10; Fig. 1; wherein discloses a display panel) comprising:
a first pixel circuit (PX_R; Fig. 12; wherein discloses a red pixel circuit), a second pixel circuit (PX_G; Fig. 12; wherein discloses a green pixel circuit), and a third pixel circuit (PX_B; Fig. 12; wherein discloses a blue pixel circuit) each including a first transistor (TR1; Fig. 5) and a second transistor (TR2; Fig. 5) on a substrate (100; Fig. 6A and 6B) and being adjacent along a first direction (D1; Fig. 12);
a first light-emitting element (OLED; Fig. 5; PX_R; Fig. 12), a second light-emitting element (OLED; Fig. 5; PX_G; Fig. 12), and a third light-emitting element (OLED; Fig. 5; PX_B; Fig. 12), electrically connected to the first pixel circuit (Fig. 5; PX_R; Fig. 12), the second pixel circuit (Fig. 5; PX_G; Fig. 12), and the third pixel circuit (Fig. 5; PX_B; Fig. 12), respectively (Fig. 12; wherein figure shows respective color pixels); and
a pixel defining layer (126; Fig. 6B; wherein discloses a pixel definition film 126) including a first pixel opening defining a first light-emitting area of the first light-emitting element (OLED; Fig. 5; PX_R; Fig. 12; EMA; Fig. 6B; EMA_R; Fig. 13 and 14), a second pixel opening defining a second light-emitting area of the second light-emitting element (OLED; Fig. 5; PX_G; Fig. 12; EMA; Fig. 6B; EMA_G; Fig. 13 and 14), a third pixel opening defining a third light-emitting area of the third light-emitting element (OLED; Fig. 5; PX_B; Fig. 12; EMA; Fig. 6B; EMA_B; Fig. 13 and 14), and an opening defining a hole area (TA and OP; Fig. 6B; wherein discloses a light transmission region) located between (See Figure 12 above) the first light-emitting area (PX_R; Fig. 12), the second light-emitting area (PX_G; Fig. 12), and the third light-emitting area (PX_B; Fig. 12),
wherein, in a plan view (Fig. 12; wherein figure shows a plan view), the first light-emitting area (PX_R; Fig. 12) and the second light-emitting area (PX_G; Fig. 12) are arranged along a second direction (D2; Fig. 12) perpendicular to the first direction (D1; Fig. 12), and the third light-emitting area (PX_B; Fig. 12) is arranged along the first direction (D1; Fig. 12) from each of the first light-emitting area (PX_R; Fig. 12) and the second light-emitting area (PX_G; Fig. 12), and
wherein the first light-emitting area (PX_R; Fig. 12), the hole area (TA; Fig. 12), and the second light-emitting area (PX_G; Fig. 12) are staggered (See figure 12 below) along the second direction (D2; Fig. 12).
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Baek does not expressly disclose wherein, in the plan view, the hole area has a closed curve shape.
Rhe (Fig. 1-12) discloses wherein, in the plan view (Fig. 7; wherein figure shows a plan view of area AA2 in from figure 3), the hole area (H; Fig. 7; wherein the figure shows a hole arranged between red subpixel SP_R, green subpixel SP_G, and blue subpixel SP_B) has a closed curve shape (Fig. 7; wherein figure shows a hole H with a closed curve shape).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek’s display panel by applying a hole shape, as taught by Rhe, so to use a display panel with a hole shape for provide a display device capable of improving a detecting performance of a sensor which is disposed on an area overlapping an area displaying an image and detecting an object positioned in front of a display panel (Paragraph [0007]).
Claim 20, Baek (Fig. 1-18) discloses an electronic device (Paragraph [0040]; wherein discloses “an electronic device”) comprising:
a display panel (10; Fig. 1; wherein discloses a display panel); and
a component (20; Fig. 3; Paragraph [0053]; wherein discloses a light sensing member 20) on a lower surface of the display panel (10; Fig. 3),
wherein the display panel (10; Fig. 1) comprises:
a first pixel circuit (PX_R; Fig. 12; wherein discloses a red pixel circuit), a second pixel circuit (PX_G; Fig. 12; wherein discloses a green pixel circuit), and a third pixel circuit (PX_B; Fig. 12; wherein discloses a blue pixel circuit) each including a driving transistor (TR1; Fig. 5) and a capacitor (Cst; Fig. 5) on a substrate (100; Fig. 6A or 6B; wherein discloses a substrate), and arranged along a first direction (D1; Fig. 12);
a first light-emitting element (OLED; Fig. 5; PX_R; Fig. 12), a second light-emitting element (OLED; Fig. 5; PX_G; Fig. 12), and a third light-emitting element (OLED; Fig. 5; PX_B; Fig. 12), electrically connected to the first pixel circuit (Fig. 5; PX_R; Fig. 12), the second pixel circuit (Fig. 5; PX_G; Fig. 12), and the third pixel circuit (Fig. 5; PX_B; Fig. 12), respectively (Fig. 12; wherein figure shows respective color pixels); and
a pixel defining layer (126; Fig. 6B; wherein discloses a pixel definition film 126) including a first pixel opening defining a first light-emitting area of the first light-emitting element (OLED; Fig. 5; PX_R; Fig. 12; EMA; Fig. 6B; EMA_R; Fig. 13 and 14), a second pixel opening defining a second light-emitting area of the second light-emitting element (OLED; Fig. 5; PX_G; Fig. 12; EMA; Fig. 6B; EMA_G; Fig. 13 and 14), a third pixel opening defining a third light-emitting area of the third light-emitting element (OLED; Fig. 5; PX_B; Fig. 12; EMA; Fig. 6B; EMA_B; Fig. 13 and 14), and an opening defining a hole area (TA and OP; Fig. 6B; wherein discloses a light transmission region),
wherein, in a plan view (Fig. 12; wherein figure shows a plan view), the first light-emitting area (PX_R; Fig. 12) and the second light-emitting area (PX_G; Fig. 12) are arranged along a second direction (D2; Fig. 12) perpendicular to the first direction (D1; Fig. 12), and the third light-emitting area (PX_B; Fig. 12) is arranged along the first direction (D1; Fig. 12) from each of the first light-emitting area (PX_R; Fig. 12) and the second light-emitting area (PX_G; Fig. 12),
wherein, in the plan view (Fig. 12; wherein figure shows a plan view), the hole area (TA; Fig. 12; TA and OP; Fig. 6B) is spaced apart from circuit elements (PX; Fig. 6B; Fig. 5) constituting the first pixel circuit (PX_R; Fig. 12), wires electrically connected to the first pixel circuit (SL_R; Fig. 17; ELVDDL_RB and DL_RB; Fig. 18), circuit elements (PX; Fig. 6B; Fig. 5) constituting the second pixel circuit (PX_G; Fig. 12), wires electrically connected to the second pixel circuit (SL_G; Fig. 17; ELVDDL_G and DL_G; Fig. 18), circuit elements (PX; Fig. 6B; Fig. 5) constituting the third pixel circuit (PX_B; Fig. 12), and wires electrically connected to the third pixel circuit (SL_B; Fig. 17; ELVDDL_RB and DL_RB; Fig. 18),
wherein, in the plan view (Fig. 12; wherein figure shows a plan view), a center of the hole area (TA; Fig. 12; wherein the lettering TA is shown in be at the approximate center of the light transmission region TA; Paragraph [0030]; wherein discloses “the respective color pixels PX of the second display region DPA_T are not adjacent to each other and are distributed so as to be spaced apart from each other with a light transmission region TA therebetween”) is located within an imaginary triangle (See Baek’s Figure 12 above as compared to Applicant’s figure 6) defined by connecting a center of the first light-emitting area (PX_R; Fig. 12), a center of the second light-emitting area (PX_G; Fig. 12), and a center of the third light-emitting area (PX_B; Fig. 12), and
wherein the component (20; Fig. 2; Paragraph [0053]; wherein discloses “the display device 1 may include a light sensing member 20 below the second display region DPA_T of the display panel 10”) overlaps the hole area (TA within area DPA_T; Fig. 12).
Baek does not expressly disclose wherein, in the plan view, the hole area has a closed curve shape.
Rhe (Fig. 1-12) discloses wherein, in the plan view (Fig. 7; wherein figure shows a plan view of area AA2 in from figure 3), the hole area (H; Fig. 7; wherein the figure shows a hole arranged between red subpixel SP_R, green subpixel SP_G, and blue subpixel SP_B) has a closed curve shape (Fig. 7; wherein figure shows a hole H with a closed curve shape).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek’s display panel by applying a hole shape, as taught by Rhe, so to use a display panel with a hole shape for provide a display device capable of improving a detecting performance of a sensor which is disposed on an area overlapping an area displaying an image and detecting an object positioned in front of a display panel (Paragraph [0007]).
Claims 10 and 19, Baek (Fig. 1-18) discloses wherein
each of the first light-emitting element (PX_R; Fig. 12; PX; Fig. 6A), the second light-emitting element (PX_G; Fig. 12; PX; Fig. 6A), and the third light-emitting element (PX_B; Fig. 12; PX; Fig. 6A) comprises:
a pixel electrode (170; Fig. 6A and 6B; Paragraph [0088]);
an emission layer (190; Fig. 6A and 6B) on the pixel electrode (170; Fig. 6A and 6B); and
a counter electrode (180; Fig. 6A and 6B; Paragraph [0092]; wherein discloses a common electrode) on the emission layer (190; Fig. 6A and 6B),
wherein the counter electrode (180; Fig. 6A and 6B; Paragraph [0092]) is integrally (Paragraph [0092]; wherein discloses “The cathode may be located not only in the emission region EMA of the pixel PX but also in the non-emission region NEA. That is, the cathode may be on an entire surface of each pixel PX”) provided corresponding to the first light-emitting element (PX_R; Fig. 12), the second light-emitting element (PX_G; Fig. 12), and the third light-emitting element (PX_B; Fig. 12) and includes an opening (OP; Fig. 6A) corresponding to the hole area (TA; Fig. 6A).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Baek et al (US 2020/0105843 A1) in view of Rhe et al (US 2023/0006183 A1) as applied to claim 1 above, and further in view of Lee et al (US 2022/0181354 A1) and Lee et al (US 2023/0143745 A1).
Claim 2, Baek in view of Rhe discloses the display panel of claim 1.
Baek in view of Rhe does not expressly disclose further comprising
a blocking metal layer between an upper surface of the substrate and the driving transistor of the first pixel circuit, between the upper surface of the substrate and the driving transistor of the second pixel circuit, and between the upper surface of the substrate and the driving transistor of the third pixel circuit,
wherein the blocking metal layer comprises:
a first blocking metal portion including a first main portion overlapping a channel region of the driving transistor of the first pixel circuit and a first branch portion connected to the first main portion and extending in a third direction opposite to the second direction from the first main portion;
a second blocking metal portion including a second main portion overlapping a channel region of the driving transistor of the second pixel circuit and a second branch portion connected to the second main portion and extending in the third direction from the second main portion; and
a third blocking metal portion including a third main portion overlapping a channel region of the driving transistor of the third pixel circuit and a third branch portion connected to the third main portion and extending in the third direction from the third main portion,
wherein a length of the third branch portion along the third direction is less than a length of the first branch portion along the third direction and a length of the second branch portion along the third direction.
Lee (Fig. 1-17) discloses further comprising
a blocking metal layer (BML; Fig. 14; wherein discloses a shield layer; Paragraph [0009]; wherein discloses “the shield layer may include a metal material”) between (BML; Fig. 6) an upper surface of the substrate (100; Fig. 6) and the driving transistor (T1; Fig. 6 and 2) of the first pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit), between (BML; Fig. 6) the upper surface of the substrate (100; Fig. 6) and the driving transistor (T1; Fig. 6 and 2) of the second pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit), and between (BML; Fig. 6) the upper surface of the substrate (100; Fig. 6) and the driving transistor (T1; Fig. 6 and 2) of the third pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit),
wherein the blocking metal layer (BML; Fig. 14) comprises:
a first blocking metal portion (BMLP; Fig. 14) including a first main portion (BMLP; Fig. 6) overlapping a channel region (AS1; Fig. 6) of the driving transistor (T1; Fig. 6) of the first pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit) and a first branch portion (BMLC1; Fig. 14) connected to the first main portion (BMLP; Fig. 14) and extending in a third direction (Fig. 14; wherein figure shows for the first pixel in the row a first connection line BMLC1 extending vertically upward from the main body BMLP of the first pixel in the row) opposite to the second direction (Fig. 14; wherein the second direction is vertically downward) from the first main portion (BMLP; Fig. 14);
a second blocking metal portion (BMLP; Fig. 14) including a second main portion (BMLP; Fig. 6) overlapping a channel region (AS1; Fig. 6) of the driving transistor (T1; Fig. 6) of the second pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit) and a second branch portion (BMLC1; Fig. 14) connected to the second main portion (BMLP; Fig. 14) and extending in the third direction (Fig. 14; wherein figure shows for the third pixel in the row a first connection line BMLC1 extending vertically upward from the main body BMLP of the third pixel in the row) from the second main portion (BMLP; Fig. 14); and
a third blocking metal portion (BMLP; Fig. 14) including a third main portion (BMLP; Fig. 6) overlapping a channel region (AS1; Fig. 6) of the driving transistor (T1; Fig. 6) of the third pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit) and a third branch portion (Fig. 14; wherein figure a removed connection line) connected to the third main portion (BMLP; Fig. 14) and extending in the third direction (Fig. 14; wherein figure shows for the second pixel in the row a removed connection line not extending vertically upward from the main body BMLP of the second pixel in the row) from the third main portion (BMLP; Fig. 14),
wherein a length of the third branch portion (Fig. 14; wherein figure shows for the second pixel in the row a removed connection line not extending vertically upward from the main body BMLP of the second pixel in the row) along the third direction is less than a length of the first branch portion along the third direction (Fig. 14; wherein figure shows for the first pixel in the row a first connection line BMLC1 extending vertically upward from the main body BMLP of the first pixel in the row) and a length of the second branch portion along the third direction (Fig. 14; wherein figure shows for the third pixel in the row a first connection line BMLC1 extending vertically upward from the main body BMLP of the third pixel in the row).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Baek in view of Rhe and Lee does not expressly disclose wherein a distance between the third branch portion and the hole area is less than a distance between the first branch portion and the hole area and a distance between the second branch portion and the hole area.
Lee (Fig. 1-35) discloses wherein a distance between the third branch portion (BML; Fig. 7) and the hole area (OPS; Fig. 17) is less than a distance between the first branch portion (Fig. 7; wherein figure shows another BML area for the adjacent subpixel) and the hole area (OPS; Fig. 17) and a distance between the second branch portion (Fig. 7; wherein figure shows another BML area for the adjacent subpixel; wherein BML area is from the red subpixel different then the green and blue subpixel) and the hole area (OPS; Fig. 19).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe and Lee’s display panel by applying a hole area, as taught by Lee, so to use a display panel with a hole area for improving display quality by reducing a reflective color band generated while being asymmetrically reflected due to reflection of external light (Paragraph [0007]).
Claims 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al (US 2020/0105843 A1) in view of Rhe et al (US 2023/0006183 A1), Lee et al (US 2022/0181354 A1), and Lee et al (US 2023/0143745 A1) as applied to claim 2 above, and further in view of Bang et al (US 2021/0183983 A1).
Claim 3, Lee (Fig. 1-17) (US 2022/0181354 A1) discloses further comprising a first initialization control line (SL3; Fig. 2, 5, 7F) extending in the first direction (X; Fig. 5 and 7F),
wherein, in the plan view (Fig. 5 and 15), the first initialization control line (SL3; Fig. 5 and 15) intersects the first branch portion (BMC1; Fig. 7A) and the second branch portion (BMC1; Fig. 7A) and is spaced apart from the third branch portion (Fig. 16; wherein figure shows BMC1 is removed and therefore space apart from the branch portion).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Baek in view of Rhe, Lee, and Lee does not expressly disclose wherein, in the plan view, the first initialization control line is spaced apart from the hole area.
Bang (Fig. 1-25) discloses wherein, in the plan view (Fig. 12), the first initialization control line (SL2; Fig. 4B; 12) is spaced apart from the hole area (TA; Fig. 11A-12).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe, Lee, and Lee’s display panel by applying an initialization control line, as taught by Bang, so to use a display panel with an initialization control line for providing the arrangement and number of lines arranged or disposed in a second display area may be different from the arrangement and number of lines arranged or disposed in a first display area, and thus, a transmissive area may be increased or maximized and a lifespan of a panel may be increased (Paragraph [0239]).
Claim 4, Lee (Fig. 1-17) (US 2022/0181354 A1) discloses wherein
each of the first pixel circuit (CA1; Fig. 5), the second pixel circuit (CA2; Fig. 5), and the third pixel circuit (CA1; Fig. 11) further comprises a first initialization transistor (T4; Fig. 2, 5, and 11) including a first initialization semiconductor layer (A4; Fig. 7E) and a first initialization gate electrode (G4a; Fig. 7D), and
the first initialization control line (143; Fig. 7D) includes the first initialization gate electrode (G4a; Fig. 7D) of each of the first pixel circuit (CA1; Fig. 5), the second pixel circuit (CA2; Fig. 5), and the third pixel circuit (CA1; Fig. 11).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Claim 5, Lee (Fig. 1-17) (US 2022/0181354 A1) discloses wherein the first initialization semiconductor layer (A4; Fig. 7E) of the first initialization transistor (T4; Fig. 2) is on a different layer (Fig. 6; wherein figure shows transistor T4 on a different layer than transistor T1) from a driving semiconductor layer (A1; Fig. 7B) of the driving transistor (T1; Fig. 2) of each of the first pixel circuit (CA1; Fig. 5), the second pixel circuit (CA2; Fig. 5), and the third pixel circuit (CA1; Fig. 11).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Claim 6, Lee (Fig. 1-17) (US 2022/0181354 A1) discloses further comprising a first initialization voltage line (VIL1; Fig. 2 and 7D) extending in the first direction (X; Fig. 7D) and electrically connected to the first initialization semiconductor layer (S4; Fig. 7E) of the first initialization transistor (T4; Fig. 2) of each of the first pixel circuit (CA1; Fig. 5), the second pixel circuit (CA2; Fig. 5), and the third pixel circuit (CA1; Fig. 11).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Claim 7, Lee (Fig. 1-17) (US 2022/0181354 A1) discloses wherein
the first initialization voltage line (VIL1; Fig. 2) includes a first portion (147(VIL1); Fig. 7D), the first portion (147(VIL1); Fig. 7D) intersecting the first branch portion (BMLC1 for first pixel; Fig. 7A) and the second branch portion (BMLC1 for second pixel; Fig. 7A) in the plan view (Fig. 5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Bang (Fig. 1-25) discloses the first initialization voltage line (VIL; Fig. 4B) includes a first portion (Fig. 12; wherein figure shows a first portion which interconnects the pixel circuits) and a second portion (VIL; Fig. 12; wherein figure shows a second portion which is connected to the first portion through a via hole and is angled to bend around TA areas), the second portion (VIL: Fig. 12) being adjacent to the hole area (TA; Fig. 11A-12) in the plan view (Fig. 12), and
at least a part of the second portion (VIL; Fig. 12; wherein figure shows a second portion which is connected to the first portion through a via hole and is angled to bend around TA areas) of the first initialization voltage line (VIL; Fig. 12) is curved along a perimeter of the hole area (TA; Fig. 11A-12) in the plan view (Fig. 12).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe, Lee, and Lee’s display panel by applying an initialization control line, as taught by Bang, so to use a display panel with an initialization control line for providing the arrangement and number of lines arranged or disposed in a second display area may be different from the arrangement and number of lines arranged or disposed in a first display area, and thus, a transmissive area may be increased or maximized and a lifespan of a panel may be increased (Paragraph [0239]).
Claim 8, Lee (Fig. 1-17) (US 2022/0181354 A1) discloses wherein the first portion (147(VIL1); Fig. 7D) extends in a straight line along the first direction (X; Fig. 7D) in the plan view (Fig. 5 and 7D).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al (US 2020/0105843 A1) in view of Rhe et al (US 2023/0006183 A1) as applied to claim 1 above, and further in view of Sung et al (US 2022/0359851 A1).
Claims 9 and 18, Baek in view of Rhe discloses the display panel of claims 1 and 18.
Baek in view of Rhe does not expressly disclose wherein the pixel defining layer includes a light-blocking insulating layer.
Sung (Fig. 1-17) discloses wherein the pixel defining layer (180; Fig. 4) includes a light-blocking insulating layer (Paragraph [0099]; wherein discloses “In other embodiments, the pixel-defining layer 180 may include an organic insulating material and an inorganic insulating material. In an embodiment, the pixel-defining layer 180 may include a light-blocking material, and may be black.”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a pixel defining layer, as taught by Sung, so to use a display panel with a pixel defining layer for providing a display apparatus including a light-emitting device having an improved life and a method of manufacturing the display apparatus may be provided (Paragraph [0164]).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al (US 2020/0105843 A1) in view of Rhe et al (US 2023/0006183 A1) as applied to claim 11 above, and further in view of Lee et al (US 2022/0181354 A1) and Bang et al (US 2021/0183983 A1).
Claim 12, Baek in view of Rhe discloses the display panel of claim 11.
Baek in view of Rhe does not expressly disclose further comprising
a first initialization voltage line extending in the first direction and electrically connected to the second transistor of each of the first pixel circuit, the second pixel circuit, and the third pixel circuit,
wherein the first initialization voltage line includes a first portion, the first portion extending in a straight line along the first direction in the plan view.
Lee (Fig. 1-17) discloses further comprising
a first initialization voltage line (VIL1; Fig. 2) extending in the first direction (X; Fig. 7D) and electrically connected to the second transistor (T4; Fig. 2) of each of the first pixel circuit (CA1; Fig. 5), the second pixel circuit (CA2; Fig. 5), and the third pixel circuit (CA1; Fig. 15),
wherein the first initialization voltage line (147(VAL1); Fig. 7A) includes a first portion (147(VAL1); Fig. 7A), the first portion (147(VAL1); Fig. 7A) extending in a straight line (147(VAL1); Fig. 7A) along the first direction (X; Fig. 7D) in the plan view (Fig. 5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Baek in view of Rhe and Lee does not expressly disclose further comprising
wherein the first initialization voltage line includes a first portion and a second portion, the second portion being at least partially curved along a perimeter of the hole area and spaced apart from the hole area in the plan view.
Bang (Fig. 1-25) discloses further comprising
wherein the first initialization voltage line (VIL; Fig. 4B) includes a first portion (Fig. 12; wherein figure shows a first portion which interconnects the pixel circuits) and a second portion (VIL; Fig. 12; wherein figure shows a second portion which is connected to the first portion through a via hole and is angled to bend around TA areas), the second portion (VIL: Fig. 12) being at least partially curved along a perimeter of the hole area (TA; Fig. 11A-12) and spaced apart from the hole area (TA; Fig. 11A-12) in the plan view (Fig. 12).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe and Lee’s display panel by applying an initialization control line, as taught by Bang, so to use a display panel with an initialization control line for providing the arrangement and number of lines arranged or disposed in a second display area may be different from the arrangement and number of lines arranged or disposed in a first display area, and thus, a transmissive area may be increased or maximized and a lifespan of a panel may be increased (Paragraph [0239]).
Claim 13, Lee (Fig. 1-17) discloses wherein
the first transistor (T1; Fig. 2) includes a first semiconductor layer (A1; Fig. 7B) and a first gate electrode (G1; Fig. 7C) on the first semiconductor layer (Fig. 7B),
the second transistor (T4; Fig. 2) includes a second semiconductor layer (A4; Fig. 7E) on the first gate electrode (Fig. 7B) and a second gate electrode (G4b; Fig. 7F) on the second semiconductor layer (Fig. 7E), and
the first initialization voltage line (147(VIL1); Fig. 7D) is electrically connected to the second semiconductor layer (S4; Fig. 73) of the second transistor (T4; Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe and Lee’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Claim 14, Lee (Fig. 1-17) discloses further comprising
a blocking metal layer (BML; Fig. 14; wherein discloses a shield layer; Paragraph [0009]; wherein discloses “the shield layer may include a metal material”) between (BML; Fig. 6) an upper surface of the substrate (100; Fig. 6) and the first transistor (T1; Fig. 6 and 2) of the first pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit), between (BML; Fig. 6) the upper surface of the substrate (100; Fig. 6) and the first transistor (T1; Fig. 6 and 2) of the second pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit), and between (BML; Fig. 6) the upper surface of the substrate (100; Fig. 6) and the first transistor (T1; Fig. 6 and 2) of the third pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit),
wherein, in the plan view (Fig. 15), the first portion of the first initialization voltage line (147(VIL1); Fig. 15) intersects a part of the blocking metal layer (BMLC1; Fig. 15 and 16), and the second portion of the first initialization voltage line (147(VIL1); Fig. 15) is spaced apart from the blocking metal layer (Fig. 16; wherein figure shows BMLC1 is not part of the first pixel circuit therefore reading on the limitation of being space apart from).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe and Lee’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al (US 2020/0105843 A1) in view of Rhe et al (US 2023/0006183 A1), and Lee et al (US 2022/0181354 A1), and Bang et al (US 2021/0183983 A1) as applied to claim 14 above, and further in view of Lee et al (US 2023/0143745 A1).
Claim 15, Lee (Fig. 1-17) (US 2022/0181354 A1) discloses wherein the blocking metal layer (BML; Fig. 14) comprises:
a first blocking metal portion (BMLP; Fig. 14) including a first main portion (BMLP; Fig. 6) overlapping a channel region (AS1; Fig. 6) of the driving transistor (T1; Fig. 6) of the first pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit) and a first branch portion (BMLC1; Fig. 14) connected to the first main portion (BMLP; Fig. 14) and extending in a third direction (Fig. 14; wherein figure shows for the first pixel in the row a first connection line BMLC1 extending vertically upward from the main body BMLP of the first pixel in the row) opposite to the second direction (Fig. 14; wherein the second direction is vertically downward) from the first main portion (BMLP; Fig. 14);
a second blocking metal portion (BMLP; Fig. 14) including a second main portion (BMLP; Fig. 6) overlapping a channel region (AS1; Fig. 6) of the driving transistor (T1; Fig. 6) of the second pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit) and a second branch portion (BMLC1; Fig. 14) connected to the second main portion (BMLP; Fig. 14) and extending in the third direction (Fig. 14; wherein figure shows for the third pixel in the row a first connection line BMLC1 extending vertically upward from the main body BMLP of the third pixel in the row) from the second main portion (BMLP; Fig. 14); and
a third blocking metal portion (BMLP; Fig. 14) including a third main portion (BMLP; Fig. 6) overlapping a channel region (AS1; Fig. 6) of the driving transistor (T1; Fig. 6) of the third pixel circuit (Fig. 14; wherein figure 14 shows the shield pattern BMLP corresponding to a portion of each pixel circuit and be arranged below the pixel circuit) and a third branch portion (Fig. 14; wherein figure a removed connection line) connected to the third main portion (BMLP; Fig. 14) and extending in the third direction (Fig. 14; wherein figure shows for the second pixel in the row a removed connection line not extending vertically upward from the main body BMLP of the second pixel in the row) from the third main portion (BMLP; Fig. 14),
wherein a length of the third branch portion (Fig. 14; wherein figure shows for the second pixel in the row a removed connection line not extending vertically upward from the main body BMLP of the second pixel in the row) along the third direction is less than a length of the first branch portion along the third direction (Fig. 14; wherein figure shows for the first pixel in the row a first connection line BMLC1 extending vertically upward from the main body BMLP of the first pixel in the row) and a length of the second branch portion along the third direction (Fig. 14; wherein figure shows for the third pixel in the row a first connection line BMLC1 extending vertically upward from the main body BMLP of the third pixel in the row).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Baek in view of Rhe, Lee, and Bang does not expressly disclose wherein a distance between the third branch portion and the hole area is less than a distance between the first branch portion and the hole area and a distance between the second branch portion and the hole area.
Lee (Fig. 1-35) (US 2023/0143745 A1) discloses wherein a distance between the third branch portion (BML; Fig. 7) and the hole area (OPS; Fig. 17) is less than a distance between the first branch portion (Fig. 7; wherein figure shows another BML area for the adjacent subpixel) and the hole area (OPS; Fig. 17) and a distance between the second branch portion (Fig. 7; wherein figure shows another BML area for the adjacent subpixel; wherein BML area is from the red subpixel different then the green and blue subpixel) and the hole area (OPS; Fig. 19).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe, Lee, and Bang’s display panel by applying a hole area, as taught by Lee, so to use a display panel with a hole area for improving display quality by reducing a reflective color band generated while being asymmetrically reflected due to reflection of external light (Paragraph [0007]).
Claim 16, Lee (Fig. 1-17) (US 2022/0181354 A1) discloses further comprising a first initialization control line (SL3; Fig. 2, 5, 7F) extending in the first direction (X; Fig. 5 and 7F),
wherein, in the plan view (Fig. 5 and 15), the first initialization control line (SL3; Fig. 5 and 15) intersects the first branch portion (BMC1; Fig. 7A) and the second branch portion (BMC1; Fig. 7A) and is spaced apart from the third branch portion (Fig. 16; wherein figure shows BMC1 is removed and therefore space apart from the branch portion).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe’s display panel by applying a shield layer, as taught by Lee, so to use a display panel with a shield layer for providing reduced power consumption and improved display quality (Paragraph [0005]).
Bang (Fig. 1-25) discloses wherein, in the plan view (Fig. 12), the first initialization control line (SL2; Fig. 4B; 12) is spaced apart from the hole area (TA; Fig. 11A-12).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe and Lee’s display panel by applying an initialization control line, as taught by Bang, so to use a display panel with an initialization control line for providing the arrangement and number of lines arranged or disposed in a second display area may be different from the arrangement and number of lines arranged or disposed in a first display area, and thus, a transmissive area may be increased or maximized and a lifespan of a panel may be increased (Paragraph [0239]).
Claim 17, Bang (Fig. 1-25) discloses wherein the first initialization control line (SL2; Fig. 4B) includes a second gate electrode (T4; Fig. 4B; wherein figure shows transistor T4 as a double gate structure) of the second transistor (T4; Fig. 4B) of each of the first pixel circuit (PC1; Fig. 11B and 12), the second pixel circuit (PC2; Fig. 11B and 12), and the third pixel circuit (PC3; Fig. 11B and 12).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Baek in view of Rhe and Lee’s display panel by applying an initialization control line, as taught by Bang, so to use a display panel with an initialization control line for providing the arrangement and number of lines arranged or disposed in a second display area may be different from the arrangement and number of lines arranged or disposed in a first display area, and thus, a transmissive area may be increased or maximized and a lifespan of a panel may be increased (Paragraph [0239]).
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection.
In view of arguments, the references of Baek et al (US 2020/0105843 A1), Rhe et al (US 2023/0006183 A1), Lee et al (US 2022/0181354 A1), Bang et al (US 2021/0183983 A1), and Lee et al (US 2023/0143745 A1) have been used for new ground rejection.
Claims 1, 11, and 20 are rejected in view of newly discovered reference(s) to Rhe et al (US 2023/0006183 A1).
Claims 3 and 15 are rejected in view of newly discovered reference(s) to Lee et al (US 2023/0143745 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam J Snyder/Primary Examiner, Art Unit 2623 07/28/2026
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