DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9, 11-12, 15-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (USPN 2013/0222357 A1) in view of Kim (USPN 2017/0178559 A1), and further in view of Kim (USPN 2024/0194147 A1).
As to claim 1, Tseng teaches a gate driver including a plurality of stages (see at least [0089] “the gate driver circuit 30 comprises a plurality of gate-driver stages”; [0096] “the multi-output circuit 200 comprises six sub-output circuits … for providing six gate signals G[N], G[N+1], … G[N+5]”; [0102] “Each gate-driver stage is used to generate gate line signals on R gate lines, with R being a positive integer greater than 1”; and [0120] “the gate-driver stages comprises Q stages, Q being a positive integer greater than 1”),
a gate output circuit configured to output first to P-th (wherein P is a positive integer greater than 2) gate clock signals as first to P-th gate signals (see at least [0098] “each of the gate signals G[N], G[N+1], … G[N+5] are sequentially generated in response to the sequential clock signals ck1, ck2, … ck6”; [0102] “P=12 … P=6”; [0119] “the output circuits comprises N output circuits arranged to receive N sequential clock signals for providing N sequential output signals”),
wherein the stages receive first to Q-th (wherein Q is a positive integer greater than P) gate clock signals (see at least [0096] “the multi-output circuit 200 comprises six sub-output circuits 210.sub.1, 210.sub.2, . . . , 210.sub.6 for providing six gate signals G[N], G[N+1], . . . , G[N+5]. The multi-output circuit has twelve clock inputs to receive clock signals ck1, ck2, . . . , ck6, xck1, xck2, . . . , xck6.”), and
wherein, when a first stage is configured to output first to P-th gate clock signals as first to P-th gate signals, a second stage is configured to output P+1-th to Q-th gate clock signals as P+1-th to Q-th gate signals, and then the second stage is configured to output the first gate clock signal as a Q+1-th gate signal (see at least [0092] “The first stage 100.sub.1 generates gate line signals G[N] to G[N+2] in response to input clock signals ck1, ck2, ck3, xck1, xck2, xck3 … The second stage 100.sub.2 generates gate line signals G[N+3] to G[N+5] in response to input clock signals ck4, ck5, ck6, xck4, xck5, xck6 ... The third stage 100.sub.3 generates gate line signals G[N+6] to G[N+8] in response to input clock signals xck1, xck2, xck3, ck1, ck2, ck3”),
a duration in which the Q+1-th gate signal is output is separated from a duration in which a voltage of a CQ node of the first stage has the high level (see at least [0094] “the first stage generates gate line signals G[N] to G[N+5] … The second stage generates gate line signals G[N+6] to G[N+11]”; [0120] “one of said N sequential output signals from the first stage is arranged to provide the trigger pulse to the main driver in the second stage. … the first output signal of the first stage and the first output signal of the second stage are shifted by N time units”; [0128] “the trigger pulse and the reset pulse are shifted by P time units”).
Tseng does not directly teach wherein each of the stages comprises: a CQ node charging circuit configured to provide a previous carry signal and a second high gate voltage to a CQ node in response to the previous carry signal; a first CQS node charging circuit configured to provide the second high gate voltage to a CQS node in response to the previous carry signal; a second CQS node charging circuit configured to provide a first high gate voltage to the CQS node in response to a voltage of a boosting node; a QB node control circuit configured to invert a voltage of the CQ node to provide the inverted voltage of the CQ node to a QB node; a CQ node boosting circuit configured to provide a boosting clock signal to the boosting node in response to the voltage of the CQ node, and to provide a second low gate voltage to the boosting node in response to a voltage of the QB node; and in response to the voltage of the CQ node, and to output a first low gate voltage as the first to P-th gate signals in response to the voltage of the QB node, wherein a pulse of each of the first to P-th gate signals is included in a duration in which the voltage of the boosting node has a high level, and the duration in which the voltage of the boosting node has the high level is included in a duration in which the voltage of the CQ node has the high level.
Kim (‘559) teaches wherein each of the stages comprises: a CQ node charging circuit configured to provide a previous carry signal and a second high gate voltage to a CQ node in response to the previous carry signal (see at least [0066] “The first carry signals Gout_Pre are used for pre-charging the Q node”; [0072] “The first carry signal Gout_Pre input to an nth stage … is an output Gout of an n−1th stage”);
a QB node control circuit configured to invert a voltage of the CQ node to provide the inverted voltage of the CQ node to a QB node (see at least [0079] “The second inverter INV2 supplies an inverted signal of the Q node Q to the Q Bar node QB”);
a CQ node boosting circuit configured to provide a boosting clock signal to the boosting node in response to the voltage of the CQ node, and to provide a second low gate voltage to the boosting node in response to a voltage of the QB node; and in response to the voltage of the CQ node, and to output a first low gate voltage as the first to P-th gate signals in response to the voltage of the QB node (see at least [0088] “a buffer outputting a clock as an output voltage when a voltage of the Q node is a high voltage and output a low voltage as an output voltage when a voltage of the QB node is a high voltage.”; [0092] “a pull-up transistor supplying the clock to an output terminal in response to the voltage of the Q node .. and a pull-down transistor supplying the low voltage to the output terminal in response to the voltage of the QB node”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Tseng’s multi-output gate-driver stages to employ Kim (‘559)’s CQ/QB carry-node architecture because Kim (‘559) teaches a compact gate-driver stage using a carry-driven Q node and complementary QB node to control clock output and low-level output while reducing clock lines and switching circuitry. Incorporating Kim (‘559)’s well-known carry-node control into Tseng’s multi-output stage would have predictably improved stage control and signal stability while preserving Tseng’s reduced-area GOA architecture.
Tseng and Kim (‘559) do not directly teach a first CQS node charging circuit configured to provide the second high gate voltage to a CQS node in response to the previous carry signal; a second CQS node charging circuit configured to provide a first high gate voltage to the CQS node in response to a voltage of a boosting node; wherein a pulse of each of the first to P-th gate signals is included in a duration in which the voltage of the boosting node has a high level, and the duration in which the voltage of the boosting node has the high level is included in a duration in which the voltage of the CQ node has the high level.
Kim (‘147) teaches a first CQS node charging circuit configured to provide the second high gate voltage to a CQS node in response to the previous carry signal (see at least [0091] “The seventh transistor T7 may be turned on by the voltage at the QN node to transmit the first high-clock signal HCLK1”; [0093] “The second auxiliary transistor Ta2 … may transmit the voltage at the QB node to the voltage at the QN node”; [0094] “The second capacitor CQN may store the voltage at the QN node” – note auxiliary node QN functions the same as the claimed CQS node);
a second CQS node charging circuit configured to provide a first high gate voltage to the CQS node in response to a voltage of a boosting node; (see at least [0098] “the QN node may change to a voltage lower than the second gate-low voltage VGL2 due to the bootstrapping of the second capacitor CQN connected to the QN node. .. the seventh transistor T7 can stably remain turn on while the second scan signal SCAN2(n) is output.” – note bootstrapped auxiliary node and capacitor arrangement are the same as the claimed boosting-node/CQS interaction);
wherein a pulse of each of the first to P-th gate signals is included in a duration in which the voltage of the boosting node has a high level, and the duration in which the voltage of the boosting node has the high level is included in a duration in which the voltage of the CQ node has the high level (see at least [0097] “the first high-clock signal HCLK1 is output at the second time t2 between the first time t1 and the third time t3 at which the first scan signal SCAN1(n) is output”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate Kim (‘147)’s auxiliary-node and bootstrapped second-output architecture into the Tseng/Kim (’354) gate-driver because Kim (’147) teaches generating an additional gate output using an auxiliary node and capacitor while sharing logic circuitry with the primary output stage. Such modification would have predictably enabled generation of additional gate outputs from a common stage while maintaining reduced circuit area and efficient clock utilization, which is the same objective as Tseng (see Tseng ([0101]-[0102]).
As to claim 19, Tseng teaches an electronic device, comprising:
a display panel including a pixel (see at least [0089] “the image on a display panel, such as a LCD panel, is composed of a plurality of pixels arranged in a two-dimensional array of columns and rows or lines. .. a display panel 10 comprises a display area 20 and a gate driver circuit 30”; [0121] “a display panel, such as a liquid-crystal display panel, which comprises a display area comprising a thin-film transistor array, the transistor array configured to receive gate lines signals in a plurality of gate lines for controlling an array of pixels”);
a gate driver configured to provide a gate signal to the pixel (see at least [0089] “Each line of pixels is activated or charged by a gate signal provided by the gate-line driver on a gate line. .. the gate driver circuit 30 provides the gate line signals to the display area 20 via a plurality of gate lines G1, G2, . . .”; [0121] “a gate line driver configured to provide the gate line signals to the thin-film transistor array”);
wherein the gate driver comprises a plurality of stages (see at least [0089] “the gate driver circuit 30 comprises a plurality of gate-driver stages”; [0096] “the multi-output circuit 200 comprises six sub-output circuits … for providing six gate signals G[N], G[N+1], … G[N+5]”; [0102] “Each gate-driver stage is used to generate gate line signals on R gate lines, with R being a positive integer greater than 1”; and [0120] “the gate-driver stages comprises Q stages, Q being a positive integer greater than 1”),
a gate output circuit configured to output first to P-th (wherein P is a positive integer greater than 2) gate clock signals as first to P-th gate signals (see at least [0098] “each of the gate signals G[N], G[N+1], … G[N+5] are sequentially generated in response to the sequential clock signals ck1, ck2, … ck6”; [0102] “P=12 … P=6”; [0119] “the output circuits comprises N output circuits arranged to receive N sequential clock signals for providing N sequential output signals”),
wherein the stages receive first to Q-th (wherein Q is a positive integer greater than P) gate clock signals (see at least [0096] “the multi-output circuit 200 comprises six sub-output circuits 210.sub.1, 210.sub.2, . . . , 210.sub.6 for providing six gate signals G[N], G[N+1], . . . , G[N+5]. The multi-output circuit has twelve clock inputs to receive clock signals ck1, ck2, . . . , ck6, xck1, xck2, . . . , xck6.”), and
wherein, when a first stage is configured to output first to P-th gate clock signals as first to P-th gate signals, a second stage is configured to output P+1-th to Q-th gate clock signals as P+1-th to Q-th gate signals, and then the second stage is configured to output the first gate clock signal as a Q+1-th gate signal,
(see at least [0092] “The first stage 100.sub.1 generates gate line signals G[N] to G[N+2] in response to input clock signals ck1, ck2, ck3, xck1, xck2, xck3 … The second stage 100.sub.2 generates gate line signals G[N+3] to G[N+5] in response to input clock signals ck4, ck5, ck6, xck4, xck5, xck6 ... The third stage 100.sub.3 generates gate line signals G[N+6] to G[N+8] in response to input clock signals xck1, xck2, xck3, ck1, ck2, ck3”),
a duration in which the Q+1-th gate signal is output is separated from a duration in which a voltage of a CQ node of the first stage has the high level (see at least [0094] “the first stage generates gate line signals G[N] to G[N+5] … The second stage generates gate line signals G[N+6] to G[N+11]”; [0120] “one of said N sequential output signals from the first stage is arranged to provide the trigger pulse to the main driver in the second stage. … the first output signal of the first stage and the first output signal of the second stage are shifted by N time units”; [0128] “the trigger pulse and the reset pulse are shifted by P time units”).
Tseng does not directly teach a data driver configured to provide a data voltage to the pixel; a driving controller configured to control the data driver and the gate driver; and a power supply configured to provide a power to the display panel, the data driver, the gate driver, and the driving controller, wherein each of the stages comprises: a CQ node charging circuit configured to provide a previous carry signal and a second high gate voltage to a CQ node in response to the previous carry signal; a first CQS node charging circuit configured to provide the second high gate voltage to a CQS node in response to the previous carry signal; a second CQS node charging circuit configured to provide a first high gate voltage to the CQS node in response to a voltage of a boosting node; a QB node control circuit configured to invert a voltage of the CQ node to provide the inverted voltage of the CQ node to a QB node; a CQ node boosting circuit configured to provide a boosting clock signal to the boosting node in response to the voltage of the CQ node, and to provide a second low gate voltage to the boosting node in response to a voltage of the QB node; and in response to the voltage of the CQ node, and to output a first low gate voltage as the first to P-th gate signals in response to the voltage of the QB node, wherein a pulse of each of the first to P-th gate signals is included in a duration in which the voltage of the boosting node has a high level, and the duration in which the voltage of the boosting node has the high level is included in a duration in which the voltage of the CQ node has the high level.
Kim (‘559) teaches a data driver configured to provide a data voltage to the pixel (see at least [0047] “ “The data driving circuit 120 includes a plurality of source drive ICs. .. The source drive ICs 120 convert the digital video data RGB into a gamma correction voltage to generate a data voltage… Then, the source drive ICs 120 supply the data voltage to the data lines of the display panel 160”);
a driving controller configured to control the data driver and the gate driver (see at least [0054] The timing controller 110 generates timing control signals to control an operation timing of the data driving circuit and the scan driving circuit ... The timing control signals include a scan timing control signal to control an operation timing of the scan driving circuit and a data timing control signal to control an operation timing of the source drive ICs 120”); and
a power supply configured to provide a power to the display panel, the data driver, the gate driver, and the driving controller (see at least [0049], [0072]-[0082] “gate high voltage VGH” and “gate low voltage VGL”; [0090]-[0097] “high voltage power line” and “low voltage power line”);
wherein each of the stages comprises: a CQ node charging circuit configured to provide a previous carry signal and a second high gate voltage to a CQ node in response to the previous carry signal (see at least [0066] “The first carry signals Gout_Pre are used for pre-charging the Q node”; [0072] “The first carry signal Gout_Pre input to an nth stage … is an output Gout of an n−1th stage”);
a QB node control circuit configured to invert a voltage of the CQ node to provide the inverted voltage of the CQ node to a QB node (see at least [0079] “The second inverter INV2 supplies an inverted signal of the Q node Q to the Q Bar node QB”);
a CQ node boosting circuit configured to provide a boosting clock signal to the boosting node in response to the voltage of the CQ node, and to provide a second low gate voltage to the boosting node in response to a voltage of the QB node; and in response to the voltage of the CQ node, and to output a first low gate voltage as the first to P-th gate signals in response to the voltage of the QB node (see at least [0088] “a buffer outputting a clock as an output voltage when a voltage of the Q node is a high voltage and output a low voltage as an output voltage when a voltage of the QB node is a high voltage.”; [0092] “a pull-up transistor supplying the clock to an output terminal in response to the voltage of the Q node .. and a pull-down transistor supplying the low voltage to the output terminal in response to the voltage of the QB node”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Tseng’s multi-output gate-driver stages to employ Kim (‘559)’s CQ/QB carry-node architecture because Kim (‘559) teaches a compact gate-driver stage using a carry-driven Q node and complementary QB node to control clock output and low-level output while reducing clock lines and switching circuitry. Incorporating Kim (‘559)’s well-known carry-node control into Tseng’s multi-output stage would have predictably improved stage control and signal stability while preserving Tseng’s reduced-area GOA architecture.
Tseng and Kim (‘559) do not directly teach a first CQS node charging circuit configured to provide the second high gate voltage to a CQS node in response to the previous carry signal; a second CQS node charging circuit configured to provide a first high gate voltage to the CQS node in response to a voltage of a boosting node; wherein a pulse of each of the first to P-th gate signals is included in a duration in which the voltage of the boosting node has a high level, and the duration in which the voltage of the boosting node has the high level is included in a duration in which the voltage of the CQ node has the high level.
Kim (‘147) teaches a first CQS node charging circuit configured to provide the second high gate voltage to a CQS node in response to the previous carry signal (see at least [0091] “The seventh transistor T7 may be turned on by the voltage at the QN node to transmit the first high-clock signal HCLK1”; [0093] “The second auxiliary transistor Ta2 … may transmit the voltage at the QB node to the voltage at the QN node”; [0094] “The second capacitor CQN may store the voltage at the QN node” – note auxiliary node QN functions the same as the claimed CQS node);
a second CQS node charging circuit configured to provide a first high gate voltage to the CQS node in response to a voltage of a boosting node; (see at least [0098] “the QN node may change to a voltage lower than the second gate-low voltage VGL2 due to the bootstrapping of the second capacitor CQN connected to the QN node. .. the seventh transistor T7 can stably remain turn on while the second scan signal SCAN2(n) is output.” – note bootstrapped auxiliary node and capacitor arrangement are the same as the claimed boosting-node/CQS interaction);
wherein a pulse of each of the first to P-th gate signals is included in a duration in which the voltage of the boosting node has a high level, and the duration in which the voltage of the boosting node has the high level is included in a duration in which the voltage of the CQ node has the high level (see at least [0097] “the first high-clock signal HCLK1 is output at the second time t2 between the first time t1 and the third time t3 at which the first scan signal SCAN1(n) is output”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate Kim (‘147)’s auxiliary-node and bootstrapped second-output architecture into the Tseng/Kim (’354) gate-driver because Kim (’147) teaches generating an additional gate output using an auxiliary node and capacitor while sharing logic circuitry with the primary output stage. Such modification would have predictably enabled generation of additional gate outputs from a common stage while maintaining reduced circuit area and efficient clock utilization, which is the same objective as Tseng (see Tseng ([0101]-[0102]).
As to claim 2, the combination of Tseng, Kim (‘559), and Kim (‘147) teach the gate driver of claim 1 (see above rejection), wherein Q is a multiple of 2 (see Tseng at least [0102] “Q=2 .. Q=4”).
As to claim 3, the combination of Tseng, Kim (‘559), and Kim (‘147) teach the gate driver of claim 1 (see above rejection), wherein Q is a minimum value which satisfies a condition that the duration in which the second stage is configured to output the Q+1-th gate signal is separated from the duration in which the voltage of the CQ node of the first stage has the high level (see Tseng at least [0120] “the first output signal of the first stage and the first output signal of the second stage are shifted by N time units” – note obvious design optimization).
As to claim 4, the combination of Tseng, Kim (‘559), and Kim (‘147) teach the gate driver of claim 1 (see above rejection), wherein the gate driver is configured to support a Dual Line Gate (DLG) mode, and while the gate driver is configured to perform the DLG mode, a time length of a pulse of each of the first to Q-th gate clock signals is reduced (see Tseng at least [0095] “The pulse-width of clock signals ck1, ck2, and ck3 is 3 H ... The pulse-width of clock signals ck1, ck2, . . . , ck6 is 6 H”; [0101] “the size of the GOA structure can be reduced”; [0110] “pulse-width of clock signals ck1 and ck2 is 1 H”).
As to claim 5, the combination of Tseng, Kim (‘559), and Kim (‘147) teach the gate driver of claim 1 (see above rejection), wherein P is 6 and Q is 10 (see Tseng at least [0102]: P=6, Q=2; P=6, Q=3; P=12, Q=2; P=12, Q=4).
As to claim 9, the combination of Tseng, Kim (‘559), and Kim (‘147) teach the gate driver of claim 1 (see above rejection), wherein the CQ node boosting circuit comprises: a first transistor including a gate electrode connected to the CQ node, a first electrode that receives the boosting clock signal, and a second electrode connected to the boosting node; a second transistor including a gate electrode connected to the QB node, a first electrode that receives the second low gate voltage, and a second electrode connected to the boosting node; and a CQ boost capacitor including a first electrode connected to the CQ node and a second electrode connected to the boosting node (see Tseng at least [0090] “main driver has two outputs denoted by Boost and node2”; [0097] “Boost signal level is pre-charged”; [0098] “clock signals sequentially increase the Boost signal level”).
As to claim 11, the combination of Tseng, Kim (‘559), and Kim (‘147) teach the gate driver of claim 1 (see above rejection), wherein each of the stages further comprises: a first CQ node discharging circuit configured to provide the second low gate voltage to the CQ node in response to a next carry signal; and a second CQ node discharging circuit configured to provide the second low gate voltage to the CQ node in response to the voltage of the QB node (see Kim (‘559) at least [0067], [0076]: second carry signal Gout_Post discharges Q node; [0075]-[0079]: QB node controls inverter action returning Q low).
As to claim 12, the combination of Tseng, Kim (‘559), and Kim (‘147) teach the gate driver of claim 11 (see above rejection), wherein the first CQ node discharging circuit comprises a first transistor including a gate electrode that receives the next carry signal, a first electrode that receives the second low gate voltage, and a second electrode connected to the CQ node, and wherein the second CQ node discharging circuit comprises a second transistor including a gate electrode connected to the QB node, a first electrode that receives the second low gate voltage, and a second electrode connected to the CQ node (see Kim (‘559) at least [0076], [0097]: M6 receives Gout_Post and pulls Q node low).
As to claim 15, the combination of Tseng, Kim (‘559), and Kim (‘147) teach the gate driver of claim 1 (see above rejection), wherein each of the stages further comprises a CQS node discharging circuit configured to provide the first low gate voltage to the CQS node in response to the voltage of the QB node (see Kim (‘147) at least [0093]: voltage at QB node transmitted to QN node and uses QN to control output transistor).
As to claim 16, the combination of Tseng, Kim (‘559), and Kim (‘147) teach the gate driver of claim 15 (see above rejection), wherein the CQS node discharging circuit comprises a first transistor including a gate electrode connected to the QB node, a first electrode that receives the first low gate voltage, and a second electrode connected to the CQS node (see Kim (‘147) at least [0093]: voltage at QB node transmitted to QN node and uses QN to control output transistor).
As to claim 17, the combination of Tseng, Kim (‘559), and Kim (‘147) teach the gate driver of claim 1 (see above rejection), wherein each of the stages further comprises a carry output circuit configured to output a carry clock signal as the carry signal in response to the voltage of the CQ node and to output the second low gate voltage as the carry signal in response to the voltage of the QB node (see Kim (‘559) at least [0062]: gate pulses Gout serve as carry signals; [0088], [0092]: buffer outputs clock when Q high and outputs low voltage when QB high).
As to claim 20, the combination of Tseng, Kim (‘559), and Kim (‘147) teach electronic device of claim 19 (see above rejection), wherein Q is a multiple of 2 (see Tseng at least [0102] “Q=2 .. Q=4”).
Allowable Subject Matter
Claims 6-8, 10, 13-14, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art of record teach:
“A gate driver including a plurality of stages, wherein each of the stages comprises: a CQ node charging circuit configured to provide a previous carry signal and a second high gate voltage to a CQ node in response to the previous carry signal; a first CQS node charging circuit configured to provide the second high gate voltage to a CQS node in response to the previous carry signal; a second CQS node charging circuit configured to provide a first high gate voltage to the CQS node in response to a voltage of a boosting node; a QB node control circuit configured to invert a voltage of the CQ node to provide the inverted voltage of the CQ node to a QB node; a CQ node boosting circuit configured to provide a boosting clock signal to the boosting node in response to the voltage of the CQ node, and to provide a second low gate voltage to the boosting node in response to a voltage of the QB node; and a gate output circuit configured to output first to P-th (wherein P is a positive integer greater than 2) gate clock signals as first to P-th gate signals in response to the voltage of the CQ node, and to output a first low gate voltage as the first to P-th gate signals in response to the voltage of the QB node, wherein a pulse of each of the first to P-th gate signals is included in a duration in which the voltage of the boosting node has a high level, and the duration in which the voltage of the boosting node has the high level is included in a duration in which the voltage of the CQ node has the high level, wherein the stages receive first to Q-th (wherein Q is a positive integer greater than P) gate clock signals, and wherein, when a first stage is configured to output first to P-th gate clock signals as first to P-th gate signals, a second stage is configured to output P+1-th to Q-th gate clock signals as P+1-th to Q-th gate signals, and then the second stage is configured to output the first gate clock signal as a Q+1-th gate signal, a duration in which the Q+1-th gate signal is output is separated from a duration in which a voltage of a CQ node of the first stage has the high level,
wherein the CQ node charging circuit comprises: a first-first transistor including a gate electrode that receives the previous carry signal, a first electrode that receives the previous carry signal, and a second electrode that receives the second high gate voltage; and a first-second transistor including a gate electrode that receives the previous carry signal, a first electrode that receives the second high gate voltage, and a second electrode connected to the CQ node,
or
wherein the first CQS node charging circuit comprises a first transistor including a gate electrode that receives the previous carry signal, a first electrode that receives the second high gate voltage, and a second electrode connected to the CQS node, and wherein the second CQS node charging circuit comprises a second transistor including a gate electrode that receives the voltage of the boosting node, a first electrode that receives the first high gate voltage, and a second electrode connected to the CQS node,
or
wherein the QB node control circuit comprises: a first transistor including a gate electrode that receives the first high gate voltage, a first electrode that receives the first high gate voltage, and a second electrode; an second transistor including a gate electrode connected to the second electrode of the first transistor, a first electrode that receives the first high gate voltage, and a second electrode connected to the QB node; a third transistor including a gate electrode connected to the CQ node, a first electrode that receives the first low gate voltage, and a second electrode connected to the second electrode of the first transistor and the gate electrode of the second transistor; and a fourth transistor including a gate electrode connected to the CQ node, a first electrode that receives the second low gate voltage, and a second electrode connected to the QB node,
or
wherein the gate output circuit comprises first to P-th gate output circuits configured to output the first to P-th gate signals, and wherein the P-th gate output circuit comprises: a P-th gate variable on transistor including a gate electrode connected to the CQS node, a first electrode connected to the CQ node, and a second electrode connected to a P-th gate Q node; a first-P-th transistor including a gate electrode connected to the P-th gate Q node, a first electrode that receives the P-th gate clock signal, and a second electrode connected to a P-th gate node from which the P-th gate signal is output; a second-P-th transistor including a gate electrode connected to the QB node, a first electrode that receives the first low gate voltage, and a second electrode connected to the P-th gate node; and a P-th gate boost capacitor including a first electrode connected to the P-th gate Q node and a second electrode connected to the boosting node,
or
wherein each of the stages further comprises a third CQS node charging circuit configured to provide the first high gate voltage to the CQS node in response to a next carry signal, wherein the third CQS node charging circuit comprises a first transistor including a gate electrode that receives the next carry signal, a first electrode that receives the first high gate voltage, and a second electrode connected to the CQS node,
or
wherein each of the stages further comprises a carry output circuit configured to output a carry clock signal as the carry signal in response to the voltage of the CQ node and to output the second low gate voltage as the carry signal in response to the voltage of the QB node, wherein the carry output circuit comprises: a carry variable on transistor including a gate electrode connected to the CQS node, a first electrode connected to the CQ node, and a second electrode connected to a carry Q node; a first transistor including a gate electrode connected to the carry Q node, a first electrode that receives the carry clock signal, and a second electrode connected to the carry node from which the carry signal is output; a second transistor including a gate electrode connected to the QB node, a first electrode that receives the second low gate voltage, and a second electrode connected to the carry node; and a carry boost capacitor including a first electrode connected to the carry Q node and a second electrode connected to the carry node.”
Conclusion
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/JENNIFER L ZUBAJLO/Examiner, Art Unit 2627 6/17/2026
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627
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