DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 10-12 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2022/0208104 A1).
As to claim 1, Chang et al. teaches a scan driver ([0053]: gate driver circuit) including a plurality of stages ([0075]: stages), wherein each of the plurality of stages comprises:
a first node controller configured to control a voltage level of a first control node (Q1 node in Fig. 5;[0091]: Q1 node controller 302 charges the Q1 node);
a second node controller configured to control a voltage level of a second control node (QB_o node in Fig. 5;[0102]: inverter 306 changes a voltage level of the QB_o node);
a first output controller including a first pull-up transistor (T71 in Fig. 5) and a first pull-down transistor (T72 in Fig. 5), wherein the first pull-up transistor (T71 in Fig. 5) has a gate connected to the first control node (Q1 node in Fig. 5), and is configured to output a scan signal of a first voltage ([0123-0124]: supplies the scan clock signal SCCLK(n) at the high level voltage to the second output node NO2), and the first pull-down transistor (T72 in Fig. 5) has a gate connected to the second control node (QB_o node in Fig. 5), and is configured to output the scan signal of a second voltage ([0126]: output a gate signal SCOUT(n) at a low level voltage based on the first low-potential voltage GVSS1 via the second output node NO2) lower than the first voltage ([0123-0124]:scan clock signal SCCLK(n) at the high level voltage); and
a second output controller including a second pull-up transistor (T61 in Fig. 5) and a second pull-down transistor (T62 in Fig. 5), wherein the second pull-up transistor (T61 in Fig. 5) has a gate connected to the first control node (Q1 node in Fig. 5), and is configured to output a carry signal of a third voltage ([0119]: output a high level voltage carry signal C(n) based on the carry clock signal CRCLK(n) via the first output node NO1), and the second pull-down transistor (T62 in Fig. 5) has a gate connected to the second control node (QB_o node in Fig. 5), and is configured to output the carry signal of a fourth voltage ([0120]: output a low level voltage carry signal C(n) based on the third low-potential voltage GVSS3 via the first output node NO1) lower than the third voltage ([0119]: output a high level voltage carry signal C(n) based on the carry clock signal CRCLK(n) via the first output node NO1). This particular embodiment does not explicitly disclose wherein a voltage difference between the first voltage and the second voltage of the scan signal is different from a voltage difference between the third voltage and the fourth voltage of the carry signal.
However, in another embodiment, Chang et al. teaches wherein a voltage difference between the first voltage ([0123-0124]:scan clock signal SCCLK(n) at the high level voltage) and the second voltage of the scan signal (([0126]: output a gate signal SCOUT(n) at a low level voltage based on the first low-potential voltage GVSS1 via the second output node NO2) is different from a voltage difference between the third voltage ([0119]: output a high level voltage carry signal C(n) based on the carry clock signal CRCLK(n) via the first output node NO1) and the fourth voltage of the carry signal ([0120]: output a low level voltage carry signal C(n) based on the third low-potential voltage GVSS3 via the first output node NO1;[0180]: low-potential voltage GVSS1, and low-potential voltage GVSS3 having different voltage levels; [0255]: The levels of the high-potential voltages and the low-potential voltage may vary).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. such that a voltage difference between the first voltage and the second voltage of the scan signal is different from a voltage difference between the third voltage and the fourth voltage of the carry signal as taught by another embodiment of Chang et al. in order to provide scan driver having improved durability and reliability.
As to claim 2, Chang et al. teaches the scan driver of claim 1, wherein the second control node includes a (2-1)st control node (QB_o node in Fig. 5) and a (2-2)nd control node (node connected to gate of transistor T73 and transistor T63 in Fig. 5;[0127]),
wherein the first pull-down transistor includes: a (1-1)st pull-down transistor (T72 in Fig. 5) connected between a first output terminal (N02 in Fig. 5) and a second voltage input terminal ([0126]: first low-potential voltage GVSS1), the (1-1)st pull-down transistor (T72 in Fig. 5) having a gate connected to the (2-1)st control node (QB_o node); and
a (1-2)nd pull-down transistor (T73 in Fig. 5) connected between the first output terminal (N02 in Fig. 5) and the second voltage input terminal ([0127]: first low-potential voltage GVSS1), the (1-2)nd pull-down transistor (T73 in Fig. 5) having a gate connected to the (2-2)nd control node(node connected to gate of transistor T73 and transistor T63 in Fig. 5;[0127]), and
wherein the (1-1)st pull- down transistor (T72 in Fig. 5) and the (1-2)nd pull-down transistor (T73 in Fig. 5) are configured to be alternately turned on in units of n times or 1/n times of a frame ([0126-0127];[0174]: the QB_o node and QB_e node of each stage circuit alternately charged or discharged in each frame), and wherein n is a natural number equal to or greater than 2 ([0024-0025];[0174];[0282]: alternately turned on or off in each frame (the odd-numbered frame and the even-numbered frame)).
As to claim 3, Chang et al. teaches the scan driver of claim 1, wherein the second control node includes a (2-1)st control node (QB_o node in Fig. 5) and a (2-2)nd control node (node connected to gate of transistor T73 and transistor T63 in Fig. 5;[0127]),
wherein the second pull-down transistor includes: a (2-1)st pull-down transistor (T62 in Fig. 5) connected between a second output terminal (N01 in Fig. 5) and a third voltage input terminal ([0120]: third low-potential voltage GVSS3), the (2-1)st pull-down transistor (T62 in Fig. 5) having a gate connected to the (2-1)st control node (QB_o node in Fig. 5); and
a (2-2)nd pull-down transistor (T63 in Fig. 5) connected between the second output terminal (N01 in Fig. 5) and the third voltage input terminal (third low-potential voltage GVSS3 in Fig. 5),
the (2-2)nd pull-down transistor (T63 in Fig. 5) having a gate connected to the (2-2)nd control node (node connected to gate of transistor T73 and transistor T63 in Fig. 5;[0127]); and wherein
the (2-1)st pull-down transistor (T62 in Fig. 5) and the (2-2)nd pull-down transistor(T63 in Fig. 5) are configured to be alternately turned on in units of n times or 1/n times of a frame (Fig. 5: gate of transistor T62 connected to QB_o node, gate of transistor T63 connected to QB_e node in Fig. 5; [0120];[0174]: the QB_o node and QB_e node of each stage circuit alternately charged or discharged in each frame), and wherein n is a natural number equal to or greater than 2 ([0024-0025];[0174];[0282]: alternately turned on or off in each frame (the odd-numbered frame and the even-numbered frame)).
As to claim 4, Chang et al. teaches the scan driver of claim 3, wherein the second output controller further includes a first capacitor connected between the first control node and the second output terminal ([0244-0245]: boosting capacitor CC is connected to and disposed between a gate and a source of the first transistor T61. The first transistor T61 outputs a high level voltage carry signal C(k) through the first output node NO1, based on the carry clock signal CRCLK(k), in response to a voltage of the Q node).
As to claim 10, Chang et al. teaches the scan driver of claim 1, wherein the first pull-up
transistor (T77 in Fig. 9) is connected between a scan clock terminal (SCCLK(i+3) terminal in Fig. 9)
and a first output terminal (N05 in Fig. 9), and the second pull-up transistor (T61 in Fig. 9) is
connected between a first carry clock terminal (CRCLK (k) in Fig. 9) and a second output terminal
(N01 in Fig. 9), and wherein a scan clock signal applied to the scan clock terminal is a signal in which the first voltage and the second voltage alternate with each other (Fig. 10 shows SCCLK(i+3) signal
alternates between the first voltage (high voltage) and the second voltage (low voltage GVSS1)) ,
and a carry clock signal applied to the first carry clock terminal is a signal in which the third
voltage and the fourth voltage alternate with each other (Fig. 10 shows CRCLK(k) signal alternates
between the third voltage (high voltage) and the fourth voltage (low voltage GVSS3)), wherein a period in which the scan clock signal is the first voltage overlaps a period in which the carry clock signal is the third voltage (Fig. 10 shows first voltage (high voltage) of scan clock signal SCCLK(i+3) overlaps a period in which the carry clock signal CRCLK(k) is the third voltage (high voltage)).
As to claim 11, Chang et al. teaches the scan driver of claim 10, wherein the first node
controller includes: a first transistor (T21 in Fig. 5) connected between an input terminal to which a start signal is applied ([0092]: front carry signal C(n-3)), and the first control node (Q1 node in Fig. 5); the first
transistor (T21 in Fig. 5) having a gate connected to a second carry clock terminal (C(n-3) terminal in Fig. 5), wherein a carry clock signal applied to the second carry clock terminal (C(n-3) terminal in Fig. 6) has a same waveform as that of the carry clock signal applied to the first carry clock terminal (Fig. 6 shows same pulse waveform of signals C(n-3) and CRCLK(n)), the carry clock signal applied to the second carry clock terminal (signal C(n-3) in Fig. 6) having a phase shifted by a preset interval (Fig. 6 shows the carry clock signal applied to the second carry clock terminal (signal C(n-3)) having a phase shifted by a preset interval from signal CRCLK(n)).
As to claim 12, Chang et al. teaches the scan driver of claim 1, further comprising a stabilizer configured to maintain the first control node at a second voltage level based on the second control node being at a first voltage level ([0097]: stabilizer 304 discharges the Q1 node to the third low-potential voltage GVSS3 level in response to a voltage of the QB_o node).
As to claim 16, Chang et al. teaches a scan driver ([0053]: gate driver circuit) including a plurality of stages ([0075]: stages), wherein each of the plurality of stages comprises:
a first node controller configured to control a voltage level of a first control node (Q1 node in Fig. 5;[0091]: Q1 node controller 302 charges the Q1 node);
a second node controller configured to control a voltage level of a second control node (QB_o node in Fig. 5;[0102]: inverter 306 changes a voltage level of the QB_o node);
a first output controller including a first pull-up transistor (T71 in Fig. 5) and a first pull-down transistor (T72 in Fig. 5), wherein the first pull-up transistor (T71 in Fig. 5) has a gate connected to the first control node (Q1 node in Fig. 5), and is configured to output a scan signal of a first voltage ([0123-0124]: supplies the scan clock signal SCCLK(n) at the high level voltage to the second output node NO2), and the first pull-down transistor (T72 in Fig. 5) has a gate connected to the second control node (QB_o node in Fig. 5), and is configured to output the scan signal of a second voltage ([0126]: output a gate signal SCOUT(n) at a low level voltage based on the first low-potential voltage GVSS1 via the second output node NO2) lower than the first voltage ([0123-0124]: scan clock signal SCCLK(n) at the high level voltage); and
a second output controller including a second pull-up transistor (T61 in Fig. 5) and a second pull-down transistor (T62 in Fig. 5), wherein the second pull-up transistor (T61 in Fig. 5) has a gate connected to the first control node (Q1 node in Fig. 5), and is configured to output a carry signal of the first voltage ([0119]: output a high level voltage carry signal C(n) based on the carry clock signal CRCLK(n) via the first output node NO1), and the second pull-down transistor (T62 in Fig. 5) has a gate connected to the second control node (QB_o node in Fig. 5), and is configured to output the carry signal of a third voltage ([0120]: output a low level voltage carry signal C(n) based on the third low-potential voltage GVSS3 via the first output node NO1),
wherein the second control node includes a (2-1)st control node (QB_o node in Fig. 5) and a (2-2)nd control node (node connected to gate of transistor T73 and transistor T63 in Fig. 5;[0127]),
wherein the first pull-down transistor includes: a (1-1)st pull-down transistor (T72 in Fig. 5) connected between a first output terminal (N02 in Fig. 5) and a second voltage input terminal ([0126]: first low-potential voltage GVSS1), the (1-1)st pull-down transistor (T72 in Fig. 5) having a gate connected to the (2-1)st control node (QB_o node); and
a (1-2)nd pull-down transistor (T73 in Fig. 5) connected between the first output terminal (N02 in Fig. 5) and the second voltage input terminal ([0127]: first low-potential voltage GVSS1), the (1-2)nd pull-down transistor (T73 in Fig. 5) having a gate connected to the (2-2)nd control node(node connected to gate of transistor T73 and transistor T63 in Fig. 5;[0127]),
wherein the second pull-down transistor includes: a (2-1)st pull-down transistor (T62 in Fig. 5) connected between a second output terminal (N01 in Fig. 5) and a third voltage input terminal ([0120]: third low-potential voltage GVSS3), the (2-1)st pull-down transistor (T62 in Fig. 5) having a gate connected to the (2-1)st control node (QB_o node in Fig. 5); and
a (2-2)nd pull-down transistor (T63 in Fig. 5) connected between the second output terminal (N01 in Fig. 5) and the third voltage input terminal (third low-potential voltage GVSS3 in Fig. 5),
the (2-2)nd pull-down transistor (T63 in Fig. 5) having a gate connected to the (2-2)nd control node (node connected to gate of transistor T73 and transistor T63 in Fig. 5;[0127]). This particular embodiment does not disclose wherein the third voltage is lower than the second voltage.
However, in another embodiment, Chang et al. teaches wherein the third voltage ([0180]; [0255]: GVSS3 set to −12V). is lower than the second voltage ([0180];[0255]: GVSS1 set to −6V).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. such that the third voltage is lower than the second voltage as taught by another embodiment of Chang et al. in order to provide scan driver having improved durability and reliability.
As to claim 17, Chang et al. teaches the scan driver of claim 16, wherein the (1-1)st pull- down transistor (T72 in Fig. 5) and the (1-2)nd pull-down transistor (T73 in Fig. 5) are configured to be alternately turned on in units of n times or 1/n times of a frame ([0126-0127];[0174]: the QB_o node and QB_e node of each stage circuit alternately charged or discharged in each frame), and
the (2-1)st pull-down transistor (T62 in Fig. 5) and the (2-2)nd pull-down transistor(T63 in Fig. 5) are configured to be alternately turned on in units of n times or 1/n times of a frame (Fig. 5: gate of transistor T62 connected to QB_o node, gate of transistor T63 connected to QB_e node in Fig. 5; [0120];[0174]: the QB_o node and QB_e node of each stage circuit alternately charged or discharged in each frame), and wherein n is a natural number equal to or greater than 2 ([0024-0025];[0174];[0282]: alternately turned on or off in each frame (the odd-numbered frame and the even-numbered frame)).
As to claim 18, Chang et al. teaches the scan driver of claim 16, further comprising:
a fourth transistor (T31 in Fig. 5) connected between the second output terminal (N01 in Fig. 5) and a third node (node directly connecting transistor T22 and T23 in Fig. 5), the fourth transistor (T31 in Fig. 5) having a gate connected to the (2-1)st control node (QB_o node in Fig. 5);
a fifth transistor (T33 in Fig. 5) connected between the second output terminal (N01 in Fig. 5) and the third node (node directly connecting transistor T22 and T23 in Fig. 5), the fifth transistor (T33 in Fig. 5) having a gate connected to the (2-2)nd control node (node connected to gate of transistor T73 and transistor T63 in Fig. 5;[0127]); and
a third transistor (T23 in Fig. 5) connected between the third node (node directly connecting transistor T22 and T23 in Fig. 5) and the first control node (transistor T23 is connected to Q1 node through transistors T24, T34 and T33 in Fig. 5), the third transistor (T23 in Fig. 5) having a gate that receives a carry clock signal (C(n+4) signal in Fig. 5).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2022/0208104 A1) in view of Fu (CN106448532 A, attached English machine translation is used in the rejection).
As to claim 15, Chang et al. teaches the scan driver of claim 1, but does not explicitly disclose wherein the first pull-up transistor, the first pull-down transistor, the second pull-up transistor and the second pull-down transistor are oxide transistors.
However, Fu teaches wherein the first pull-up transistor, the first pull-down transistor, the second pull-up transistor and the second pull-down transistor are oxide transistors ([0044]: each first pull-up output module, second pull-up output module, the first pull-down output module , and the second pull-down output module includes metal-oxide-semiconductor transistor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang et al. such that the first pull-up transistor, the first pull-down transistor, the second pull-up transistor and the second pull-down transistor are oxide transistor as taught by Fu because oxide transistors have low leakage current.
Allowable Subject Matter
Claims 5-9, 13-14 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4, 10-12, and 15-18 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
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