DETAILED ACTION
Claims 1-4 and 6-10 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on application CN 2024110749157, filed on August 7, 2024. It is noted, however, that applicant has not filed a certified copy of the application as required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of species I in the reply filed on June 1, 2026, is acknowledged.
Specification
The title of the invention is objected to for use of “QUICKLY” (see issue below). A new title is required. At this point in time, the examiner recommends --CPU FOR EXECUTING A MEMORY COPY INSTRUCTION USING A STATE MACHINE--.
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided. As such, please replace instances of “comprises” and any variation thereof.
The abstract of the disclosure is objected to because of the following informalities:
In line 2, “the CPU comprises:” in this context is grammatically incorrect and must be reworded. For instance, it should read --the CPU including:--. Or, applicant could insert a period after “therefor” and start a new sentence with --The CPU includes an instruction decoder…--.
Periods and new sentences should start after “comparator” in line 3, and after “the first instance of “state machine” in line 4, to improve readability.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In paragraphs 5, 63, and 69, please correct each instance of “din a case thatferent”.
In paragraphs 24 and 60, the examiner does not understand how a vacant bit could be not less than 2N bytes. A vacant bit is 1 bit, which is always less than any number of bytes.
In paragraphs 24 and 60, please correct each instance of “signin a case thaticant bit”.
In paragraph 42, please correct “spec in a case thatic”.
In paragraph 62, please correct “spec in a case thatically”.
Appropriate correction is required.
Drawings
FIGs.1 and 3 are objected to because the text is too small. 37 CFR 1.84(p)(3) requires that all numbers, letters, and reference characters measure at least 1/8 inches in height. The examiner asserts that at least some of the text does not satisfy this requirement. Applicant is asked to print the drawings, measure the text, and enlarge the text where appropriate.
FIGs.1-3 are objected to for failing to comply with 37 CFR 1.84(t), which requires that drawing sheet numbers be placed in the middle of the top of the sheet, but not in the margin. From 37 CFR 1.84(f), the top of the sheet is regarded as one of the shorter sides. Applicant's sheet numbers incorrectly appear at the bottom. The sheet numbers should also appear as “1/3”, “2/3”, and “3/3”.
FIGs.1 and 3 are objected to for failing to comply with 37 CFR 1.84(p)(3), which states that “Numbers, letters, and reference characters…should not be placed in the drawing so as to interfere with its comprehension. Therefore, they should not cross or mingle with the lines.” For instance, in FIG.1, the text in the ovals within the Memory copy controller overlaps various lines, as does other text in FIGs.1 and 3 (e.g. “address” appears to be obscuring “OP1” within the Adder; and, in the general-purpose register, text should be fully within the border).
FIG.2 is objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(L), which requires that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The examiner asserts that the quality of FIG.2, which includes blurry, fuzzy, faded, non-uniform text, is inadequate.
The drawings are objected to because of the following minor informalities:
In FIG.1, remove the word “DRAWINGS”
In FIG.1, replace “machin” with --machine--.
In FIG.1, fit the word “Comparator” on one line (like in FIG.3).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Please ensure any replacement is in only black and white to avoid pixelation and further objection. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections/Recommendations
In general, the examiner recommends increasing the number of paragraphs and/or making better use of indentation to improve readability (for instance, see claim 1 as shown in the 12-page document submitted on January 14, 2026).
In claims 1, 4, 6, and 10, the examiner recommends inserting --file-- after each instance of “general-purpose register” based on paragraph 48 of the specification, which states “The general-purpose register is a register file for storing temporary results inside the CPU…”. This would allow the claim to be more properly interpreted without referencing the disclosure, as a register is generally understood to be a singular storage location within a register file, and applicant clearly means for the register to be a file.
Claim 1 is objected to because of the following informalities:
In claim 1, line 1, replace “CPU” with --central processing unit (CPU)--. An abbreviation should be spelled out before it appears.
On page 1, line 12, insert --wherein, -- before “in the read state”.
Claim 2 is objected to because of the following informalities:
Replace both instances of “2N” with --2N-- to match the specification (e.g. paragraphs 15 and 50). Not only does the latter appear to be correct, but under Patent Prosecution Highway (PPH), it is the examiner’s understanding that the filed claims must sufficiently match the allowed claims from another patent office. Claim 2 is significantly different from allowed claim 2 as submitted by applicant on January 14, 2026.
Claim 3 is objected to because of the following informalities:
Both “end address of the source address” and “end address of the target address” are grammatically incorrect and must be reworded. From paragraph 47, it appears applicant means --end address relative to a source address-- and --end address relative to the target address--.
Claim 4 is objected to because of the following informalities:
In line 2, what is the purpose of “wherein one state machine, one adder and one bus interface are provided respectively;”? Such is already established by claim 1, which claims all three of these components. Applicant is asked to remove redundancy where possible.
Claim 7 is objected to because of the following informalities:
Replace all three instances of “2N” with --2N-- to match the specification (e.g. paragraphs 34 and 59). Again, not only does the latter appear to be correct, but under PPH, it is the examiner’s understanding that the filed claims must sufficiently match the allowed claims from another patent office. Claim 7 is significantly different from allowed claim 7 as submitted by applicant on January 14, 2026.
Claim 8 is objected to because of the following informalities:
Replace all four instances of “2N” with --2N-- to match the specification (e.g. paragraph 60). Similar comments made above for claims 2 and 7 also apply here.
Appropriate correction is required.
Claim Interpretation
At least one claim is identified as including a non-limiting contingent limitation. “The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” “The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.” See MPEP 2111.04(II).
Regarding claim 6, if a valid memory copy instruction is not received, then only lines 1-4 of the claim are limiting, i.e., everything else is not required to be performed by the method. The examiner recommends rewording to require all limitations. For instance, after line 4, applicant could insert a line claiming --receiving, by the instruction decoder, the valid memory copy
instruction;--. Applicant should also amend to require any additional contingent limitations.
Regarding claim 7, the read and write state are simply further defined, but the method does not require being in either state if the valid memory copy instruction is not received. Thus, claim 7, under broadest reasonable interpretation (BRI), does not require anything beyond claim 6 under its BRI.
Regarding claim 8, again, all limitations are non-limiting because they depend on the valid memory copy instruction being received. Also, even if received, there are contingencies based on the values of the bits, e.g. the vacant bit. Thus, at most one of the limitations for each bit is limiting.
Regarding claim 9, again, when there is no valid instruction, the system doesn’t go to the read state and empty state. Thus, claim 9 sets forth non-limiting steps under BRI.
Regarding claim 10, the entirety of the claim is based on receiving an interrupt request signal or a debugging signal. When neither is received, claim 10 is not limiting under BRI.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “quickly” in claims 1-4 and 6-10 is a relative term which renders the claims indefinite. The term is not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. That is, one of ordinary skill in the art would not understand where the line is drawn between “quick processing” and not quick processing.
In claim 6, on page 4, 1st paragraph, it is not clear what is meant by reading register labels to the general-purpose register. Thus, the claim is indefinite. The examiner believes applicant may be reading the labels from the instruction and sending them to the register file so as to access the contents of the registers identified by the labels. If this is the case, please make this clear.
In claim 6, it is not clear what is meant by “reading the data at least once” and “writing the data at least once” in the context claimed. The data read and written is associated with the source address and target address, which are singular. Thus, data associated with any given address is only being read and written once, whereas the claim appears to be encompassing an embodiment where the same data is read/written multiple times. This is inconsistent with the specification (MPEP 2173.03), particularly where it is described that data may be read and then the source address is incremented (e.g. paragraph 51). Thus, if, after a read, the source address (and similarly the target address on a write) is incremented, then the data at each source address is not read more than once. Thus, it’s not clear if applicant is actually reading the same data item repeatedly before writing that same data item repeatedly. If applicant means that at least one data item from at least one source address is read before switching to the write state, and then writing at least one data item to at least one target address before switching back to the read state, this needs to be clarified. The specification should be clarified as well (where it includes the “at least once” language (paragraphs 22 and 59). The examiner believes applicant means to read first data from a first source address, increment the source address, and then read second data from the incremented source address (when “at least once” encompasses two times, for instance). Then, the system switches to the write state, where the two data items are written to two different target addresses before switching back to the read state. Alternatively, applicant may mean to read multiple data items (e.g. bytes) at once in response to the same source address (paragraph 51) and then write these bytes to the same target address, before repeating the process at the next source/target addresses (however, this is not the same data being read more than once).
In claim 8, the examiner does not understand how a vacant bit can be not less than 2N bytes. A bit is a single bit. A byte is 8 bits. Thus, a vacant bit would always be less than any number of bytes. Similarly, in line 6, how could the bit be not less than a number of bytes? The claim is not understood.
In claim 8, the phrase “signin a case thaticant bit” is not English and not understood. Thus, the claim is indefinite.
The term “about” in claim 9 is a relative term which renders the claim indefinite. The term is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Specifically, paragraphs 26, 62, and 65, which include the nine instances of “about” in the specification, do not make clear when the read is “about to be finished”. It seems to be based on some comparison to the end information, but it is not clear if the read is about to be finished when the current source address equals the copy end information, or if it must be within some distance from the copy end information. Applicant has not made this clear.
In claim 9, there is a lack of antecedent basis for each instance of “the read operation” and “the write operation”. No such operations were previously set forth.
The term “normally”, used multiple times in claim 10, is a relative term which renders the claim indefinite. The term is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Specifically, applicant never established what it means for a processor to normally respond to interrupt and debugging requests and one of ordinary skill in the art would not know where the line is drawn between a normal response and an abnormal response.
In claim 10, there is a lack of antecedent basis for “the remaining memory copy”. Does applicant mean --a remaining portion of memory copy--?
All dependent claims are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Mishaeli (US 2017/0285959) in view of Nagabhushana et al. (US 2008/0172534).
Referring to claim 1, Mishaeli has taught a CPU (FIG.5, 530) capable of quickly processing a memory copy instruction (FIG.5, 531), comprising:
an instruction decoder (FIG.5, at least 532), which has an input terminal for inputting a CPU instruction (from FIG.5, instructions are input into the decoder via terminal) and an output terminal connected with a read port of a general-purpose register (FIG.5, 534 represent registers that are part of a register file (e.g. FIG.10B, 1058). These registers hold operands of the memory copy instruction and would be read when the decoder encounters a memory copy instruction. Thus, there must be a connection from the output of the decoder and a read port of the registers so as to read the operands needs to perform the memory copy) and a memory copy controller (FIG.5, 533), and is used for decoding a valid memory copy instruction (FIG.5, 531), wherein the valid memory copy instruction comprises a source address register label (from abstract, the instruction includes an identifier/label for register 535, which holds a source address), a target address register label (from abstract, the instruction includes an identifier/label for register 536, which holds a target address) and a copy end information register label (from abstract, the instruction includes an identifier/label for register 537, which holds copy end (copy amount) information);
the general-purpose register (again, from paragraph 48 of applicant’s specification, “The general-purpose register is a register file”. This component would correspond to file 1058 in FIG.10B, which includes the registers of FIG.5), which is connected with the memory copy controller (FIG.10B shows the register file connected to the execution unit 1060. Such a connection is necessary to execute the memory copy using the register parameters), and used for storing a source address, a target address and copy end information (see FIG.5, registers 535-537);
the memory copy controller, which comprises an idle state, a read state and a write state, and in the idle state, the instruction decoder waits for receiving a valid memory copy instruction (see paragraphs 62-64, and FIG.5. Basically, the execution unit logic that performs the memory copy will only do so when a memory copy instruction is encountered. Otherwise, that particular logic, including logic 539 will be idle); in the read state, a bus interface is controlled to read data from the source address (see FIG.2, which shows data is read (in a read state) from source address 0100. This would be the address stored in register 534); and in the write state, the bus interface is controlled to write the data to the target address (see FIG.2, which shows writing (in a write state) the data from address 0100 to target address 0105, which would be in register 535);
Mishaeli has not taught that the memory copy controller comprises a state machine, wherein the state machine comprises the idle state, the read state and the write state. However, Nagabhushana has taught such a state machine to perform memory operations (see FIG.2 and paragraph 27). Paragraph 62 of Mishaeli has taught that implementations may vary and may include any combination of hardware and/or software. A state machine is a known way to implement logic having defined states. State machines are simple implementations and are predictable and deterministic by nature with their explicitly enforceable transitions. This also allows for easier debugging. And, they require little memory and processing power to implement. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishaeli such that the memory controller comprises a state machine, wherein the state machine comprises the idle state, the read state and the write state.
Mishaeli has also not taught that the data read from the source address are temporarily stored in a buffer and that the data written to the target address is the temporarily stored data from the buffer to the target address. In other words, Mishaeli has not taught that the data flowing from sources to targets in FIG.2 goes through a buffer. However, Mishaeli has taught replacing a memmove function with the memory copy instruction, where the memmove function stores read data to a temporary array before writing it to a target (see paragraphs 100 and 102). The examiner notes the known advantages of buffering data including to decouple the reading and writing. That is, data may be read as part of a copy operation but cannot be currently written to the target, perhaps because another access of that target is currently in progress (e.g. by another thread or previous write). In such a case, buffering the data would be useful to hold the data until the target is free, at which point it may be copied from the buffer. This will allow the reading to continue buffering data until finished so that the reading can finish as soon as possible, thereby partially freeing up the processor to proceed with other work. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Mishaeli such that the data read from the source address are temporarily stored in a buffer and that the data written to the target address is the temporarily stored data from the buffer to the target address.
Mishaeli, as modified, has further taught the CPU comprising:
the bus interface, which is connected with the memory copy controller and the buffer, and externally connected with an external storage (see FIG.5. The memory controller (at least 533) and the buffer would be connected via bus interface to an external storage (545) to perform a copy of data therein);
the buffer, which is connected with the memory copy controller (again, as modified, Mishaeli would include the buffer to hold read data before it is written to the target);
an adder, which has an input terminal connected with the read port of the general-purpose register and the memory copy controller, and an output terminal connected with a write port of the general-purpose register, and is used for updating the source address and the target address (see the example in the code in paragraph 33. The first source address is in the ESI register (in FIG.2, ESI = 0100). The first target address is in the EDI register (in FIG.2, EDI = 0105). After the copy of data (FIG.2, “H”) from 0100 to 0105 occurs (using the buffer), an adder is used to read and increment data in both ESI and EDI (via “++”) and then write the incremented data back to the same registers such that they now equal 0101 and 0106, respectively. Then the next copy occurs (FIG.2, “O”)); and
a comparator, which has an input terminal connected with the read port of the general-purpose register and an output terminal connected with the memory copy controller, and is used for judging whether memory copy is finished according to the copy end information (again, see the example code in paragraph 33. The copy end information is stored in register ECX. This register is read, and its contents are compared to 0. When 0, the memory copy is finished and the memory controller will be instructed to cease copying data).
Referring to claim 2, Mishaeli, as modified, has taught the CPU capable of quickly processing the memory copy instruction according to claim 1, wherein a space of the buffer is M*2N bytes, wherein M is a positive integer and 2N is a width of the bus interface (since a buffer exists to store data to be copied, the buffer must be able to accommodate at least one read data value. The data value is 2N bytes wide. Thus, the buffer must be 2N bytes wide. And, M is at least equal to 1 to hold that value. In other words, in order to hold a single item, the bare minimum size (space) the buffer could have is 2N bytes (which corresponds to M=1)).
Referring to claim 3, Mishaeli, as modified, has taught the CPU capable of quickly processing the memory copy instruction according to claim 1, wherein the copy end information is one or more of an end address of the source address, an end address of the target address and a total copy length (again, see the code in paragraph 33. ECX corresponds to a copy length).
Referring to claim 6, under the interpretation where the instruction decoder does not receive the valid memory copy instruction (and, thus, the contingent limitations of the method are not performed), Mishaeli, as modified, has taught a method for quickly processing a memory copy instruction by using the CPU capable of quickly processing the memory copy instruction according to claim 1, comprising the following step of: allowing the state machine of the memory copy controller to be in the idle state initially (again, as modified, there is an idle state (FIG.2, 22 of Nagabhushana) that would be used when the memory controller is not performing a memory copy, e.g. when the processor is not currently performing a copy, but instead branch instructions (paragraph 193), arithmetic/logical instructions (paragraph 3), etc.);
Referring to claim 6, taking into account all limitations, Mishaeli, as modified, has taught a method for quickly processing a memory copy instruction by using the CPU capable of quickly processing the memory copy instruction according to claim 1, comprising the following steps of: allowing the state machine of the memory copy controller to be in the idle state initially (again, as modified, there is an idle state (FIG.2, 22 of Nagabhushana) that would be used when the memory controller is not performing a memory copy, e.g. when the processor is not currently performing a copy, but instead branch instructions (paragraph 193), arithmetic/logical instructions (paragraph 3), etc.); when the instruction decoder receives the valid memory copy instruction, reading the source address register label, the target address register label and the copy end information register label from the valid memory copy instruction to the general-purpose register (per the abstract and FIG.5, the instruction identifies the claimed labels and sends them to general-purpose registers 534 to access the claimed information from registers 535-537), sending an actuating signal to the memory copy controller at the same time (when the decoder decodes a memory copy instruction, signals are sent to various logic components to start the memory copy process. At least one of these signals is the actuating signal), and obtaining and outputting, by the general-purpose register, initial values of the source address and the target address and the copy end information through the source address register label, the target address register label and the copy end information register label (the claimed data is obtained and outputted from registers 535-537); and when the memory copy controller receives the actuating signal, allowing the state machine to jump to the read state, reading the data from the source address through the bus interface and temporarily storing the data in the buffer (see FIG.2 and the code in paragraph 33. Data is read from the current source address in ESI and would be stored in a buffer, as modified. Note from FIG.2 of Nagabhushana that the read state 26 may be entered after the controller is activated), and allowing the state machine to jump to the write state after reading the data at least once (again, see the code of paragraph 33. After the data is read from the current source address, it is written to the current target address, which necessarily requires a jump to the write state); in the write state, writing the data in the buffer to the target address in sequence according to a principle of first-in, first-out through the bus interface (from FIG.2 of Mishaeli, as modified, data is written from the buffer in FIFO fashion (e.g. ‘H’ is first read and first written, ‘O’ is second read and second written, etc.), clearing written data in the buffer (reading data from the buffer so that it may be written clears that data from the buffer (otherwise it could be written twice, which would be incorrect), and allowing the state machine to jump to the read state after writing the data at least once (again, see the code of paragraph 33. Each iteration of the loop does a read and write. Thus, the state machine ping-pongs between read and write states); and constantly switching the state machine between the read state and the write state (again the loop in paragraph 33 will constantly switch between the two states), updating the source address and the target address by the adder (see the code of paragraph 33, where both addresses are updated via incrementing (++)), judging whether memory copy is finished by the comparator according to the copy end information (the code of paragraph 33 compares the copy end information associated with ECX (if it is greater than 0, data remains to be copied)), and allowing the state machine to return to the idle state in a case that memory copy is finished (when the memory copy is complete, the state machine will be idle again until the next memory copy (just as Nagabhushana shows returning to the idle state after a memory operation)).
Referring to claim 7, Mishaeli, as modified, has taught the method for quickly processing the memory copy instruction according to claim 6 (under either interpretation above), wherein, in the read state, 1-2N bytes of data are read each time; and in the write state, 1-2Nbytes of data are written each time, and 2N is the width of the bus interface (from paragraph 27, the data may be of various size, include byte-size. Thus, when each element in FIG.2 is a byte, 1 byte of data is read each time, and 1 byte is written each time. Thus, the range of data read/written by applicant is satisfied by Mishaeli).
Referring to claim 8, Mishaeli, as modified, has taught the method for quickly processing the memory copy instruction according to claim 7. Based on the first rejection of claim 6, where contingent limitations are not performed, claim 8 is rejected for similar reasoning as claim 7 because it includes no limitations beyond that in claim 7 (the read and write states of claim 8 are only active when the memory copy instruction is received. When not received, no limitations are set forth in claim 8).
Referring to claim 9, Mishaeli, as modified, has taught the method for quickly processing the memory copy instruction according to claim 6. Based on the first rejection of claim 6, where contingent limitations are not performed, claim 9 is rejected for similar reasoning as claim 6 because it includes no limitations beyond that in claim 6 (the read and empty states of claim 9 are only active when the memory copy instruction is received. When not received, no limitations are set forth in claim 9).
Referring to claim 10, Mishaeli, as modified, has taught the method for quickly processing the memory copy instruction according to claim 6. As described above, all limitations in this claim are contingent on an interrupt or debugging request being received. Thus, when such a request is not received, claim 10 sets forth nothing beyond that in claim 6 and, thus, is rejected for similar reasons as claim 6.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable over the prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Caulfield (US 2024/0036760) has taught a bulk memory move/copy instruction.
Arimilli (US 2018/0052608) has taught a memory move instruction sequence to copy data.
Mistry (US 2023/0030741) has taught an efficient compressed verbatim copy (e.. FIGs.28A and 31A)
Mathew (US 2022/0076717) has taught a memory controller for copying data.
Kamath has taught “(MC)2: Lazy MemCopy at the Memory Controller”, including providing a source, destination, and size for a memory copy.
Jiang has taught “Architecture Support for Improving Bulk Memory Copying and Initialization Performance”.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
Prosecution Insights