DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/08/2025 and 06/02/2026 are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1, 4 and 8-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1, 3, 5-9 and 11-14 of US. Patent No. 12,406,615. Although the conflicting claims are not identical, they are not patentably distinct from each other because the broader claim limitation of claims 1, 18 and 19 of the current application is met by the narrower claim limitation of claims 1 and 7 of US. Patent No. 12,406,615 as shown in the following tables and the discussion thereafter.
Current Application
US. Patent No. 12,406,615
1. A display panel, comprising:
a driver circuit and a pixel circuit;
a light-emitting element, wherein the light-emitting element comprises a first electrode and a second electrode;
a first power signal bus and a second power signal bus, wherein the first power signal bus is connected to the pixel circuit, the pixel circuit is connected to the first electrode, and the second power signal bus is connected to the second electrode; and
an auxiliary connection layer, wherein the auxiliary connection layer is located between a film where the second electrode is located and a film where the second power signal bus is located, and the auxiliary connection layer is connected to the second electrode and the second power signal bus;
wherein the second power signal bus at least partially overlaps the driver circuit;
wherein the driver circuit comprises a first driver circuit, the first driver circuit is configured to provide a first control signal for the pixel circuit, and the first driver circuit comprises a plurality of stages of first shift registers cascaded with each other in a first direction;
wherein the display panel further comprises a first signal line group, and the first signal line group is connected to the first driver circuit; and
in a second direction, a width of an overlapping region between the first shift registers and the first signal line is W11, a width of an overlapping region between the first shift registers and the
second power signal bus is W12, and the second direction intersects whit the first direction, and
wherein W11 < W12.
1. A display panel, comprising:
a driver circuit and a pixel circuit, wherein the driver circuit provides a drive signal for the
pixel circuit;
a light-emitting element, wherein the light-emitting element comprises a first electrode and a second electrode; and
a first power signal bus and a second power signal bus, wherein the first power signal bus is configured to transmit a first power signal V1, the second power signal bus is configured to transmit a second power signal V2, and V1 # V2;
wherein the first power signal bus is connected to the pixel circuit, the pixel circuit is
connected to the first electrode; and
the second power signal bus at least partially overlaps the driver circuit, and the second
power signal bus is not connected to the driver circuit;
wherein the driver circuit comprises a first driver circuit configured to provide a first control signal for the pixel circuit, and the first driver circuit comprises a plurality of stages of first shift registers cascaded with each other in a first direction;
wherein the display panel further comprises a first signal line group connected to the first driver circuit and configured to provide a signal for the first driver circuit, and a first signal line in the first signal line group overlaps a first shift register of the plurality of stages of the first shift registers; and the first signal line group does not comprise the second power signal bus; and
wherein the display panel further comprises an auxiliary connection layer and the driver
circuit further comprises a second driver circuit configured to provide a second control
signal for the pixel circuit;
the auxiliary connection layer is located between a film where the second electrode is
located and a film where the second power signal bus is located, and the second power signal bus is connected to the auxiliary connection layer and is connected to the second electrode through the auxiliary connection layer;
in a second direction, a width of an overlapping region between the first shift register and the first signal line is W11, a width of an overlapping region between the first shift register and the second power signal bus is W12, and the second direction and the first direction intersect, wherein W11<W12;
the second driver circuit comprises a plurality of stages of second shift registers cascaded
with each other in the first direction, the second driver circuit is located on a side of the first driver circuit facing a display region of the display panel, and the second drive circuit is located on a same side of the display region as the first drive circuit; and
in the second direction, a width of an overlapping region between a second shift register of the plurality of stages of the second shift registers and the second power signal bus is W22,
wherein W12 > W22 ≥ 0.
Claim 4 of the present application corresponds to claim 5 of US. Patent No. 12,406,615.
Claim 8 of the present application corresponds to claim 3 of US. Patent No. 12,406,615.
Claim 9 of the present application corresponds to claim 6 of US. Patent No. 12,406,615.
Claim 10 of the present application corresponds to claim 7 of US. Patent No. 12,406,615.
Claim 11 of the present application corresponds to claim 1 of US. Patent No. 12,406,615.
Claim 12 of the present application corresponds to claim 8 of US. Patent No. 12,406,615.
Claim 13 of the present application corresponds to claim 9 of US. Patent No. 12,406,615.
Claim 14 of the present application corresponds to claim 1 of US. Patent No. 12,406,615.
Claim 15 of the present application corresponds to claim 11 of US. Patent No. 12,406,615.
Claim 16 of the present application corresponds to claim 12 of US. Patent No. 12,406,615.
Claim 17 of the present application corresponds to claim 13 of US. Patent No. 12,406,615.
Current Application
US. Patent No. 12,406,615
18. A display panel, comprising:
a driver circuit and a pixel circuit;
a light-emitting element, wherein the light-emitting element comprises a first electrode and a second electrode;
a first power signal bus and a second power signal bus, wherein the first power signal bus is connected to the pixel circuit, the pixel circuit is connected to the first electrode, and the second power signal bus is connected to the second electrode; and
an auxiliary connection layer, wherein the auxiliary connection layer is located between a film where the second electrode is located and a film where the second power signal bus is located, and the auxiliary connection layer is connected to the second electrode and the second power signal bus;
wherein the second power signal bus at least partially overlaps the driver circuit;
wherein the driver circuit comprises a first driver circuit, the first driver circuit is configured to provide a first control signal for the pixel circuit, and the first driver circuit comprises a plurality of stages of first shift registers cascaded with each other in a first direction;
wherein the display panel further comprises a first signal line group, and the first signal line group is connected to the first driver circuit; and in a second direction, a total width of an overlapping region between a signal line in the first signal line group and the first shift registers is WS1, a width of an overlapping region between the first shift registers and the second power signal bus is W12, and the second direction and the first direction intersect, and the second direction intersects whit the first direction, and wherein WS1<W12.
1. A display panel, comprising:
a driver circuit and a pixel circuit, wherein the driver circuit provides a drive signal for the
pixel circuit;
a light-emitting element, wherein the light-emitting element comprises a first electrode and a second electrode; and
a first power signal bus and a second power signal bus, wherein the first power signal bus is configured to transmit a first power signal V1, the second power signal bus is configured to transmit a second power signal V2, and V1 # V2;
wherein the first power signal bus is connected to the pixel circuit, the pixel circuit is
connected to the first electrode; and
the second power signal bus at least partially overlaps the driver circuit, and the second
power signal bus is not connected to the driver circuit;
wherein the driver circuit comprises a first driver circuit configured to provide a first control signal for the pixel circuit, and the first driver circuit comprises a plurality of stages of first shift registers cascaded with each other in a first direction;
wherein the display panel further comprises a first signal line group connected to the first driver circuit and configured to provide a signal for the first driver circuit, and a first signal line in the first signal line group overlaps a first shift register of the plurality of stages of the first shift registers; and the first signal line group does not comprise the second power signal bus; and
wherein the display panel further comprises an auxiliary connection layer and the driver
circuit further comprises a second driver circuit configured to provide a second control
signal for the pixel circuit;
the auxiliary connection layer is located between a film where the second electrode is
located and a film where the second power signal bus is located, and the second power signal bus is connected to the auxiliary connection layer and is connected to the second electrode through the auxiliary connection layer;
in a second direction, a width of an overlapping region between the first shift register and the first signal line is W11, a width of an overlapping region between the first shift register and the second power signal bus is W12, and the second direction and the first direction intersect, wherein W11<W12;
the second driver circuit comprises a plurality of stages of second shift registers cascaded
with each other in the first direction, the second driver circuit is located on a side of the first driver circuit facing a display region of the display panel, and the second drive circuit is located on a same side of the display region as the first drive circuit; and
in the second direction, a width of an overlapping region between a second shift register of the plurality of stages of the second shift registers and the second power signal bus is W22,
wherein W12 > W22 ≥ 0.
7. The display panel according to claim 1, wherein at least one signal line of the first signal line group overlaps a first shift register of the plurality of stages of the first shift registers; and in the second direction, a total width of an overlapping region between the whole of the at least one signal line in the first signal line group and the first shift register is WS1, wherein WS1<W12.
Claim 20 of the present application corresponds to claim 14 of US. Patent No. 12,406,615.
Current Application
US. Patent No. 12,406,615
19. A display device, comprising a display panel which comprises:
a driver circuit and a pixel circuit;
a light-emitting element, wherein the light-emitting element comprises a first electrode and a second electrode;
a first power signal bus and a second power signal bus, wherein the first power signal bus is connected to the pixel circuit, the pixel circuit is connected to the first electrode, and the second power signal bus is connected to the second electrode; and
an auxiliary connection layer, wherein the auxiliary connection layer is located between a film where the second electrode is located and a film where the second power signal bus is located, and the auxiliary connection layer is connected to the second electrode and the second power signal bus;
wherein the second power signal bus at least partially overlaps the driver circuit;
wherein the driver circuit comprises a first driver circuit, the first driver circuit is configured to provide a first control signal for the pixel circuit, and the first driver circuit comprises a plurality of stages of first shift registers cascaded with each other in a first direction;
wherein the display panel further comprises a first signal line group, and the first signal line group is connected to the first driver circuit; and
in a second direction, a width of an overlapping region between the first shift registers and the first signal line is W11, a width of an overlapping region between the first shift registers and the second power signal bus is W12, and the second direction intersects whit the first direction, and
wherein W11 < W12.
1. A display panel, comprising:
a driver circuit and a pixel circuit, wherein the driver circuit provides a drive signal for the
pixel circuit;
a light-emitting element, wherein the light-emitting element comprises a first electrode and a second electrode; and
a first power signal bus and a second power signal bus, wherein the first power signal bus is configured to transmit a first power signal V1, the second power signal bus is configured to transmit a second power signal V2, and V1 # V2;
wherein the first power signal bus is connected to the pixel circuit, the pixel circuit is
connected to the first electrode; and
the second power signal bus at least partially overlaps the driver circuit, and the second
power signal bus is not connected to the driver circuit;
wherein the driver circuit comprises a first driver circuit configured to provide a first control signal for the pixel circuit, and the first driver circuit comprises a plurality of stages of first shift registers cascaded with each other in a first direction;
wherein the display panel further comprises a first signal line group connected to the first driver circuit and configured to provide a signal for the first driver circuit, and a first signal line in the first signal line group overlaps a first shift register of the plurality of stages of the first shift registers; and the first signal line group does not comprise the second power signal bus; and
wherein the display panel further comprises an auxiliary connection layer and the driver
circuit further comprises a second driver circuit configured to provide a second control
signal for the pixel circuit;
the auxiliary connection layer is located between a film where the second electrode is
located and a film where the second power signal bus is located, and the second power signal bus is connected to the auxiliary connection layer and is connected to the second electrode through the auxiliary connection layer;
in a second direction, a width of an overlapping region between the first shift register and the first signal line is W11, a width of an overlapping region between the first shift register and the second power signal bus is W12, and the second direction and the first direction intersect, wherein W11<W12;
the second driver circuit comprises a plurality of stages of second shift registers cascaded
with each other in the first direction, the second driver circuit is located on a side of the first driver circuit facing a display region of the display panel, and the second drive circuit is located on a same side of the display region as the first drive circuit; and
in the second direction, a width of an overlapping region between a second shift register of the plurality of stages of the second shift registers and the second power signal bus is W22,
wherein W12 > W22 ≥ 0.
The primary difference between claim 19 of the current application and the above US Patent pertains to the recitation of “a display device, comprising a display panel” in the current application. A display device may comprise a display panel and some accessory parts such as speakers. It was well known in the art before the effective filing date of the invention to integrate the speakers with the display panel in order to make it easy for the user to use the display device.
Allowable Subject Matter
Claims 2-3 and 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1, 4 and 8-20 would be allowable if a Terminal Disclaimer is filed to overcome the Double Patenting rejections(s) set forth in this Office Action.
The following is an examiner’s statement of reasons for allowance:
None of the prior art, made of record, singularly or in combination, teaches or fairly suggests the features presented in the combined limitations of independent claims 1, 18 and 19, specifically the limitation stated as “wherein the second power signal bus at least partially overlaps the driver circuit; an auxiliary connection layer, wherein the auxiliary connection layer is located between a film where the second electrode is located and a film where the second power signal bus is located, and the auxiliary connection layer is connected to the second electrode and the second power signal bus; in a second direction, a width of an overlapping region between the first shift registers and the first signal line is W11, a width of an overlapping region between the first shift registers and the second power signal bus is W12, and the second direction and the first direction intersect, wherein W11 < W12” of claims 1 and 19; and “wherein the second power signal bus at least partially overlaps the driver circuit; an auxiliary connection layer, wherein the auxiliary connection layer is located between a film where the second electrode is located and a film where the second power signal bus is located, and the auxiliary connection layer is connected to the second electrode and the second power signal bus; in a second direction, a total width of an overlapping region between a signal line in the first signal line group and the first shift registers is WS1, a width of an overlapping region between the first shift registers and the second power signal bus is W12, and the second direction and the first direction intersect, and the second direction intersects whit the first direction, and wherein WS1<W12” of claim 18. The dependent claims 2-17 and 20 are allowed for at least the same reason indicated above.
Kim (US. Pub. No. 2007/0103063) is considered the closest prior art. Kim discloses a display panel comprising a driver circuit and a pixel circuit; a light-emitting element, wherein the light-emitting element comprises a first electrode and second electrode. Kim further discloses a first power signal bus; however, Kim fails to disclose wherein the second power signal bus at least partially overlaps the driver circuit; an auxiliary connection layer, wherein the auxiliary connection layer is located between a film where the second electrode is located and a film where the second power signal bus is located, and the auxiliary connection layer is connected to the second electrode and the second power signal bus; in a second direction, a width of an overlapping region between the first shift registers and the first signal line is W11, a width of an overlapping region between the first shift registers and the second power signal bus is W12, and the second direction and the first direction intersect, wherein W11 < W12 required for claims 1 and 19; and wherein the second power signal bus at least partially overlaps the driver circuit; an auxiliary connection layer, wherein the auxiliary connection layer is located between a film where the second electrode is located and a film where the second power signal bus is located, and the auxiliary connection layer is connected to the second electrode and the second power signal bus; in a second direction, a total width of an overlapping region between a signal line in the first signal line group and the first shift registers is WS1, a width of an overlapping region between the first shift registers and the second power signal bus is W12, and the second direction and the first direction intersect, and the second direction intersects whit the first direction, and wherein WS1<W12 required for claim 18.
Song (US. Pub. No. 2020/0058728) discloses a display panel comprising a driver circuit, a power signal bus, and a light-emitting element; however, Song fails to disclose wherein the second power signal bus at least partially overlaps the driver circuit; an auxiliary connection layer, wherein the auxiliary connection layer is located between a film where the second electrode is located and a film where the second power signal bus is located, and the auxiliary connection layer is connected to the second electrode and the second power signal bus; in a second direction, a width of an overlapping region between the first shift registers and the first signal line is W11, a width of an overlapping region between the first shift registers and the second power signal bus is W12, and the second direction and the first direction intersect, wherein W11 < W12 required for claims 1 and 19; and wherein the second power signal bus at least partially overlaps the driver circuit; an auxiliary connection layer, wherein the auxiliary connection layer is located between a film where the second electrode is located and a film where the second power signal bus is located, and the auxiliary connection layer is connected to the second electrode and the second power signal bus; in a second direction, a total width of an overlapping region between a signal line in the first signal line group and the first shift registers is WS1, a width of an overlapping region between the first shift registers and the second power signal bus is W12, and the second direction and the first direction intersect, and the second direction intersects whit the first direction, and wherein WS1<W12 required for claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US. Pub. No. 2009/0040168 (Liu et al.) is considered as pertinent art as seen in figures 1A-B.
US. Pub. No. 2009/0237329 (Matsuura et al.) is also considered as pertinent art as seen in figure 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAN-YING YANG whose telephone number is (571)272-2211. The examiner can normally be reached Monday-Friday, 8am-5pm, EST.
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/NAN-YING YANG/Primary Examiner, Art Unit 2629
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