DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/8/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6, & 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suzuki et al. (US 20130208026).
As to claim 1, Suzuki discloses a manufacturing method of a display device [abstract & figs. 11-12 & para. 111-113], the method comprising:
transferring a plurality of first light emitting elements (thin film LED 443A) [figs. 9-10 & para. 102] onto a plurality of first pixel electrodes (second contact layer 443f of thin film LED 443A) [fig. 10 & para. 104];
transferring a plurality of second light emitting elements (thin film LED 443B) [figs. 9-10 & para. 102] onto a plurality of second pixel electrodes (second contact layer 443f of thin film LED 443B) [fig. 10 & para. 104], the plurality of second pixel electrodes being spaced apart from the plurality of first pixel electrodes (spacing between second contact layer 443f of thin film LED 443A & second contact layer 443f of thin film LED 443B) [figs. 9-10];
forming a support layer (bridge insulating film 453) [figs. 9-10 & para. 108-109] having a height between the plurality of first light emitting elements and the plurality of second light emitting elements;
forming a conductive pattern (junction wirings 450, 451A, and 451B) [figs. 9-10 & para. 107-109] on the support layer, the conductive pattern having an end electrically connected to one of the plurality of second pixel electrodes (series connected LEDs) [figs. 9-12 & para. 114 & 81];
forming a contact layer (second electrode 443g) [figs. 9-10 & para. 104 & 107] having an end electrically connected to another end of the conductive pattern (series connected LEDs) [figs. 9-12 & para. 114 & 81];
forming a first common electrode (first electrode 443a of thin film LED 443A) [fig. 10 & para. 104] overlapping at least a portion of the plurality of first pixel electrodes and the plurality of first light emitting elements [figs. 9-10]; and
forming a second common electrode (first electrode 443a of thin film LED 443B) [fig. 10 & para. 104] overlapping at least a portion of the second pixel electrodes and the plurality of second light emitting elements [figs. 9-10].
As to claim 2, Suzuki discloses the manufacturing method of claim 1, wherein the support layer overlaps at least a portion of the first common electrode (bridge insulating film 453) [figs. 9-10].
As to claim 4, Suzuki discloses the manufacturing method of claim 1, wherein the support layer includes an organic material (polyimide) [para. 108].
As to claim 6, Suzuki discloses the manufacturing method of claim 1, wherein another end of the contact layer is electrically connected to the first common electrode (series connected LEDs) [figs. 9-12 & para. 114 & 81].
As to claim 7, Suzuki discloses the manufacturing method of claim 1, wherein the first common electrode is electrically connected to one of the plurality of second pixel electrodes through the contact layer and the conductive pattern (series connected LEDs) [figs. 9-12 & para. 114 & 81].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki.
As to claim 5, Suzuki teaches the manufacturing method of claim 1, the conductive pattern (junction wirings 450, 451A, and 451B formed using a combination of photolithography with vapor deposition or sputtering,) [figs. 9-10 & para. 109].
Suzuki further teaches wherein the conductive pattern includes a metal [para. 174].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the conductive pattern of the manufacturing method of the display device of Suzuki, such that the conductive pattern includes a metal, as further taught by Suzuki, to reduce costs of manufacturing by utilizing commonly available conductive materials, as one or ordinary skill in the art would appreciate.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki, in view of Hsieh et al. (US 20220336523).
As to claim 3, Suzuki teaches the manufacturing method of claim 1, wherein the height is higher than heights of ones of the plurality of first light emitting elements and ones of the plurality of second light emitting elements [fig. 10].
Suzuki does not explicitly teach wherein the height is smaller than heights of ones of the plurality of first light emitting elements and ones of the plurality of second light emitting elements.
Hsieh teaches the concept of a manufacturing method of a display device [abstract & fig. 1], that utilizes a support layer (insulation layer INS) [fig. 3 & para. 31] disposed between a plurality of first light emitting elements (first sub-chip 310) [fig. 3 & para. 31] and a plurality of second light emitting elements (second sub-chip 320) [fig. 3 & para. 31] and having a height (bold line of INS) [fig. 3].
Because Suzuki and Hsieh are in the same field of endeavor, i.e., configuration of series connected LED’s for display devices, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to simply substitute the height that is higher than heights of ones of the plurality of first light emitting elements and ones of the plurality of second light emitting elements of the support layer of the manufacturing method of the display device of Suzuki, with a height that is smaller than heights of ones of the plurality of first light emitting elements and ones of the plurality of second light emitting elements, as taught by Hsieh, for the purposes of achieving the predictable result of isolating conductive elements to avoid incorrect electrical connections.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki, in view of Kishimoto et al. (US 20200388661).
As to claim 8, Suzuki teaches the manufacturing method of claim 1 (see claim 1 above).
Suzuki does not explicitly teach wherein the forming the contact layer includes:
forming an organic layer surrounding the plurality of first light emitting elements, the plurality of second light emitting elements, the conductive pattern, and the support layer;
etching the organic layer to form a hole corresponding to the contact layer; and
depositing a conductive material in the hole.
Kishimoto teaches the concept of a manufacturing method for a display device [abstract & figs. 4a & figs. 5a-5e], wherein forming a contact layer (source contact 25b) [figs. 4a & 5e] utilizes:
forming an organic layer (organic insulating layer 32) [figs. 5b-5c & para. 79-80] surrounding and planarizing manufactured component elements [figs. 5b-5c & para. 79-80];
etching the organic layer to form a hole corresponding to the contact layer (contact hole 30a formed via etching) [fig. 5d & para. 81]; and
depositing a conductive material in the hole (source contact 25b) [fig. 5e & para 82].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the forming of the contact layer of the manufacturing method of Suzuki, such that forming the contact layer includes: forming an organic layer surrounding the plurality of first light emitting elements, the plurality of second light emitting elements, the conductive pattern, and the support layer; etching the organic layer to form a hole corresponding to the contact layer; and depositing a conductive material in the hole, as taught by Kishimoto, to improve image quality by improving luminance uniformity, as taught by Kishimoto [para. 80].
As to claim 9, Suzuki teaches the manufacturing method of claim 1 (see claim 1 above).
Suzuki does not explicitly teach wherein the forming the contact layer includes:
forming an inorganic layer on the conductive pattern;
forming an organic layer surrounding the plurality of first light emitting elements, the plurality of second light emitting elements, the inorganic layer, the conductive pattern, and the support layer;
etching the inorganic layer to form a hole corresponding to the contact layer; and
depositing a conductive material in the hole.
Kishimoto teaches the concept of a manufacturing method for a display device [abstract & figs. 4a & figs. 5a-5e], wherein forming a contact layer (source contact 25b) [figs. 4a & 5e] utilizes:
forming an inorganic layer (first inorganic insulating layer 31) [figs. 5b-5c & para. 79-80] on a conductive pattern (second conductor layer 25a) [figs. 5a-5c & para. 77];
forming an organic layer (organic insulating layer 32) [figs. 5b-5c & para. 79-80] surrounding and planarizing manufactured component elements [figs. 5b-5c & para. 79-80];
etching the inorganic layer to form a hole corresponding to the contact layer (contact hole 30a formed via etching) [fig. 5d & para. 81]; and
depositing a conductive material in the hole (source contact 25b) [fig. 5e & para 82].
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the forming of the contact layer of the manufacturing method of Suzuki, such that forming the contact layer includes: forming an inorganic layer on the conductive pattern; forming an organic layer surrounding the plurality of first light emitting elements, the plurality of second light emitting elements, the inorganic layer, the conductive pattern, and the support layer; etching the inorganic layer to form a hole corresponding to the contact layer; and depositing a conductive material in the hole, as taught by Kishimoto, to improve image quality by improving luminance uniformity, as taught by Kishimoto [para. 80].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 & 6-8 of U.S. Patent No. 12387660. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the instant application are claiming common subject matter.
Claims of Instant Application
Claims of US 12387660
1
1
2
2
3
3
4
4
5
6
6
1
7
7
8
1
9
1 & 8
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US 20110062465).
Hsu (US 20110140078).
Shim et al. (US 20220149128).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID TUNG whose telephone number is (571)270-3385. The examiner can normally be reached Monday-Friday; 10:00AM - 6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at (571)-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID TUNG/Primary Examiner, Art Unit 2622
Prosecution Insights