DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-5 and 7-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-14 and 17-20 of U.S. Patent No. US 12,406,606. Although the claims at issue are not identical, they are not patentably distinct from each other because
Instant Application
U.S. Patent No. US 12,406,606
1. A display apparatus comprising:
a display panel comprising a pixel;
a gate driver configured to provide a gate signal to the pixel;
a data driver configured to provide a data voltage to the pixel; and
an emission driver configured to provide an emission signal to the pixel,
wherein the pixel is configured to emit light based on a data writing gate signal, a data initialization gate signal, a compensation gate signal, the emission signal and the data voltage,
wherein the data initialization gate signal has an active pulse in a first period,
wherein the compensation gate signal has an active pulse in the first period, wherein the data writing gate signal has an active pulse in the first period,
wherein the emission signal has an active period in the first period,
wherein the data initialization gate signal does not have the active pulse in a second period subsequent to the first period,
wherein the compensation gate signal does not have the active pulse in the second period, and
wherein the emission signal has the active period in the second period.
2. The display apparatus of claim 1, wherein at least one of the data initialization gate signal and the compensation gate signal does not have the active pulse in a third period subsequent to the second period,
wherein the data writing gate signal has the active pulse in the third period, and wherein the emission signal has the active period in the third period.
17. A display apparatus comprising:
a display panel comprising a pixel;
a gate driver configured to provide a gate signal to the pixel;
a data driver configured to provide a data voltage to the pixel; and
an emission driver configured to provide an emission signal to the pixel,
wherein the pixel is configured to emit a light based on a data writing gate signal, a data initialization gate signal, a compensation gate signal, the emission signal and the data voltage,
wherein the data initialization gate signal has an active pulse in a first period,
wherein the compensation gate signal has an active pulse in the first period, wherein the data writing gate signal has an active pulse in the first period,
wherein the emission signal has an active period in the first period,
wherein the data initialization gate signal does not have the active pulse in a second period subsequent to the first period,
wherein the compensation gate signal does not have the active pulse in the second period,
wherein the data writing gate signal does not have the active pulse in the second period,
wherein the emission signal has the active period in the second period,
wherein at least one of the data initialization gate signal and the compensation gate signal does not have the active pulse in a third period subsequent to the second period,
wherein the data writing gate signal has the active pulse in the third period, and wherein the emission signal has the active period in the third period.
3. The display apparatus of claim 2, wherein the data initialization gate signal does not have the active pulse in the third period, and wherein the compensation gate signal does not have the active pulse in the third period.
4. The display apparatus of claim 2, wherein the data initialization gate signal has the active pulse in the third period, and wherein the compensation gate signal does not have the active pulse in the third period.
5. The display apparatus of claim 2, wherein the data initialization gate signal does not have the active pulse in the third period, and wherein the compensation gate signal has the active pulse in the third period.
7. The display apparatus of claim 6, wherein, when the frequency of the data writing gate signal is reduced in the variable frequency driving, the frequency of at least one of the data initialization gate signal and the compensation gate signal is reduced.
8. The display apparatus of claim 6, wherein a frequency of the emission signal is greater than the frequency of the data writing gate signal.
9. The display apparatus of claim 6, wherein a frequency of the data initialization gate signal is less than the frequency of the data writing gate signal, and wherein a frequency of the compensation gate signal is less than the frequency of the data writing gate signal.
10. The display apparatus of claim 6, wherein a frequency of the compensation gate signal is less than the frequency of the data writing gate signal.
11. The display apparatus of claim 10, wherein a frequency of the data initialization gate signal is substantially the same as the frequency of the data writing gate signal.
12. The display apparatus of claim 10, wherein a frequency of the emission signal is greater than the frequency of the data writing gate signal, and wherein a frequency of the data initialization gate signal is substantially the same as the frequency of the emission signal.
13. The display apparatus of claim 6, wherein a frequency of the data initialization gate signal is less than the frequency of the data writing gate signal, and wherein a frequency of the compensation gate signal is substantially the same as the frequency of the data writing gate signal.
14. The display apparatus of claim 1, wherein the pixel comprises: a light emitting element; a first transistor configured to apply a driving current to the light emitting element; and a second transistor configured to write the data voltage to a storage capacitor, and wherein the data writing gate signal is applied to a control electrode of the second transistor.
15. The display apparatus of claim 14, wherein the pixel further comprises a third transistor connected between a control electrode of the first transistor and a second electrode of the first transistor, and wherein the compensation gate signal is applied to a control electrode of the third transistor.
16. The display apparatus of claim 15, wherein the pixel further comprises a fifth transistor configured to apply a reference voltage to a second electrode of the second transistor, and wherein the compensation gate signal is applied to a control electrode of the fifth transistor.
17. The display apparatus of claim 14, wherein the pixel further comprises a fourth transistor configured to apply an initialization voltage to a control electrode of the first transistor, andwherein the data initialization gate signal is applied to a control electrode of the fourth transistor.
18. The display apparatus of claim 1, wherein the pixel comprises:
a first transistor including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node;
a second transistor including a control electrode configured to receive the data writing gate signal, a first electrode configured to receive the data voltage and a second electrode connected to a fourth node;
a third transistor including a control electrode configured to receive the compensation gate signal, a first electrode connected to the first node and a second electrode connected to the third node;
a fourth transistor including a control electrode configured to receive the data initialization gate signal, a first electrode configured to receive an initialization voltage and a second electrode connected to the first node;
a fifth transistor including a control electrode configured to receive the compensation gate signal, a first electrode configured to receive a reference voltage and a second electrode connected to the fourth node;
a sixth transistor including a control electrode configured to receive a second emission signal, a first electrode connected to the third node and a second electrode connected to an anode electrode of a light emitting element;
a seventh transistor including a control electrode configured to receive a light emitting element initialization gate signal, a first electrode configured to receive the initialization voltage and a second electrode connected to the anode electrode of the light emitting element;
an eighth transistor including a control electrode configured to receive the light emitting element initialization gate signal, a first electrode configured to receive a bias voltage and a second electrode connected to the second node;
a ninth transistor including a control electrode configured to receive a first emission signal, a first electrode configured to receive a high power voltage and a second electrode connected to the second node;
a hold capacitor including a first electrode configured to receive the high power voltage and a second electrode connected to the fourth node; and
a storage capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node, wherein
the light emitting element includes the anode electrode and a cathode electrode configured to receive a low power voltage.
19. The display apparatus of claim 18, wherein the data initialization gate signal has an active pulse in a data initialization period,
wherein the compensation gate signal has an inactive pulse in the data initialization period,
wherein the data writing gate signal has an inactive level in the data initialization period,
wherein the data initialization gate signal has an inactive level in a compensation period,
wherein the compensation gate signal has an active pulse in the compensation period,
wherein the data writing gate signal has the inactive level in the compensation period,
wherein the data initialization gate signal has the inactive level in a data writing period,
wherein the compensation gate signal has the inactive level in the data writing period, and
wherein the data writing gate signal has an active pulse in the data writing period.
18. The display apparatus of claim 17, wherein the data initialization gate signal does not have the active pulse in the third period, and wherein the compensation gate signal does not have the active pulse in the third period.
19. The display apparatus of claim 17, wherein the data initialization gate signal has the active pulse in the third period, and wherein the compensation gate signal does not have the active pulse in the third period.
20. The display apparatus of claim 17, wherein the data initialization gate signal does not have the active pulse in the third period, and wherein the compensation gate signal has the active pulse in the third period.
2. The display apparatus of claim 1, wherein, when the frequency of the data writing gate signal is reduced in the variable frequency driving, the frequency of at least one of the data initialization gate signal and the compensation gate signal is reduced.
3. The display apparatus of claim 1, wherein a frequency of the emission signal is greater than the frequency of the data writing gate signal.
4. The display apparatus of claim 1, wherein a frequency of the data initialization gate signal is less than the frequency of the data writing gate signal, and wherein a frequency of the compensation gate signal is less than the frequency of the data writing gate signal.
5. The display apparatus of claim 1, wherein a frequency of the compensation gate signal is less than the frequency of the data writing gate signal.
6. The display apparatus of claim 5, wherein a frequency of the data initialization gate signal is substantially the same as the frequency of the data writing gate signal.
7. The display apparatus of claim 5, wherein a frequency of the emission signal is greater than the frequency of the data writing gate signal, and wherein a frequency of the data initialization gate signal is substantially the same as the frequency of the emission signal.
8. The display apparatus of claim 1, wherein a frequency of the data initialization gate signal is less than the frequency of the data writing gate signal, and wherein a frequency of the compensation gate signal is substantially the same as the frequency of the data writing gate signal.
9. The display apparatus of claim 1, wherein the pixel comprises: a light emitting element; a first transistor configured to apply a driving current to the light emitting element; and a second transistor configured to write the data voltage to a storage capacitor, and wherein the data writing gate signal is applied to a control electrode of the second transistor.
10. The display apparatus of claim 9, wherein the pixel further comprises a third transistor connected between a control electrode of the first transistor and a second electrode of the first transistor, and wherein the compensation gate signal is applied to a control electrode of the third transistor.
11. The display apparatus of claim 10, wherein the pixel further comprises a fifth transistor configured to apply a reference voltage to a second electrode of the second transistor, and wherein the compensation gate signal is applied to a control electrode of the fifth transistor.
12. The display apparatus of claim 9, wherein the pixel further comprises a fourth transistor configured to apply an initialization voltage to a control electrode of the first transistor, and wherein the data initialization gate signal is applied to a control electrode of the fourth transistor.
13. The display apparatus of claim 1, wherein the pixel comprises:
a first transistor including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node;
a second transistor including a control electrode configured to receive the data writing gate signal, a first electrode configured to receive the data voltage and a second electrode connected to a fourth node;
a third transistor including a control electrode configured to receive the compensation gate signal, a first electrode connected to the first node and a second electrode connected to the third node;
a fourth transistor including a control electrode configured to receive the data initialization gate signal, a first electrode configured to receive an initialization voltage and a second electrode connected to the first node;
a fifth transistor including a control electrode configured to receive the compensation gate signal, a first electrode configured to receive a reference voltage and a second electrode connected to the fourth node;
a sixth transistor including a control electrode configured to receive a second emission signal, a first electrode connected to the third node and a second electrode connected to an anode electrode of a light emitting element;
a seventh transistor including a control electrode configured to receive a light emitting element initialization gate signal, a first electrode configured to receive the initialization voltage and a second electrode connected to the anode electrode of the light emitting element;
an eighth transistor including a control electrode configured to receive the light emitting element initialization gate signal, a first electrode configured to receive a bias voltage and a second electrode connected to the second node;
a ninth transistor including a control electrode configured to receive a first emission signal, a first electrode configured to receive a high power voltage and a second electrode connected to the second node;
a hold capacitor including a first electrode configured to receive the high power voltage and a second electrode connected to the fourth node;
a storage capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node; and
the light emitting element including the anode electrode and a cathode electrode configured to receive a low power voltage.
14. The display apparatus of claim 13, wherein the data initialization gate signal has an active pulse in a data initialization period,
wherein the compensation gate signal has an inactive pulse in the data initialization period,
wherein the data writing gate signal has an inactive level in the data initialization period,
wherein the data initialization gate signal has an inactive level in a compensation period,
wherein the compensation gate signal has an active pulse in the compensation period,
wherein the data writing gate signal has the inactive level in the compensation period,
wherein the data initialization gate signal has the inactive level in a data writing period,
wherein the compensation gate signal has the inactive level in the data writing period, and
wherein the data writing gate signal has an active pulse in the data writing period.
20. An electronic apparatus comprising:
a display panel comprising a pixel;
a gate driver configured to provide a gate signal to the pixel;
a data driver configured to provide a data voltage to the pixel;
an emission driver configured to provide an emission signal to the pixel;
a driving controller configured to control the gate driver, the data driver and the emission driver; and a processor configured to supply input image data and an input control signal to the driving controller,
wherein the pixel is configured to emit light based on a data writing gate signal, a data initialization gate signal, a compensation gate signal, the emission signal and the data voltage,
wherein the data initialization gate signal has an active pulse in a first period,
wherein the compensation gate signal has an active pulse in the first period,
wherein the data writing gate signal has an active pulse in the first period,
wherein the emission signal has an active period in the first period,
wherein the data initialization gate signal does not have the active pulse in a second period subsequent to the first period,
wherein the compensation gate signal does not have the active pulse in the second period, and
wherein the emission signal has the active period in the second period.
2. The display apparatus of claim 1, wherein at least one of the data initialization gate signal and the compensation gate signal does not have the active pulse in a third period subsequent to the second period,
wherein the data writing gate signal has the active pulse in the third period, and wherein the emission signal has the active period in the third period.
17. A display apparatus comprising:
a display panel comprising a pixel;
a gate driver configured to provide a gate signal to the pixel;
a data driver configured to provide a data voltage to the pixel; and
an emission driver configured to provide an emission signal to the pixel,
wherein the pixel is configured to emit a light based on a data writing gate signal, a data initialization gate signal, a compensation gate signal, the emission signal and the data voltage,
wherein the data initialization gate signal has an active pulse in a first period,
wherein the compensation gate signal has an active pulse in the first period,
wherein the data writing gate signal has an active pulse in the first period,
wherein the emission signal has an active period in the first period,
wherein the data initialization gate signal does not have the active pulse in a second period subsequent to the first period,
wherein the compensation gate signal does not have the active pulse in the second period,
wherein the data writing gate signal does not have the active pulse in the second period,
wherein the emission signal has the active period in the second period,
wherein at least one of the data initialization gate signal and the compensation gate signal does not have the active pulse in a third period subsequent to the second period,
wherein the data writing gate signal has the active pulse in the third period, and wherein the emission signal has the active period in the third period.
Note that claim 20 of U.S. Patent No. US 12,406,606 does not expressly recite a driving controller configured to control the gate driver, the data driver and the emission driver; and a processor configured to supply input image data and an input control signal to the driving controller. However, it is well known for a display panel apparatus to have a driving controller configured to control the gate driver, the data driver and the emission driver; and a processor configured to supply input image data and an input control signal to the driving controller. Also, U.S. Patent No. US 12,406,606 teaches these limitations in the specification.
Therefore, the instant Application claim is broader in every aspect than the patent claim and is therefore an obvious variant thereof. Although the conflicting claims are not identical, they are not patentability distinct from each other because the instant Application claim is generic to all that is recited in the above patent claim. The more specific anticipates the broader (see In re Goodman – 29 USPQ2d 2010), also see Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2d, 189 and Miller v. Eagle Mfg. Co., 151 U.S. 186 1894). Therefore, the instant claim is anticipated by the above patent claim.
Reasons for Allowance
4. Claims 1-20 will be allowable when there is no double patenting rejection.
5. The following is an examiner’s statement of reasons for allowance:
The subject matter of the independent claims could either not be found or was not suggested in the prior art of record.
Regarding claim 1, the closet prior art Kim (US 20210319755) teaches a display apparatus (Fig. 13(300)) comprising:
a display panel (Fig. 13(310)) comprising a pixel (Fig. 13(PX)), [0094]);
a gate driver (Fig. 13(330): scan driver) configured to provide a gate signal to the pixel ([0096]);
a data driver (Fig. 13(320)) configured to provide a data voltage to the pixel ([0095]); and
an emission driver (Fig. 13(340)) configured to provide an emission signal to the pixel ([0097]),
wherein the pixel is configured to emit light based on a data writing gate signal, a data initialization gate signal, a compensation gate signal, the emission signal and the data voltage (Figs. 4, 10, 13),
wherein the compensation gate signal has an active pulse in the first period (Figs. 4, 10, 13),
wherein the data writing gate signal has an active pulse in the first period (Figs. 4, 10, 13),
wherein the emission signal has an active period in the first period (Figs. 4, 10, 13),
wherein the data initialization gate signal does not have the active pulse in a second period subsequent to the first period (Figs. 4, 10, 13),
wherein the data writing gate signal does not have the active pulse in the second period (Figs. 4, 10, 13),
wherein the emission signal has the active period in the second period (Figs. 4, 10, 13), and
wherein the data writing gate signal has the active pulse in the third period (Figs. 4, 10, 13).
The subject matter not found was “a display apparatus comprising: … wherein the data initialization gate signal has an active pulse in a first period, … and wherein the emission signal has the active period in the third period”, in combination with the other elements (or steps) of the brace and method recited in the claim 1. Same explanation applies claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AFROZA Y CHOWDHURY whose telephone number is (571)270-1543. The examiner can normally be reached M-F 9am-5pm.
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/AFROZA CHOWDHURY/Primary Examiner, Art Unit 2628
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