DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9, 11-16 and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-14, 16 and 18-19 of U.S. Patent No. US 12,399,819 B2 (‘819) because claims 11-14, 16 and 18-19 of ‘819 contains every element of claims 1-9, 11-16 and 18-20 of the instant application and as such anticipates claims 1-9, 11-16 and 18-20 of the instant application.
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berq, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Instant Application
‘819
1. An apparatus, comprising:
a number of memory devices within a memory system; and
a controller coupled to the number of memory devices and configured to:
configure the memory system with a first set of operating characteristics corresponding to a first thermal voltage model;
select a second thermal voltage model based on a monitored operation of the memory system;
configure the memory system with a selected second set of operating characteristics corresponding to a second thermal voltage model based on a monitoring of the memory system while configured with the first set of operating characteristics; and
write data to the memory system while configured with the second set of operating characteristics.
16. A system, comprising:
memory components [within the system including memory (i.e., memory system)]
and a processing device [interpreted as a controller] coupled to the memory components, wherein the processing device is configured to:
write data to the memory components configured with a first set of operating characteristics corresponding to a first thermal voltage model for a period of time subsequent to a power-on event associated with the system;
monitor operational temperatures of at least one of the memory components during the period of time; subsequent to elapse of the period of time, select a second thermal voltage model based on the monitored operational temperatures,
wherein a second set of operating characteristics that correspond to the second thermal voltage model includes an upper operational temperature that is less than an upper operational temperature in the first thermal voltage model, a lowest operational temperature that is higher than a lowest operational temperature in the first thermal voltage model, or both; configure the memory system with the second set of operating characteristics corresponding to the second thermal voltage model;
and write data to components configured with the second set of operating characteristics.
2. The apparatus of claim 1, wherein the controller is configured to configure the memory system with the first set of operating characteristics responsive to a power-on event of the memory system.
16…wherein the processing device is configured to: write data to the memory components configured with a first set of operating characteristics corresponding to a first thermal voltage model for a period of time subsequent to a power-on event associated with the system…
3. The apparatus of claim 2, wherein the controller is configured to monitor operation of the memory system for a predetermined period of time beginning from the power-on event.
16…monitor operational temperatures of at least one of the memory components during the period of time… [i.e., where that period of time is subsequent to a power-on event associated with the system (beginning from the power-on event)]
4. The apparatus of claim 3, wherein the controller is configured to, subsequent to the predetermined period of time, select the second thermal voltage model based on the monitored operation of the memory system.
16… subsequent to elapse of the period of time, select a second thermal voltage model based on the monitored operational temperatures…
5. The apparatus of claim 1, wherein the second thermal voltage model includes at least one operational temperature that is different than a corresponding operational temperature in the first thermal voltage model.
16… wherein a second set of operating characteristics that correspond to the second thermal voltage model includes an upper operational temperature that is less than an upper operational temperature in the first thermal voltage model, a lowest operational temperature that is higher than a lowest operational temperature in the first thermal voltage model, or both…
6. The apparatus of claim 1, wherein an uppermost operational temperature in the second thermal voltage model is less than an uppermost operational temperature in the first thermal voltage model.
16… wherein a second set of operating characteristics that correspond to the second thermal voltage model includes an upper operational temperature that is less than an upper operational temperature in the first thermal voltage model, a lowest operational temperature that is higher than a lowest operational temperature in the first thermal voltage model, or both…
7. The apparatus of claim 6, wherein a lowermost operational temperature in the second thermal voltage model is higher than a lowermost operational temperature in the first thermal voltage model.
16… wherein a second set of operating characteristics that correspond to the second thermal voltage model includes an upper operational temperature that is less than an upper operational temperature in the first thermal voltage model, a lowest operational temperature that is higher than a lowest operational temperature in the first thermal voltage model, or both…
8. The apparatus of claim 1, wherein the monitoring of the memory system while configured with the first set of operating characteristics includes monitoring operational temperatures of the memory system.
…monitor operational temperatures of at least one of the memory components during the period of time…
9. The apparatus of claim 1, wherein the second set of operating characteristics includes at least one operational characteristic that is different than a corresponding operational characteristic in the first set of operating characteristics.
16… wherein a second set of operating characteristics that correspond to the second thermal voltage model includes an upper operational temperature that is less than an upper operational temperature in the first thermal voltage model, a lowest operational temperature that is higher than a lowest operational temperature in the first thermal voltage model, or both…
11. A method, comprising:
configuring a memory system with a first set of operating characteristics corresponding to a first thermal voltage model;
writing data to the memory system configured with the first set of operating characteristics for a period of time;
monitoring an operational temperature of the memory system for the period of time;
subsequently to the period of time, selecting a second thermal voltage model based on the monitoring of the operational temperature;
configuring the memory system with a second set of operating characteristics corresponding the second thermal voltage model; and
writing data to the memory system configured with the second set of operating characteristics.
11. An apparatus, comprising: a processing device configured to: responsive to an occurrence of a power-on event associated with a memory system,
configure the memory system with a first set of operating characteristics corresponding to a first thermal voltage model;
write data to memory system configured with the first set of operating characteristics for a period of time;
monitor an operational temperature of the memory system for the period of time;
subsequent to elapse of the period of time, select a second thermal voltage model based on the monitored operational temperature;
configure the memory system with a second set of operating characteristics corresponding the second thermal voltage model; and
write data to the memory system configured with the second set of operating characteristics.
12. The method of claim 11, wherein a difference between an uppermost operational temperature and a lowermost operational temperature in the first thermal voltage model is different than a difference between an uppermost operational temperature and a lowermost operational temperature in the second thermal voltage.
12. The apparatus of claim 11, wherein a difference between an upper operational temperature and a lower operational temperature in the first thermal voltage model is equal to a first value.
13. The apparatus of claim 12, wherein a difference between an upper operational temperature and a lower operational temperature in the second thermal voltage model is equal to a second value that is less than the first value.
13. The method of claim 11, wherein the method includes subsequently reconfiguring the memory system with the first set of operating characteristics responsive to the memory system experiencing a temperature that exceeds a threshold temperature.
14. The apparatus of claim 13, wherein the controller is configured to revert the memory system configured with the second set of operating characteristics to the first set of operating characteristics responsive to: the memory system experiencing a temperature that exceeds a threshold temperature; or the memory system experiencing a bit error rate that that exceed a bit error rate threshold.
14. The method of claim 11, wherein the method includes subsequently reconfiguring the memory system with the first set of operating characteristics responsive to the memory system experiencing a bit error rate that that exceeds a bit error rate threshold.
14. The apparatus of claim 13, wherein the controller is configured to revert the memory system configured with the second set of operating characteristics to the first set of operating characteristics responsive to: the memory system experiencing a temperature that exceeds a threshold temperature; or the memory system experiencing a bit error rate that that exceed a bit error rate threshold.
15. An apparatus, comprising:
a memory component configured with a first set of operating characteristics corresponding to a first thermal voltage model;
and a processing device coupled to the memory component and configured to:
write data to the memory component configured with the first set of operating characteristics for a period of time;
monitor an operational temperature of the memory component during the period of time;
based on the monitoring of the operation temperature, configure the memory system with a selected second set of operating characteristics corresponding to a second thermal voltage model;
and write data to the memory component while configured with the second set of operating characteristics.
16. A system, comprising:
…memory components configured with a first set of operating characteristics corresponding to a first thermal voltage model for a period…
…a processing device coupled to the memory components, wherein the processing device is configured to…
write data to the memory components configured with a first set of operating characteristics corresponding to a first thermal voltage model for a period of time subsequent to a power-on event associated with the system;
monitor operational temperatures of at least one of the memory components during the period of time;
subsequent to elapse of the period of time, select a second thermal voltage model based on the monitored operational temperatures, wherein a second set of operating characteristics that correspond to the second thermal voltage model includes an upper operational temperature that is less than an upper operational temperature in the first thermal voltage model, a lowest operational temperature that is higher than a lowest operational temperature in the first thermal voltage model, or both; configure the memory system with the second set of operating characteristics corresponding to the second thermal voltage model; and
write data to components configured with the second set of operating characteristics.
16. The apparatus of claim 15, wherein the second set of operating characteristics that correspond to the second thermal voltage model includes an uppermost operational temperature that is less than an uppermost operational temperature in the first thermal voltage model.
16… wherein a second set of operating characteristics that correspond to the second thermal voltage model includes an upper operational temperature that is less than an upper operational temperature in the first thermal voltage model, a lowest operational temperature that is higher than a lowest operational temperature in the first thermal voltage model, or both…
18. The apparatus of claim 15, wherein the apparatus comprises a mobile system.
18. The system of claim 16, wherein the system is a mobile system.
19. The apparatus of claim 15, wherein the processing device is configured to:
write the data to the memory component while configured with the second set of operating characteristics for an additional period of time;
monitor the operational temperature of the memory component during the additional period of time;
subsequent to the additional period of time, configure the memory component with a third set operating characteristics corresponding to a third thermal voltage model.
19. The system of claim 16, wherein the processing device is configured to:
write the data to memory system with the second set of operating characteristics for an additional period of time;
monitor an operational temperatures of the memory system during the additional period of time;
subsequent to elapse of the additional period of time, configure the memory system with a nth set of operating characteristics corresponding to a nth thermal voltage model; and write data to memory system with the third set of operating characteristics.
20. The apparatus of claim 15, wherein the processing device is configured to initiate the monitoring responsive to a power-on event.
16…write data to the memory components configured with a first set of operating characteristics corresponding to a first thermal voltage model for a period of time subsequent to a power-on event associated with the system; monitor operational temperatures of at least one of the memory components during the period of time…
Claims 10 and 17 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of ‘819 in view of US Patent Application Publication US 2015/0092488 A1 (Wakchaure).
Regarding claim 10:
The apparatus of claim 1 is made obvious by claim 16 of ‘819 as applied in the rejection of claim 1 above.
Claim 16 of ‘819 does not explicitly disclose, but Wakchaure teaches:
wherein the at least one operational characteristic that is different is an amount of read latency, a program/erase (P/E) cycle time, or both (by teaching that profile trim parameters include array operation timeouts [0033], and the slower program trims for trim profile B causes program performance impacts of slower program times [0033], and the read voltage settings change read performance and read latency and are different for the different trim profiles [0020-0022] [0030-0035]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the configuration with the first set of operating characteristics corresponding to the first thermal voltage model of claim 16 of ‘819 to include trim parameters that can use slower program times for higher temperatures or change the read voltage settings to affect read performance and latency as taught by Wakchaure in [0030-0035].
One of ordinary skill in the art would have been motivated to make this modification because adjusting the trims including read levels and others can allow the device to operate with optimal parameters for different temperature conditions and can help improve read performance by reducing ECC triggers, improve data retention margins, and increase cycling capability as taught by Wakchaure in [0024] [0032] [0035] [0051-0054].
Regarding claim 17:
The apparatus of claim 15 is made obvious by claim 16 of ‘819 as applied in the rejection of claim 15 above.
Claim 16 of ‘819 does not explicitly disclose, but Wakchaure teaches:
wherein the apparatus comprises a solid state drive (SSD) (by teaching a plurality of memory devices connected to a controller and where the controller applies different configurations to the memory devices depending can be incorporated into an SSD [0012-0013] [0015] [0018]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system including the memory components and the processing device configured to perform the functions of claim 16 of ‘819 to be embodied by an SSD because it would have only required the combination of known elements according to known methods to yield predictable results. For example, claim 16 of ‘819 does not teach that the memory components or processing device are incorporated into an SSD, but Wakchaure teaches that analogous memory devices and processing devices performing analogous functions can be incorporated into an SSD. Accordingly, one of ordinary skill in the art could have combined the memory components and processing device with the functionality as disclosed in claim 16 of ‘819 into the form factor of an SSD as taught by Wakchaure according to known methods and the results would have been predictable.
One of ordinary skill in the art would have been motivated to make this modification because adjusting the trims including read levels and others can allow the device to operate with optimal parameters for different temperature conditions and can help improve read performance by reducing ECC triggers, improve data retention margins, and increase cycling capability as taught by Wakchaure in [0024] [0032] [0035] [0051-0054].
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1 recites, “a second thermal voltage model” after previously reciting “a second thermal voltage model”, which as best understood by the Examiner in light of the specification, should be amended to recite “[[a]]the second thermal voltage model”.
Claim 11 recites, “operating characteristics corresponding the second thermal voltage model”, which as best understood by the Examiner in light of the specification, should be amended to recite “operating characteristics corresponding to the second thermal voltage model”.
Claim 12 recites, “second thermal voltage.”, which as best understood by the Examiner in light of the specification, should be amended to recite “second thermal voltage model.”
Claim 14 recites, “that that” which as best understood by the Examiner in light of the specification, should be amended to recite “that
Claim 15 recites, “the memory system”, which as best understood by the Examiner in light of the specification, should be amended to recite “the memory component”.
Claim 19 recites, “a third set operating characteristics”, which as best understood by the Examiner in light of the specification, should be amended to recite “a third set of operating characteristics”.
Claims 2-10, 12-14 and 16-20 are objected to for failing to cure the deficiencies of a base claim from which they depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 4:
Claim 4 recites “the monitored operation of the memory system”. However, claim 1 recites “based on a monitored operation of the memory system” and claim 3 recites that the controller is configured to “monitor operation of the memory system”. Accordingly, the antecedent basis of “the monitored operation of the memory system” recited in claim 4 is unclear as it could refer to either of the previous recitations in the alternative or as a combination. The Examiner therefore suggests clarifying if the controller configured to “monitor operation of the memory system for a predetermined period of time” in claim 3 is the same “monitored operation” of claim 1 and furthermore, whether it relates to “based on a monitoring of the memory system while configured with the first set of operation characteristics” as also recited in claim 1. For the purposes of examination, the examiner will interpret the limitation as any monitored operation.
Regarding claim 10:
Claim 10 recites, “the at least one operational characteristic that is different”. However, there is insufficient antecedent basis for this limitation in the claims. Accordingly, the scope of the claim cannot be determined, and the claim is indefinite. The Examiner supposes this claim was meant to depend from claim 9. Accordingly, for the purposes of examination, the Examiner will interpret claim 10 as depending from claim 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 8-11, 13-15, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication US 2015/0092488 A1 (Wakchaure) in view of US Patent No. US 10,379,739 B1 (Bazarsky).
Regarding claim 1 and analogous claims 11 and 15:
Wakchaure discloses:
An apparatus, comprising: a number of memory devices within a memory system; and (an SSD includes one or more NVM memories (152) [0018])
a controller coupled to the number of memory devices and configured to (the SSD also includes controller logic (150) coupled to the memories (152), where the logic may be provided by one of the processors (102) (120) [0018] [Fig. 1])
configure the memory system with a first set of operating characteristics based on a first set of parameters (the controller (150) may have access to temperature readings of the drive and is configured to load a trim profile (first thermal voltage model) to the SSD based on the measured temperatures. The trim profile includes pre-defined settings for NAND parameters including WL/BL voltages during array operations including program operations [0021-0022]. Trim profile A or trim profile B may be applied to the NAND (302) [0019-0021] [0024] [Fig. 3]. [Figs. 2A-2B] show how operating temperature affects RBER and post retention RBER, such that the trim profiles are optimized for the different operating conditions that affect the performance of the NAND based on temperature and time [0029-0035]).
select a second set of parameters based on a monitored operation of the memory system (when the temperature reaches Tc (306) or falls below Tc (310), the controller logic may select trim profile B or trim profile A instead of the trim profile currently being used [0021] [0024-0025] [Fig. 3] (a monitored operation is interpreted as a monitored temperature per Applicant’s Specification [0073]). The trim profile B is for higher temperatures and therefore reflects the trade-off where NAND reliability is prioritized as program disturb is worse at higher temperatures and read window budget margin can be increased as reliability is worse at higher temperatures rather than trim profile A which is used most of the time for normal operations [0020-0022] [0027-0035]).
configure the memory system with a selected second set of operating characteristics corresponding to the second set of parameters based on a monitoring of the memory system while configured with the first set of operating characteristics; and (by teaching that the temperature is monitored while operating with trim profile A (306) or trim profile B (310) and the system may continue using trim profile A (304) or B (312) unless the monitored temperature reaches Tc (306 – No) or drops below TC (310 -No) at which point, trim profile B may be selected (308) and used (312) or A may be selected (302) and used (304), which includes the parameters for operating the NAND memory system that will continue to be used so long as the temp does not decrease below Tc (310 – NO) or increase above Tc (306 – No) [Fig. 3] [0024-0025]).
write data to the memory system while configured with the second set of operating characteristics (trim profile B or A remains loaded as is used to operate the NAND (312) (304), which includes settings such as WL and BL voltages for performing program operations at the higher temperatures associated with temps above Tc or for lower temps below Tc [0021-0022] [0030] [0033]).
Wakchaure does not explicitly disclose, but Bazarsky teaches:
That a set of operating parameters may be obtained from a selected thermal voltage model including a first thermal voltage model and a second thermal voltage model (by teaching that operating parameters establish parameters used to read or write from a memory cell or group of memory cells and may be determined with a calibration process. The calibration may increase the computing resources required and so to limit such increases, the non-volatile memory device can be configured to allow storage of a predetermined number of operating parameters, and to retrieve the ones that are optimal based on environmental models [Col 2: lines 40-65]. The operating parameters may include voltage levels used to write to memory cells. The write thresholds/levels can be modeled and pre-calculated [Col 3: lines 15-40]. There can be a plurality of models for different environmental parameters, such as temperature [Col 11: lines 55-65]. Each model can be applicable to only a certain range of temperatures [Col 12: line 60 – Col 13: line 10]. The measurement of the environmental parameter can be based on a measurement period, and the measurements may be aggregated [Col 13: lines 15-25]. The models can include a power on/off interval, a forecasted bit error rate, predicted use of the memory or workload, geolocation data, type of memory, the type of device the memory is in or its heat generation profile, range of motion data, etc. [Col 15: lines 45-57], [Col 7: lines 20-35], [Col 12: lines 1-67].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified parameter sets chosen based on the temperature thresholds as taught by Wakchaure to include choosing the parameter sets based on a selected model that has an appropriate environmental range including an appropriate temperature range based on the determined and predicted temperature of the memory device as taught by Bazarsky.
One of ordinary skill in the art would have been motivated to make this modification because it would allow optimal parameters to be retrieved based on environmental parameters following a predicted model, which may account for many more factors than simply temperature over the life of the storage device as taught by Bazarsky in [Col 2: lines 44-67] [Col 15: lines 45-57], [Col 7: lines 20-35], [Col 12: lines 1-67].
Regarding claim 5:
The apparatus of claim 1 is made obvious by Wakchaure in view of Bazarsky (Wakchaure-Bazarsky).
Wakchaure further discloses:
wherein the second trim profile (i.e., thermal voltage model as taught by Bazarsky) includes at least one operational temperature that is different than a corresponding operational temperature in the first trim profile (i.e., thermal voltage model as taught by Bazarsky) (by disclosing that profile A applies to temperatures below Tc while profile B applies to temperatures above Tc. There may also be more temperature ranges/profiles such that A would apply below Tc1 and B would apply between Tc1 and Tc2 and C would apply above Tc2 [0024-0025] [Fig. 3]).
Regarding claim 8:
The apparatus of claim 1 is made obvious by Wakchaure-Bazarsky.
Wakchaure further discloses:
wherein the monitoring of the memory system while configured with the first set of operating characteristics includes monitoring operational temperatures of the memory system (by disclosing that the temperature of the memory system is monitored while trim profile A is applied to the system [Fig. 3] [0024-0025]).
Regarding claim 9:
The apparatus of claim 1 is made obvious by Wakchaure-Bazarsky.
Wakchaure further discloses:
wherein the second set of operating characteristics includes at least one operational characteristic that is different than a corresponding operational characteristic in the first set of operating characteristics (by disclosing that the trim profiles define sets of NAND operating parameters including program/erase/read WL/BL voltages, program-verify voltages, read-reference levels, maximum WL bias and operational timeout [0022]. There are different characteristic values for high-temperature profile B than for lower temperature profile A to cause deeper erase, slower programs, SLC operation, and dynamic Vread [0030-0034]).
Regarding claim 10:
The apparatus of claim 1 is made obvious by Wakchaure-Bazarsky.
Wakchaure further discloses:
wherein the at least one operational characteristic that is different is an amount of read latency, a program/erase (P/E) cycle time, or both (by teaching that profile trim parameters include array operation timeouts [0033], and the slower program trims for trim profile B causes program performance impacts of slower program times [0033], and the read voltage settings change read performance and read latency and are different for the different trim profiles [0034-0035]).
Regarding claim 13:
The method of claim 11 is made obvious by Wakchaure-Bazarsky.
Wakchaure further discloses:
wherein the method includes subsequently reconfiguring the memory system with the first set of operating characteristics responsive to the memory system experiencing a temperature that exceeds a threshold temperature (by disclosing that if temperature reaches the temperature threshold Tc (the memory system experiencing a temperature that exceeds a threshold temperature), then trim profile B may be loaded (308) and used for operating the memory (312) [Fig. 3] [0024-0025]. This may be part of a continuous operation that involves continually switching between trim profiles A and B depending on the temperature of the memory system [Fig. 3] [0024-0025]).
Regarding claim 14:
The method of claim 11 is made obvious by Wakchaure-Bazarsky.
Wakchaure further discloses:
wherein the method includes subsequently reconfiguring the memory system with the first set of operating characteristics (by disclosing that if temperature reaches the temperature threshold Tc (the memory system experiencing a temperature that exceeds a threshold temperature), then trim profile B may be loaded (308) and used for operating the memory (312) [Fig. 3] [0024-0025]. This may be part of a continuous operation that involves continually switching between trim profiles A and B depending on the temperature of the memory system [Fig. 3] [0024-0025]).
Wakchaure does not explicitly disclose, but Bazarsky teaches:
that a trigger for switching between models and operating with different parameters can be responsive to the memory system experiencing a bit error rate that that exceeds a bit error rate threshold (by teaching that a different parameter set may be selected if the bit error rate is within a certain threshold [Col 7: lines 20-35] [Col 9: lines 30-67] [Col 10: lines 1-45] [Col 14: lines 12-25]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the selection of parameter sets based on temperature as taught by Wakchaure to additionally include selection of a different parameter set, such as one used previously, if the bit error rate is above a threshold as taught by Bazarsky.
One of ordinary skill in the art would have been motivated to make this modification because it can reduce errors and power consumption and improve efficiency and can allow for the selection of optimal parameters as taught by Bazarsky in [Col 2: lines 20-65].
Regarding claim 17:
The apparatus of claim 15 is made obvious by Wakchaure-Bazarsky.
Wakchaure further discloses:
wherein the apparatus comprises a solid state drive (SSD) (by disclosing that the control logic (150) and NVM (152) may be included in an SSD [0018])
Regarding claim 18:
The apparatus of claim 15 is made obvious by Wakchaure-Bazarsky.
Wakchaure further discloses:
wherein the apparatus comprises a mobile system (by disclosing that the techniques may be employed in smartphone, tablet, laptop, smart watch, smart glasses, etc. [0014]))
Regarding claim 19:
The apparatus of claim 15 is made obvious by Wakchaure-Bazarsky.
Wakchaure further discloses:
wherein the processing device is configured to: write the data to the memory component while configured with the second set of operating characteristics for an additional period of time (by teaching that the method shown in [Fig. 3] is continuous, and so the temperature is monitored while operating with trim profile B (308)/(312) and the system may continue using trim profile B (312) unless the monitored temperature drops below Tc (310 – No), at which point, trim profile A may be selected and used (302), which includes the parameters for operating the NAND memory system that will continue to be used so long as the temp does not increase above Tc (306 – NO) [Fig. 3] [0024-0025]. Performed over time, this causes the system to operate with trim profile B for at least the period of time while the temperature of the memory system stays above Tc (additional period of time). While trim profile B remains loaded, it is used to operate the NAND (312), which includes settings such as WL and BL voltages for performing program operations at the higher temperatures associated with temps above Tc [0021-0022] [0030] [0033]).
monitor the operational temperature of the memory component during the additional period of time (the temp is continuously monitored (310) while operating with trim profile B [Fig. 3] [0024-0025])
subsequent to the additional period of time, configure the memory component with a third set operating characteristics (i.e., corresponding to a third thermal voltage model as taught by Bazarsky) (after operating in trim profile B (308) (312), the system may revert to operating with trim profile A (302) when the temperature drops below Tc (310 -NO) [Fig. 3] [0024-0025], or may move to trim profile C as there may be more than two trim profiles, if the temperature increases above Tc2 [0025]).
Claims 2-4, 6-7, 12, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wakchaure-Bazarsky in further view of US Patent Application Publication US 2019/0050160 A1 (Dardis).
Regarding claim 2:
The apparatus of claim 1 is made obvious by Wakchaure-Bazarsky.
Wakchaure further discloses:
wherein the controller is configured to configure the memory system with the first set of operating characteristics while the memory system is powered-on (by teaching applying profile A and operating the NVM under those parameters until the temperature causes a transition to profile B [Fig. 3] [0024-0025]).
Wakchaure does not explicitly disclose, but Dardis teaches,
wherein the controller is configured to configure the memory system with the first set of operating characteristics responsive to a power-on event of the memory system (by teaching that at start up, an ambient temperature is detected using a temperature sensor, and a temperature-based profile is loaded based on whether the current temperature falls within a temperature range for a profile [0049]. The profile includes configuration parameters such as a frequency and a voltage for operating a non-volatile memory during program and read operations [0016] [0037] [0077-0079] [0084] [Fig. 6]. A default profile may be used if there is no profile for the current temperature. The default profile may be configured to be functional over a wide range of environments (temperatures) [0049-0051]. Rather than using a set of minimal parameters, which are minimally trained to reduce training time at boot, an enhanced training operation may be performed to create a more narrowly tailored set of operating parameters tailored to a narrower environmental range. In this case, at boot, a set of parameters from a profile trained with an enhanced training operation may be performed with parameters tailored to the particular operating environment. The enhanced training may be performed at manufacture, at shutdown, or other times when it would not interfere with the boot operation, including once the memory device is deployed [0038] [0041] [0047] [0051] [0055-0060]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified models used in different temperature ranges that select trim parameters as taught by Wakchaure-Bazarsky to include default profiles (i.e. models) applicable to a wide range of operating environments (temperatures) that can be used at boot (power-on event) and then enhanced profiles (i.e., models) that are more narrowly tailored to smaller operating environments (temperature ranges) that are stored and then can also be loaded at boot (power-on event) at subsequent uses depending on temperatures measured at boot as taught by Dardis.
One of ordinary skill in the art would have been motivated to make this modification because the default profiles can be used quickly and are applicable over wide temperature ranges so as not to interfere with boot times and affect user perceived performance as taught by Dardis in [0036] [0044] while the enhanced profiles based on enhanced training that are more narrowly tailored for more narrow operating environments (temperature ranges) can increase performance compared to the minimally trained profiles as taught by Dardis in [0036-0037] [0041] [0051] [0061].
Regarding claim 3 and analogous claim 20:
The apparatus of claim 2 is made obvious by Wakchaure-Bazarsky in further view of Dardis.
Wakchaure does not explicitly disclose, but Dardis teaches:
wherein the controller is configured to monitor operation of the memory system beginning from the power-on event (by teaching that at start up, an ambient temperature is detected using a temperature sensor, and a temperature-based profile is loaded based on whether the current temperature falls within a temperature range for a profile [0049])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified models used in different temperature ranges that select trim parameters as taught by Wakchaure-Bazarsky to include default profiles (i.e. models) applicable to a wide range of operating environments (temperatures) that can be used at boot (power-on event) and then enhanced profiles (i.e., models) that are more narrowly tailored to smaller operating environments (temperature ranges) that are stored and then can also be loaded at boot (power-on event) at subsequent uses depending on temperatures measured at boot as taught by Dardis.
One of ordinary skill in the art would have been motivated to make this modification because the default profiles can be used quickly and are applicable over wide temperature ranges so as not to interfere with boot times and affect user perceived performance as taught by Dardis in [0036] [0044] while the enhanced profiles based on enhanced training that are more narrowly tailored for more narrow operating environments (temperature ranges) can increase performance compared to the minimally trained profiles as taught by Dardis in [0036-0037] [0041] [0051] [0061].
Wakchaure does not explicitly disclose, but Bazarsky teaches that the temperature may be monitored for a predetermined period of time (i.e., beginning from the power-on event as taught by Dardis) by teaching that measurements of the environmental parameter (i.e., temperature) may be taken over a period of time and the average can be used as the measurement of the environmental parameter (i.e., temperature) [Col 13: lines 15-22]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the temperature measured beginning at the power-on event as taught by Wakchaure in view of Dardis to include the average temperature over a period of time as taught by Bazarsky because it would have only required the combination on known elements according to known methods to yield predictable results. For example, Dardis teaches that the temperature may be obtained at boot but does not teach a particular method of measuring the temperature and Bazarsky teaches a particular method that includes averaging the value over a period of time. One of ordinary skill in the art could have combined the measured temperature taught by Dardis with the technique of measuring the temperature according to the average over a period as taught by Bazarsky according to known methods and the results would have been predictable. Accordingly, the claims would have been obvious to one of ordinary skill in the art at the time the invention was filed.
Regarding claim 4:
Wakchaure further discloses:
wherein the controller is configured to, after measuring the temperature (i.e., subsequent to the predetermined period of time as taught by the combination of references in claim 3), select the second thermal voltage model based on the monitored operation of the memory system (by teaching that if the measured temperature crosses the temperature threshold (Tc), then trim profile B is loaded (i.e., second thermal voltage model as taught by Bazarsky in claim 1) [Fig. 3]).
Regarding claim 6 and analogous claim 16:
The apparatus of claim 1 is made obvious by Wakchaure-Bazarsky.
Wakchaure does not explicitly disclose, but Dardis teaches:
wherein an uppermost operational temperature in the second thermal voltage model is less than an uppermost operational temperature in the first thermal voltage model (by teaching that over time, models may be tightened such that ranges may be narrowed. For example, profile N has range of 67±40 degrees, while profile 1 has a range of 40±4 degrees, such that the uppermost operational temperature is lower, while the lowermost temperature is also higher (36-44 for profile 1 while profile N is 27-107) [0056] [0062-0072] [0074] [Fig. 7]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified models used in different temperature ranges that select trim parameters as taught by Wakchaure-Bazarsky to include default profiles (i.e. models) applicable to a wide range of operating environments (temperatures) that can be used at boot (power-on event) and then enhanced profiles (i.e., models) that are more narrowly tailored to smaller operating environments (temperature ranges) that are stored and then can also be loaded at boot (power-on event) or on subsequent uses as taught by Dardis.
One of ordinary skill in the art would have been motivated to make this modification because the default profiles can be used quickly and are applicable over wide temperature ranges so as not to interfere with boot times and affect user perceived performance as taught by Dardis in [0036] [0044] while the enhanced profiles based on enhanced training that are more narrowly tailored for more narrow operating environments (temperature ranges) can increase performance compared to the minimally trained profiles as taught by Dardis in [0036-0037] [0041] [0051] [0061].
Regarding claim 7 and analogous claim 12:
The apparatus of claim 6 is made obvious by Wakchaure-Bazarsky in further view of Dardis.
Wakchaure does not explicitly disclose, but Dardis teaches:
wherein a lowermost operational temperature in the second thermal voltage model is higher than a lowermost operational temperature in the first thermal voltage model (through the analysis performed for claim 6).
Conclusion
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/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139
