DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. In an amendment dated, September 01, 2026, claims 1 and 19 are amended. Currently claims 1-20 are pending.
Response to Arguments
Applicant's arguments filed September 01, 2026, have been fully considered but they are not persuasive.
In the remarks filed on September 01, 2026, applicant argues prior art of record fails to disclose newly added claim limitation of independent claim 1 as filed wherein "a first gate electrode configured to receive a scan signal, and a second gate electrode coupled to the DC voltage”. The Examiner does not identify where Woo discloses that the body electrode is "a second gate electrode coupled to the DC voltage." Because Woo does not disclose each element arranged as recited in claim 1(added). And claim limitation of independent claim 19 as filed wherein "a first gate electrode configured to receive a scan signal, and a second gate electrode coupled to the DC voltage." The Examiner relies on Lee's switching transistor T2, which the Examiner identifies as having a gate electrode connected to a first scan line and a body electrode connected to a driving voltage line. (Office Action, p. 4.) The Examiner does not identify where Lee discloses that the body electrode is "a second gate electrode coupled to the DC voltage." The office respectfully disagrees. Independent claim(s) recites the connection of first gate electrode and second gate electrode of switching thin film transistor. Thus, as shown below prior art of recode clearly discloses the connection of first and second gate electrode of switching thin film transistor as claimed. Applicant argues limitations of independent claims 1 and 19 that are not claimed. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., body electrode) are not recited in the rejected claim(s) 1 and 19. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, as to the connection of components within a circuit. Applicant recites one component connected to another component (e.g. back gate electrode of TFT to source electrode). The claim limitation does not recite a direct connection of circuit components. Thus, given the claim limitation broadest reasonable interpretation, it is clear that components of (pixel) circuit are connected to each other within said circuit; therefore, it is clearly shown within prior art of record that each components (i.e. electrodes) of said circuit would be electrically connected to each other within said circuit.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Woo et al (PG PUB NO 2025/0384834).
As in claim 1, Woo et al discloses a circuit (Fig. 5) comprising:
a switching thin film transistor (TFT) having a threshold voltage based on a value of a direct current (DC) voltage; (Fig. 5 item TR2) discloses switching thin film transistor connected to a first power line PL1
a first gate electrode configured to receive a scan signal, and a second gate electrode coupled to a source of the DC voltage; (Fig. 5 item TR2) discloses first gate electrode configured to receive a scan signal (SCAN1[i]), and a second gate electrode coupled to a source of the DC voltage (power voltage VDD1)
a driving TFT coupled to the switching TFT; (Fig. 5 item TR1) discloses driving TFT coupled to the switching TFT
a storage capacitor disposed between the switching TFT and the driving TFT; (Fig. 5 item Cstg) discloses storage capacitor (Cstg) disposed between the switching TFT (TR2) and the driving TFT (TR1)
and an organic light-emitting diode (OLED) having an anode coupled to the driving TFT. (Fig. 5 item LD)
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al (2025/0061862).
As in claim 19, Lee et al discloses a circuit (Fig 4, pixel circuit) comprising:
a switching TFT having a threshold voltage based on a value of a direct current (DC) voltage; (Fig 4 item T2) discloses the switching TFT connected to a DC voltage higher than the common voltage ELVSS and lower than the driving voltage ELVDD.
a first gate electrode configured to receive a scan signal, and a second gate electrode coupled to a source of the DC voltage; (Fig. 5 item TR2) discloses first gate electrode configured to receive a scan signal (SS1), and a second gate electrode coupled to a source of the DC voltage (ELVDD)
a loading capacitor coupled to the switching TFT; (Fig 4 capacitor C1) discloses capacitor coupled to the switching TFT
and a storage capacitor coupled to the switching TFT. (Fig 4 capacitor C3) discloses capacitor coupled to the switching TFT
As in claim 20, Lee et al discloses the circuit (Fig 4, pixel circuit) of claim 19, wherein a top gate electrode of the switching TFT is coupled to the DC voltage or a back gate electrode of the switching TFT is coupled to the DC voltage. (Fig 4 item T2) discloses back gate/body electrode of the switching TFT connected to a DC voltage.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 6-11 and 13-16 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Miyake (PG Pub No 2013/0063413).
As in claim 6, Miyake discloses a circuit (Fig 4) comprising:
a first switching thin film transistor (TFT); (Fig 4 item 34)
a second switching TFT, the second switching TFT having a threshold voltage that is based on a value of a direct current (DC) voltage; (Fig. 4 item 37) discloses (second) thin film transistor (37) connected to a first power line VLc
a driving TFT coupled to the first switching TFT and the second switching TFT; (Fig. 4 item 15) discloses driving TFT coupled to the switching TFT
a first storage capacitor having a first side that is coupled to a first node disposed between the second switching TFT and the driving TFT; (Fig. 4 item capacitor 38) discloses storage capacitor (38) disposed between the (second) TFT (37) and the driving TFT (15)
and an organic light-emitting diode (OLED) having an anode coupled to the driving TFT. (Fig. 4 item light-emitting element 14)
As in claim 7, Miyake discloses the circuit (Fig 4) of claim 6, wherein a second side of the first storage capacitor (38) is coupled to the anode of the OLED (light-emitting element 14), a positive supply voltage, or a source electrode of the driving TFT (15). (Fig 4) discloses the second side of the first storage capacitor (38) coupled to a source electrode of the driving TFT (15)
As in claim 8, Miyake discloses the circuit (Fig 4) of claim 6, wherein the first side of the first storage capacitor (38) is coupled to a drain electrode of the second switching TFT (37) and a back gate electrode of the driving TFT (15) via the first node. (Fig 4) discloses claimed connection via a node between driving TFT (15) and second switching TFT (37)
As in claim 9, Miyake discloses the circuit (Fig 4) of claim 8, further comprising: a second storage capacitor (17) coupled to a second node disposed between a source electrode of the first switching TFT (34) and a top gate electrode of the driving TFT (15). (Fig 4) discloses second storage capacitor (17) coupled to second node in between first switching TFT and driving TFT (15).
As in claim 10, Miyake discloses the circuit (Fig 4) of claim 6, wherein the first side of the first storage capacitor (38) is coupled to a drain electrode of the second switching TFT (37) and a top gate electrode of the driving TFT via the first node. (Fig 4) discloses the storage capacitor is coupled to a drain electrode of the second switching TFT and a top gate electrode of the driving TFT via the first node
As in claim 11, Miyake discloses the circuit (Fig 4) of claim 10, further comprising: a second storage capacitor (17) coupled to a second node disposed between a source electrode of the first switching TFT and a back gate electrode of the driving TFT. (Fig 4) discloses second storage capacitor (17) coupled to a second node disposed between a source electrode of the first switching TFT (34) and a back gate electrode of the driving TFT (15 gate BG).
As in claim 13, Miyake discloses the circuit (Fig 4) of claim 6, further comprising a third switching TFT coupled between a voltage sensing line and the anode of the OLED. (Fig 4 item 36) discloses third switching TFT (36)
As in claim 14, Miyake discloses the circuit (Fig 4) of claim 13, further comprising a fourth switching TFT (3) coupled between the driving TFT (15) and a positive supply voltage (Vla). (Fig 4 item 33)
As in claim 15, Miyake discloses the circuit (Fig 4) of claim 14, further comprising a fifth switching TFT (35) coupled between the driving TFT (15) and the anode of the OLED (14). (Fig 4 TFT 35)
As in claim 16, Miyake discloses the circuit (Fig 4) of claim 15, further comprising a sixth switching TFT (31) having a source electrode coupled to a third node and a drain electrode coupled to a fourth node, wherein the third node that is further coupled to a source electrode of the fourth switching TFT and a drain electrode of the driving TFT(15), and the fourth node is further coupled to a top gate electrode of the driving TFT (15) and a second capacitor. (Fig 4 item TFT 31) discloses sixth switching TFT and its connection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo et al (PG PUB NO 2025/0384834) in view of Miyake (PG Pub No 2013/0063413).
As in claim 2, Woo et al discloses the circuit (Fig 5) of claim 1, wherein: a drain electrode of the switching TFT is coupled to a data signal line (DLj) [(Fig 5 item TR2) discloses the connection of drain electrode and data line(DLj)] ; and a source electrode of the switching TFT is coupled to a node (N3, N1) that is further coupled to a top gate electrode of the driving TFT (TR1) and the storage capacitor (Cstg) [(Fig 5) discloses the connection]; a source electrode of the driving TFT (TR1) is coupled to the anode of the OLED (LD) (Fig 5) discloses the connection of switching TFT; but fails to disclose a back gate electrode of the driving TFT is coupled to the source electrode of the driving TFT. However, Miyake (Fig 4) discloses the back gate electrode of the driving TFT (15) is coupled to the source electrode of the driving TFT (15). Therefore, it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Woo et al with the teaching of Miyake pixel drive circuit with an alternat method of connecting drive TFT within pixel circuit to yield same predictable outcome.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo et al (PG PUB NO 2025/0384834) in view of Shirasaki et al (PG Pub No 2006/0061526).
As in claim 3, Woo et al discloses the circuit (Fig 5) of claim 1, wherein: a drain electrode of the switching TFT (TR2) is coupled to a data signal line(DLj) (Fig 5, TR2); a source electrode of the switching TFT (TR2) is coupled to a node that is further coupled to a top gate electrode of the driving TFT (TR1) and the storage capacitor(Cstg) (Fig 5); a source electrode of the driving TFT i(TR1)s coupled to the anode of the OLED (LD) (fig 5); but fails to disclose a back gate electrode of the driving TFT is coupled to the source electrode of the switching TFT. However, Shirasaki et al (Fig 2) discloses the back gate electrode of the driving TFT (Tr12) is coupled to the source electrode of the switching TFT(Tr11). Therefore, it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Woo et al with the teaching of Shirasaki et al pixel drive circuit for an alternat method of connecting drive TFT and switching TFT within pixel circuit to yield same predictable outcome.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo et al (PG PUB NO 2025/0384834) in view of Yim et al (PG Pub NO 2024/0194152).
As in claim 4 , Woo et al discloses the circuit (Fig 5) of claim 1, wherein a top gate electrode of the switching TFT is coupled to a gate driver on array (GOA) circuit [(Fig 1, 5) discloses the top gate of (TR2) is connected to gate driver (GL1) gate driver line] comprising: but fails to explicitly disclose gate driver on array (GOA) circuit comprising a pull-up TFT having a back gate electrode coupled to the DC voltage; and a pull-down TFT coupled to the pull-up TFT, the pull-down TFT having a back gate electrode coupled to the DC voltage. However, Yim et al (Fig 1, 4 and Par 0037) discloses pixel circuits 404 and GOA circuits 402 in a display panel 100. The GOA circuit 402 comprising switching transistors, such as a pull up buffer switching transistor Tdown and a pull-down buffer switching transistor Tup. Therefore, it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Woo et al with the teaching of Yim et al well-known gate deriving circuit to illustrate known components of display device to yield same predictable outcome.
As in claim 5, Woo et al discloses the circuit (Fig 5) of claim 1, wherein a top gate electrode of the switching TFT is coupled to a gate driver on array (GOA) circuit [(Fig 1, 5) discloses the top gate of (TR2) is connected to (SGL1i) gate driver line] comprising: but fails to explicitly disclose gate driver on array (GOA) circuit comprising a pull-up TFT having a top gate electrode coupled to the DC voltage; and a pull-down TFT coupled to the pull-up TFT, the pull-down TFT having a top gate electrode coupled to the DC voltage. However, Yim et al (Fig 1, 4 and Par 0037) discloses pixel circuits 404 and GOA circuits 402 in an display panel 100. The GOA circuit 402 comprising switching transistors, such as a pull up buffer switching transistor Tdown and a pull-down buffer switching transistor Tup. Therefore, it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Woo et al with the teaching of Yim et al well-known gate deriving circuit to illustrate known components of display device to yield same predictable outcome.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (PG Pub No 2013/0063413) in view of Lim et al (PG Pub NO 2016/0300526).
As in claim 12, Miyake discloses the circuit (Fig 4) of claim 6, but fails to disclose a top gate electrode of the second switching TFT is coupled to a back gate electrode of the second switching TFT. However, Lim et al (Fig 3) discloses OLED pixel circuit wherein top gate electrode of the second switching TFT (TFT 307) is coupled to a back gate electrode of the second switching TFT(TFT 307). Therefore, it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Miyake with the teaching of Lim et al wherein the switching TFT top gate electrode and back gate electrode is coupled in order to improve efficiency and switching speed of the pixel.
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (PG Pub No 2013/0063413) in view of Yim et al (PG Pub NO 2024/0194152).
As in claim 17, Miyake discloses the circuit (Fig 4) of claim 6, wherein the first switching TFT and the second switching TFT are coupled to a gate driver on array (GOA) circuit [(Fig 4) discloses first and second switching TFT’s connected to gate line of gate driver (i.e. source driver)] comprising: but fails to explicitly disclose gate driver on array (GOA) circuit comprising a pull-up TFT having a back gate electrode coupled to the DC voltage; and a pull-down TFT coupled to the pull-up TFT, the pull-down TFT having a back gate electrode coupled to the DC voltage. However, Yim et al (Fig 1, 4 and Par 0037) discloses pixel circuits 404 and GOA circuits 402 in an display panel 100. The GOA circuit 402 comprising switching transistors, such as a pull up buffer switching transistor Tdown and a pull-down buffer switching transistor Tup. Therefore, it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Miyake with the teaching of Yim et al well-known gate deriving circuit to illustrate known components of display device to yield same predictable outcome.
As in claim 18, Miyake discloses the circuit (Fig 4) of claim 6, wherein the first switching TFT and the second switching TFT are coupled to a gate driver on array (GOA) circuit [(Fig 4) discloses first and second switching TFT’s connected to gate line of gate driver (i.e. source driver)] comprising: but fails to explicitly disclose gate driver on array (GOA) circuit comprising a pull-up TFT having a top gate electrode coupled to the DC voltage; and a pull-down TFT coupled to the pull-up TFT, the pull-down TFT having a top gate electrode coupled to the DC voltage. However, Yim et al (Fig 1, 4 and Par 0037) discloses pixel circuits 404 and GOA circuits 402 in an display panel 100. The GOA circuit 402 comprising switching transistors, such as a pull up buffer switching transistor Tdown and a pull-down buffer switching transistor Tup. Therefore, it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Miyake with the teaching of Yim et al well-known gate deriving circuit to illustrate known components of display device to yield same predictable outcome.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENYAM KETEMA whose telephone number is (571)270-7224. The examiner can normally be reached 9AM-5PM (M-F).
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/BENYAM KETEMA/Primary Examiner, Art Unit 2626
