Prosecution Insights
Last updated: October 23, 2026
Application No. 19/311,207

ACTIVE CONTROL OF LIGHT EMITTING DIODES AND LIGHT EMITTING DIODE DISPLAYS

Non-Final OA §DP
Filed
Aug 27, 2025
Priority
Mar 29, 2019 — CIP of 11/727,857 +5 more
Examiner
CHAN, WEI
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
CreeLED Inc.
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
446 granted / 597 resolved
+6.7% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
22 currently pending
Career history
628
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
71.9%
+31.9% vs TC avg
§102
4.8%
-35.2% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 597 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 07/15/2026, 05/16/2026, 04/18/2026, 02/01/2026 and 12/11/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 11,694,601 B2 in view of Peting et al [US 2012/0299480 A1]. Instant Application: 19/311,207 claims 1-25 of U.S. Patent No. 11,694,601 B2 1. A light-emitting diode (LED) display, comprising:a control element configured to provide a serial communication signal; anda plurality of LED packages arranged to receive the serial communication signal from the control element, each LED package of the plurality of LED packages comprising:a submount;at least one LED chip on the submount; andan active electrical element on the submount and electrically connected to the at least one LED chip, the active electrical element comprising a pulse width modulation (PWM) driver and a counter transformation device, the active electrical element configured to:provide a PWM signal to the at least one LED chip that comprises a PWM period and a PWM duty cycle, the PWM duty cycle corresponding to a portion of the PWM period in which the at least one LED chip is electrically activated;wherein, for the PWM duty cycle, the at least one LED chip iselectrically activated and electrically deactivated a plurality of times within the PWM period by transforming a sequential binary counter signal into a non-numerically ordered counter sequence for the PWM period by bit reversal, wherein the bit reversal comprises reversing an order of values within a sequential binary counter value to provide a modified binary counter value of the sequential binary counter signal while maintaining a bit depth of the PWM signal. 2. The LED display of claim 1, wherein the active electrical element comprises a signal conditioning element that is configured to transform a command signal received from a data stream. 3. The LED display of claim 1, wherein the counter transformation device is configured to transform the sequential binary counter signal into the non- numerically ordered counter sequence for the PWM period. 4. The LED display of claim 3, wherein the non-numerically ordered counter sequence is formed by bit reversal of all sequential binary counter values of the sequential binary counter signal within the PWM period. 5. The LED display of claim 3, wherein the non-numerically ordered counter sequence is formed by partial bit reversal such that less than all sequential binary counter values of the sequential binary counter signal are subjected to bit reversal. 6. The LED display of claim 3, wherein the non-numerically ordered counter sequence comprises eight segments within the PWM period. 7. The LED display of claim 3, wherein the non-numerically ordered counter sequence comprises sixteen segments within the PWM period. 8. The LED display of claim 3, wherein the non-numerically ordered counter sequence comprises thirty-two segments within the PWM period. 9. The LED display of claim 3, wherein the non-numerically ordered counter sequence comprises sixty-four segments within the PWM period. 10. The LED display of claim 3, wherein the non-numerically ordered counter sequence counts a total number of values in the PWM period that corresponds to a bit-depth of a command signal. 11. The LED display of claim 3, wherein the active electrical element comprises a comparator device that is configured to compare a command signal from a data stream with the non-numerically ordered counter sequence to provide a control signal for the at least one LED chip. 12. The LED display of claim 11, wherein the active electrical element comprises a driver that is configured to receive the control signal and drive the at least one LED chip. 13. The LED display of claim 1, wherein the active electrical element comprises a memory element configured to receive and store a command signal from a data stream. 14. The LED display of claim 1, wherein the at least one LED chip comprises a plurality of LED chips that form at least one LED pixel. 15. The LED display of claim 1, wherein the active electrical element is configured to receive an input at the counter transformation device and select between a segmented duty PWM cycle and a continuous PWM duty cycle for the at least one LED chip. 16. A method of light output control for alight-emitting diode (LED) display, the method comprising:providing a display panel comprising a plurality of serially connected LED packages, each LED package of the plurality of serially connected LED packages comprising one or more LED chips and an active electrical element with a pulsewidth modulation (PWM) driver;sending a data signal from a controller to the plurality of serially connected LED packages;providing a PWM signal from the PWM driver to the one or more LED chips of each LED package, the PWM signal comprising a PWM period and aPWM duty cycle that corresponds to a portion of the PWM period in which the one or more LED chips are electrically activated; and separately segmenting the PWM duty cycle within the active electrical element of each LED package such that the one or more LED chips of each LED package are electrically activated and electrically deactivated a plurality of times within the PWM period by transforming a sequential binary counter signal into anon-numerically ordered counter sequence for the PWM period by bit reversal, wherein the bit reversal comprises reversing an order of values within a sequential binary counter value to provide a modified binary counter value of the sequential binary counter signal while maintaining a bit depth of the PWM signal. 17. The method of claim 16, further comprising receiving an input at the active electrical element for selecting between a numerically ordered counter sequence and the non-numerically ordered counter sequence for each PWM period of each serially connected LED package. 18. The method of claim 17, wherein the non-numerically ordered counter sequence is a segmented duty cycle and the numerically ordered counter sequence is a continuous duty cycle, the method further comprising toggling between the segmented duty cycle and the continuous duty cycle. 19. The method of claim 16, further comprising comparing a command signal for the one or more LED chips with the non-numerically ordered counter sequence and providing a control signal for the one or more LED chips during the PWM period. 20. The method of claim 16, wherein the active electrical element of each LED package is configured to initiate a reset command upon receiving a reset signal embedded in the data signal from the controller. 12. A light emitting diode (LED) package comprising: a submount; at least one LED chip on the submount; and an active electrical element adjacent to the at least one LED chip on the submount and electrically connected to the at least one LED chip, the active electrical element comprising a pulse width modulation (PWM) driver and a counter transformation device, the active electrical element configured to: provide a PWM signal to the at least one LED chip that comprises a PWM period and a PWM duty cycle, the PWM duty cycle corresponding to a portion of the PWM period in which the at least one LED chip is electrically activated; and receive an input at the counter transformation device and select between a segmented duty PWM cycle and a continuous PWM duty cycle for the at least one LED chip; wherein, for the segmented PWM duty cycle, the at least one LED chip is electrically activated and electrically deactivated a plurality of times within the PWM period by transforming a sequential binary counter signal into a non-numerically ordered counter sequence for the PWM period by bit reversal, wherein the bit reversal comprises reversing an order of values within a sequential binary counter value to provide a modified binary counter value of the sequential binary counter signal while maintaining a bit depth of the PWM signal. 13. The LED package of claim 12, wherein the active electrical element comprises a signal conditioning element that is configured to transform a command signal received from a data stream. 14. The LED package of claim 12, wherein the counter transformation device is configured to transform the sequential binary counter signal into the non-numerically ordered counter sequence for the PWM period. 15. The LED package of claim 14, wherein the non-numerically ordered counter sequence is formed by bit reversal of all sequential binary counter values of the sequential binary counter signal within the PWM period. 16. The LED package of claim 14, wherein the non-numerically ordered counter sequence is formed by partial bit reversal such that less than all sequential binary counter values of the sequential binary counter signal are subjected to bit reversal. 17. The LED package of claim 14, wherein the non-numerically ordered counter sequence comprises eight segments within the PWM period. 18. The LED package of claim 14, wherein the non-numerically ordered counter sequence comprises sixteen segments within the PWM period. 19. The LED package of claim 14, wherein the non-numerically ordered counter sequence comprises thirty-two segments within the PWM period. 20. The LED package of claim 14, wherein the non-numerically ordered counter sequence comprises sixty-four segments within the PWM period. 21. The LED package of claim 14, wherein the non-numerically ordered counter sequence counts a total number of values in the PWM period that corresponds to a bit-depth of a command signal. 22. The LED package of claim 14, wherein the active electrical element comprises a comparator device that is configured to compare a command signal from a data stream with the non-numerically ordered counter sequence to provide a control signal for the at least one LED chip. 23. The LED package of claim 22, wherein the active electrical element comprises a driver that is configured to receive the control signal and drive the at least one LED chip. 24. The LED package of claim 12, wherein the active electrical element comprises a memory element configured to receive and store a command signal from a data stream. 25. The LED package of claim 12, wherein the at least one LED chip comprises a plurality of LED chips that form at least one LED pixel. 1. A method of controlling a light emitting diode (LED) device, the method comprising: providing a plurality of LED packages, each LED package of the plurality of LED packages comprising one or more LED chips and an active electrical element with a pulse width modulation (PWM) driver; providing a PWM signal from the PWM driver to the one or more LED chips of each LED package, the PWM signal comprising a PWM period and a PWM duty cycle that corresponds to a portion of the PWM period in which the one or more LED chips are electrically activated; and receiving an input at the active electrical element for selecting between a numerically ordered counter sequence and a non-numerically ordered counter sequence for each PWM period of each LED package; wherein selecting the non-numerically ordered counter sequence comprising separately segmenting the PWM duty cycle within the active electrical element of each LED package such that the one or more LED chips of each LED package are electrically activated and electrically deactivated a plurality of times within the PWM period by transforming a sequential binary counter signal into the non-numerically ordered counter sequence for the PWM period by bit reversal, wherein the bit reversal comprises reversing an order of values within a sequential binary counter value to provide a modified binary counter value of the sequential binary counter signal while maintaining a bit depth of the PWM signal. 2. The method of claim 1, wherein the non-numerically ordered counter sequence is a segmented duty cycle and the numerically ordered counter sequence is a continuous duty cycle, the method further comprising toggling between the segmented duty cycle and the continuous duty cycle. 3. The method of claim 1, further comprising comparing a command signal for the one or more LED chips with the non-numerically ordered counter sequence and providing a control signal for the one or more LED chips during the PWM period. 4. The method of claim 3, wherein the non-numerically ordered counter sequence counts a total number of values in the PWM period that corresponds to a bit-depth of the command signal. 5. The method of claim 3, wherein the non-numerically ordered counter sequence is formed by bit reversal of all sequential binary counter values of the sequential binary counter signal within the PWM period. 6. The method of claim 3, wherein the non-numerically ordered counter sequence is formed by partial bit reversal such that less than all sequential binary counter values of the sequential binary counter signal are subjected to bit reversal. 7. The method of claim 3, wherein the non-numerically ordered counter sequence comprises eight segments within the PWM period. 8. The method of claim 3, wherein the non-numerically ordered counter sequence comprises sixteen segments within the PWM period. 9. The method of claim 3, wherein the non-numerically ordered counter sequence comprises thirty-two segments within the PWM period. 10. The method of claim 3, wherein the non-numerically ordered counter sequence comprises sixty-four segments within the PWM period. 11. The method of claim 1, wherein the active electrical element of each LED package is configured to initiate reset command upon receiving a reset signal. Hussell does not specify a light-emitting diode (LED) display Peting discloses a light-emitting diode (LED) display (Paragraph [0044]). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to use the teachings of Peting with Hussell to discloses or teaches a light-emitting diode (LED) display for purpose of reduces the cost of LED based lighting systems while simultaneously improving the feature set of LED based lighting systems disclosed by Peting (Paragraph [0224]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhao [US 2010/0085295 A1] Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEI (VICTOR) CHAN whose telephone number is (571)272-5177. The examiner can normally be reached M-F 9:00am to 6:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. WEI (VICTOR) CHAN Primary Examiner Art Unit 2844 /WEI (VICTOR) Y CHAN/Primary Examiner, Art Unit 2845
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Prosecution Timeline

Aug 27, 2025
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §DP (current)

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
88%
With Interview (+13.8%)
2y 2m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 597 resolved cases by this examiner. Grant probability derived from career allowance rate.

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