Prosecution Insights
Last updated: April 19, 2026
Application No. 19/315,804

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE SIDE INTERCONNECTION AND METHOD OF FORMING THE SAME

Final Rejection §112
Filed
Sep 01, 2025
Examiner
SOWARD, IDA M
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Etron Technology Inc.
OA Round
2 (Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allow Rate
1226 granted / 1316 resolved
+25.2% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
48 currently pending
Career history
1364
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
33.6%
-6.4% vs TC avg
§102
35.2%
-4.8% vs TC avg
§112
30.2%
-9.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1316 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is in response to the Applicant’s amendment filed on December 24, 2025. Drawings (PREVIOUSLY PRESENTED IN-PART) The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first body; the primary surface greater than the secondary surface in area; the primary redistribution layer (RDL) over the primary surface of the first body; the primary RDL having an edge surface aligned or substantially aligned with the secondary surface of the first body; the edge RDL over the secondary surface of the first body of each IC structure and the edge surface of the primary RDL of each IC structure; the primary RDL electrically connected to the edge RDL and the first body; and the edge RDL electrically connected to the first body through the primary RDL must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to because reference characters not shown or known for the edge RDL, first conductive element, plurality of second conductive elements, first interconnect surface and second interconnect surface. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification (PREVIOUSLY PRESENTED IN-PART with corrections) The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE SIDE INTERCONNECTION . The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the first body; the primary surface greater than the secondary surface in area; the primary redistribution layer (RDL) over the primary surface of the first body; the primary RDL having an edge surface aligned or substantially aligned with the secondary surface of the first body; the edge RDL over the secondary surface of the first body of each IC structure and the edge surface of the primary RDL of each IC structure; the primary RDL electrically connected to the edge RDL and the first body; and the edge RDL electrically connected to the first body through the primary RDL. Claim Rejections - 35 USC § 112 (PREVIOUSLY PRESENTED) The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1, 3 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In regard to claim 1, it is not understood where exactly the first body; the primary surface greater than the secondary surface in area; the primary redistribution layer (RDL) over the primary surface of the first body; the primary RDL having an edge surface aligned or substantially aligned with the secondary surface of the first body; the edge RDL over the secondary surface of the first body of each IC structure and the edge surface of the primary RDL of each IC structure; the primary RDL electrically connected to the edge RDL and the first body; and the edge RDL electrically connected to the first body through the primary RDL as related to one another; In regard to claim 3, it is not understood where exactly the first body; the primary surface greater than the secondary surface in area; the primary redistribution layer (RDL) over the primary surface of the first body; the primary RDL having an edge surface aligned or substantially aligned with the secondary surface of the first body; the edge RDL over the secondary surface of the first body of each IC structure and the edge surface of the primary RDL of each IC structure; the primary RDL electrically connected to the edge RDL and the first body; the edge RDL electrically connected to the first body through the primary RDL as related to one another; a first conductive element exposed through the edge surface of the primary RDL; and a conductive pad on the edge surface of the primary RDL substantially parallel to the primary surface, a conductive via connecting adjacent layers of the primary RDL, a stacked via traversing the primary RDL, or a combination thereof; and In regard to claim 7, it is not understood where exactly the first body; the primary surface greater than the secondary surface in area; the primary redistribution layer (RDL) over the primary surface of the first body; the primary RDL having an edge surface aligned or substantially aligned with the secondary surface of the first body; the edge RDL over the secondary surface of the first body of each IC structure and the edge surface of the primary RDL of each IC structure; the primary RDL electrically connected to the edge RDL and the first body; the edge RDL electrically connected to the first body through the primary RDL as related to one another; the secondary surface of the first body and the edge surface of the primary RDL jointly form a secondary plane; the secondary surface of the first body and the edge surface of the primary RDL jointly form a secondary plane, wherein the edge RDL covers the secondary plane, with the edge RDL comprising a first surface coincident with the secondary plane, and a second surface opposite to the first surface; and the first surface of the edge RDL comprises a first flip-chip bonding layer corresponding to a second flip-chip bonding layer on the secondary plane. Claims 2, 4-6 and 8-11 are rejected as being dependent upon rejected claim 1. Allowable Subject Matter As best understood, claims 1-11 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Response to Arguments Applicant's arguments filed December 24, 2025 have been fully considered but they are not persuasive. It would be extremely beneficial to correlate the claimed semiconductor package structure with the application drawings and reference characters due to in-part by the numerous number of drawing and reference characters with similar names. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor packages: Liu et al (US 2019/0051621 A1) Patel (US 8,294,252 B1). Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDA M SOWARD whose telephone number is (571)272-1845. The examiner can normally be reached Monday through Thursday, 7am to 5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chang Leonard can be reached on 571-570-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. IMS January 15, 2026 /IDA M SOWARD/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Sep 01, 2025
Application Filed
Oct 14, 2025
Non-Final Rejection — §112
Dec 24, 2025
Response Filed
Jan 15, 2026
Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+5.4%)
2y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 1316 resolved cases by this examiner. Grant probability derived from career allow rate.

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