DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 05 September 2025.
Claims 1-20 are pending and have been presented for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 8, 11, 15 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation “… the first data being stored in at least one of a first memory in an accelerator including a vector register, a scalar register and the vector processor, and a second memory located external to the accelerator.” The language and punctuation used create some confusion with respect to the grouping and what the elements are in the list of “at least one of.” The list of elements could be interpreted multiple ways, as shown below.
The first data being stored in at least one of:
(1) a first memory in an accelerator including a vector register, a scalar register and the vector processor
(2) and a second memory located external to the accelerator
The first data being stored in at least one of:
(1) a first memory in an accelerator including a vector register
(2) a scalar register and the vector processor
(3) and a second memory located external to the accelerator
Claim 8 contains similar limitations and is rejected for the same reasons set forth above with respect to claim 7.
Claim 11 is also rejected based on the dependency to claim 7.
Claim 8 recites the limitation “… the controller is configured to store the first data stored in the LUT memory based on a fourth index value, in at least one of…” While claim 1 recites the limitation “… store first data in the LUT memory using the first index value.” The first data was stored using a first index value, therefore it is not clear what data is being referred to in claim 8. There is no first data stored using a fourth index value.
Claim 15 recites “… store the first data, stored in the vector register, in the LUT memory to perform register spill.” However, claim 1 recites the first data is stored in the LUT memory. It is not clear what data is being referred to in claim 15 since “the first data” was never referred to as being stored in the vector register.
Claim 16 is also rejected based on the dependency to claim 15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-9, 11, 12 and 15-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by CHO (U.S. Patent Application Publication #2017/0344369).
Claim 1: CHO discloses A vector processor (see [0049]: vector processor) comprising: a look-up table (LUT) memory (see [0047]-[0048]: RAM, main memory; [0076]: lookup tables are generated and stored in the memory banks) in which data corresponding to an index value is stored (see [0066]: data gathered from lookup table, data is stored at a predetermined index position); a processing unit configured to perform an operation based on the data (see [0053]: vector functional unit for performing an operation); and a controller (see [0073]: vector processor includes a controller) configured to identify a first index value based on an instruction and store first data in the LUT memory using the first index value (see [0055]-[0056]: identify an address to store the result; [0108]-[0110]: scatter unit uses software codes to identify an address to store the result vector).
Claim 2: The vector processor of claim 1, further comprising a vector register (see [0107]: divide data stored in vector register), wherein the index value is extracted from data stored in the vector register (see [0110]: scatter function stores an address that is used to store the result vector in memory).
Claim 3: The vector processor of claim 1, wherein the data includes a coefficient for linear approximation of a predetermined function (see [0075]: one of the functions performed by the vector processor involves coefficients for a gaussian filter).
Claim 4: The vector processor of claim 1, wherein the first index value is a value designated by a field of the instruction (see [0110]: scatter function includes a field to designate the first index value).
Claim 7: The vector processor of claim 1, wherein the controller is configured to store the first data in the LUT memory based on the first index value (see [0055]-[0056]: identify an address to store the result; [0108]-[0110]: scatter unit uses software codes to identify an address to store the result vector), the first data being stored in at least one of a first memory in an accelerator including a vector register, a scalar register and the vector processor, and a second memory located external to the accelerator (see [0107]: the result data is stored in a vector register, this result data is divided up and stored to the lookup table in memory).
Claim 8: The vector processor of claim 1, wherein the controller is configured to store the first data stored in the LUT memory based on a fourth index value (see [0083]-[0084]: data stored in a lookup table and is read by adding an offset to the base address, this would be the fourth index value), in at least one of a first memory in an accelerator including a vector register, a scalar register and the vector processor, and a second memory located external to the accelerator (see figure 2, lookup tables stored in main memory external to the vector processor).
Claim 9: The vector processor of claim 1, wherein the first index value is a value generated by a finite state machine (FSM) or counter logic operated based on the instruction (see [0056]: result vector stored in memory address incremented by a constant value).
Claim 11: The vector processor of claim 7, wherein the vector processor comprises a datapath between the LUT memory and at least one of the vector register, the scalar register, the first memory, and the second memory (see figure 6A, data transferred between the 8-way vector inn the vector processor and the main memory by way of the gather unit and scatter unit, these units are the data path).
Claim 12: The vector processor of claim 1, wherein the controller comprises a direct memory access (DMA) unit configured to store, in the LUT memory, the first data stored in a first memory in an accelerator including the vector processor or a second memory located external to the accelerator or store the first data stored in the LUT memory in the first memory or the second memory (see [0082]: gather unit accesses a location in main memory according to an index; [0106]: scatter unit performs the reverse process of the gather unit / the scatter unit and gather unit are considered DMA as these units access memory themselves based on an index).
Claim 15: The vector processor of claim 1, further comprising a vector register (see [0051]: vector processor includes a vector register), wherein the controller is configured to store the first data, stored in the vector register, in the LUT memory to perform register spill (see [0107]: the result data is stored in a vector register, this result data is divided up and stored to the lookup table in memory).
Claim 16: The vector processor of claim 15, wherein the controller is configured to store the first data, stored in the LUT memory, back in the vector register (see [0084]: gather unit reads data from the lookup table and stores the data in the vector register).
Claim 17: The vector processor of claim 1, wherein the LUT memory is a memory configured to simultaneously output a plurality of data stored at a plurality of locations in the LUT memory to correspond to a plurality of index values (see [0076]-[0080]: lookup tables are stored in each bank to allow simultaneous access; [0095]: eight pieces of data read from different banks, there is no bank conflict).
Claim 18: The vector processor of claim 1, wherein the data is stored in a first area of the LUT memory (see [0055]-[0057]: data is read from the memory using an address; [0083]-[0084]: vector data is gathered by the gather unit using an offset from a base address), and the first data is stored in a second area of the LUT memory (see [0055]-[0057]: result data is stored using a different address [0108]-[0110]: scatter unit stores the result data to the memory based on an address in the software code).
Claim 19: CHO discloses An operation method of a vector processor (see [0049]: vector processor) comprising a look-up table (LUT) memory (see [0047]-[0048]: RAM, main memory; [0076]: lookup tables are generated and stored in the memory banks) in which data corresponding to an index value is stored (see [0066]: data gathered from lookup table, data is stored at a predetermined index position) and a processing unit configured to perform an operation based on the data (see [0053]: vector functional unit for performing an operation) the operation method comprising: identifying a first index value based on an instruction; and storing first data in the LUT memory using the first index value (see [0055]-[0056]: identify an address to store the result; [0108]-[0110]: scatter unit uses software codes to identify an address to store the result vector).
Claim 20: CHO discloses A non-transitory computer-readable recording medium comprising a program for performing the operation method of claim 19 on a computer (see [0166]: method implemented as computer readable codes on a computer readable recording medium).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5, 6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHO (U.S. Patent Application Publication #2017/0344369) in view of WILLIAMS (U.S. Patent Application Publication #2023/0004389).
Claim 5: The vector processor of claim 1 (see CHO above), wherein the processing unit comprises a first processing unit for a multiply and accumulation (MAC) operation and a second processing unit that is an arithmetic and logic unit (ALU), and the second processing unit is configured to perform a predetermined operation based on second data identified in the LUT memory based on a second index value (see WILLIAMS below).
WILLIAMS discloses the following limitations that are not disclosed by CHO: wherein the processing unit comprises a first processing unit for a multiply and accumulation (MAC) operation (see [0048]: vector processor includes a MAC) and a second processing unit that is an arithmetic and logic unit (ALU) (see [0048]: vector processor includes an ALU), and the second processing unit is configured to perform a predetermined operation based on second data identified in the LUT memory based on a second index value (see [0047]-[0048]: vector processor performs operations on vector data stored in a vector register; MAC and ALU perform a computation on a data vector). CHO already discloses a vector processor that performs operations on data in a LUT memory that is accessed using an index value. A combination of CHO and WILLIAMS would result in an MAC and/or ALU being included inn the vector processor of CHO and fetching data from a LUT memory. A vector processor with a MAC and ALU is useful for enhancing and improving the performance of a computer in numerical computational tasks (see [0017]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify CHO to include an MAC and ALU processor, as disclosed by WILLIAMS. One of ordinary skill in the art would have been motivated to make such a modification to enhance and improve the performance of numerical computational tasks, as taught by WILLIAMS. CHO and WILLIAMS are analogous/in the same field of endeavor as both references are directed to vector processors.
Claim 6: The vector processor of claim 5, wherein the first processing unit is configured to perform a MAC operation (see WILLIAMS [0048]: performing a MAC operation on a data vector) based on fourth data identified in the LUT memory based on third data and a third index value extracted from the third data (see CHO [0093]-[0095]: data for a processing is fetched from the LUT memory by a gather unit, the indexes used to read the data would be the third data), and the fourth data includes a coefficient for linear approximation of a predetermined function (see [0075]: one of the functions performed by the vector processor involves coefficients for a gaussian filter; coefficients fetched as part of the gather operation would be the fourth data).
Claim 10: The vector processor of claim 5, wherein the vector processor comprises a datapath between the second processing unit and the LUT memory (see CHO figure 6A, data transferred between the 8-way vector inn the vector processor and the main memory by way of the gather unit and scatter unit, these units are the data path).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHO (U.S. Patent Application Publication #2017/0344369) in view of STEPHENS (U.S. Patent Application Publication #2018/0253310).
Claim 13: The vector processor of claim 1, wherein the vector processor further comprises a vector register (see [0051]: vector processor includes a vector register), and when the instruction is a loop-unrolled instruction, the controller is configured to store at least a portion of data associated with data processing in the LUT memory and store a remaining portion other than the at least a portion among the data associated with data processing in the vector register (see STEPHENS below).
STEPHENS discloses the following limitations that are not disclosed by CHO: when the instruction is a loop-unrolled instruction (see [0066]-[0069]: when there are contiguous vector load/store instructions that form a loop, loop unrolling can be performed), the controller is configured to store at least a portion of data associated with data processing in the LUT memory and store a remaining portion other than the at least a portion among the data associated with data processing in the vector register (see [0075]-[0076]: series of data transfers, each element in the transfer corresponding to a portion of the contiguous block of addresses). CHO already discloses storing data needed for processing in LUT memory, then having a gather unit fetch the data from LUT memory to the vector register for processing. A combination of CHO and STEPHENS would result in a series of data transfers to the LUT memory and then to the vector register when a loop unrolling is executed. Loop unrolling improves performance by enabling other optimization techniques such as software pipelining or modulo scheduling (see [0070]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify CHO to perform loop unrolling and store the data in LUT memory, as disclosed by STEPHENS. One of ordinary skill in the art would have been motivated to make such a modification to enable optimization techniques, as taught by STEPHENS. CHO and STEPHENS are analogous/in the same field of endeavor as both references are directed to vector processing.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHO (U.S. Patent Application Publication #2017/0344369) and STEPHENS (U.S. Patent Application Publication #2018/0253310) as applied to claims 1-4, 7-9, 11-13 and 15-20 above, and further in view of XIE (U.S. Patent Application Publication #2022/0051370).
Claim 14: The vector processor of claim 13, wherein when the data processing is data processing related to convolution (see CHO [0075]: a gaussian filter is a convolution), the at least a portion includes at least one of feature data and a kernel weight related to the convolution (see XIE below).
XIE discloses the following limitations that are not disclosed by CHO: the at least a portion includes at least one of feature data and a kernel weight related to the convolution (see [0036]: gaussian filtering replaces a pixel corresponding to a weight value). CHO already discloses one possible operation performed by the vector processor, which is gaussian filtering. The data fetched from the LUT memory in CHO is data used for gaussian filtering. XIE discloses the a gaussian filter uses kernel weights in the operation for determining a replacement pixel value. At least a portion of the data in memory would be kernel weights, another portion would be the pixel values. This data is necessary for a gaussian filter to function and would be obvious to store this data in memory for use by the gaussian filter, as described by XIE.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify CHO to store a kernel weight related to a convolution, as disclosed by XIE. One of ordinary skill in the art would have been motivated to make such a modification to allow the gaussian function already disclosed by CHO to operate, as taught by XIE. CHO and XIE are analogous/in the same field of endeavor as both references are directed to a gaussian filter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
TRAYLOR – 11,630,668 – discloses a vector processor that includes an ALU. See columns 3 and 4.
SHALEV – 10,915,494 – discloses storing coefficients in a lookup table that is used by a vector processor. See column 4.
DANNE – 2014/0207838 – discloses a lookup table memory used by a vector processor. See claims 8 and 15
JAKOVLIJEVIC – 2014/0149657 – discloses a lookup table for use with vector processor. See [0146]
MIMAR – 2013/0212353 – discloses a memory being used as a lookup table for vector operations. See [0008]
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2136