DETAILED ACTION
This action is responsive to 09/11/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-6, 9-10, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (US Pub. 2021/0295777), hereinafter Jeong.
Regarding claim 1, Jeong discloses a display device (see figs. 1-2), comprising: a display panel (display panel 100-see figs. 1-3) including a display area (display area DA-see fig.1) and a peripheral area surrounding at least a portion of the display area (non-display area NDA-see fig. 1); a gate driver disposed in the peripheral area (scan driver 400-see fig. 2) and including odd-numbered stages (STG1, STG3, … see fig. 5) and even-numbered stages (STG2, STG4, … see fig. 5); a first scan start signal line disposed in the peripheral area and configured to apply a first scan start signal to a first odd-numbered stage of the odd-numbered stages (start terminal ST of the first stage STG1 may receive a first start signal from a first start signal line STL1-see fig. 5 with description in [0106] and fig. 7 with description in [0118]-[0122]); a second scan start signal line disposed in the peripheral area and configured to apply a second scan start signal to a first even-numbered stage of the even-numbered stages (start terminal ST of the second stage STG2 may receive a second start signal from a second start signal line STL2-figs. 5 and 13, with description in [0138]-[0142]) after all of the odd-numbered stages are driven (when the even rows are driven, first start signal STS1 may maintain a gate high voltage during one frame. Therefore, the pixels SP arranged in odd rows may maintain a light-off state-see [0132] and [0142]); a first pixel circuit portion disposed in the display area, electrically connected to the first odd-numbered stage (a first pixel RP (red) may be connected to odd-numbered data lines-see [0069]), and connected to a first light-emitting diode that emits a first color (light emitting element E (in each pixel circuit) for a red color-see [0094] and fig. 4); and a second pixel circuit portion disposed in the display area (third pixel GP may be connected to the first scan lines (odd) or the second scan lines (even)-see [0007], [0070], and claim 1), spaced apart from the first pixel circuit portion in a first direction (GP is spaced apart from RP in a row direction (first direction)-see fig. 3), and connected to a second light-emitting diode that emits a second color different from the first color (light emitting element E (in each pixel circuit), in this case, emitting a green color (GP)-see [0094] and fig. 4).
Jeong does not appear to expressly disclose a second pixel circuit portion disposed in the display area, electrically connected to the first odd-numbered stage.
However, Jeong, in for example, [0007], [0070], and claim 1, discloses that the third pixel GP may be connected to either the first scan line or the second scan line.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to couple each third pixel GP to either an odd scan line or an even scan line, as taught by Jeong, which constitutes choosing from a finite number of identified, predictable solutions for connecting the third pixel GP to a scan line, with a reasonable expectation of success.
Regarding claim 2, Jeong discloses further comprising: a third pixel circuit portion disposed in the display area, electrically connected to the first even-numbered stage, spaced apart from the first pixel circuit portion in a second direction intersecting the first direction (second pixel BP is spaced apart from first pixel RP in a column direction (second direction), and connected to an even scan line (SL2, SL4 … see [0069] and fig. 3), and connected to a third light-emitting diode that emits a third color different from the first and second colors (light emitting element E (in each pixel circuit), in this case, emitting a blue color (BP)-see [0094] and fig. 4); and a fourth pixel circuit portion disposed in the display area, electrically connected to the first even-numbered stage, spaced apart from the third pixel circuit portion in the first direction, and connected to a fourth light-emitting diode that emits the third color (see figs. 3 and 10 and [0069]-GP at intersection of scan line SL2 and data line DL2).
Regarding claim 3, Jeong discloses wherein the odd-numbered stages are electrically connected to each other by an odd carry line, and the even-numbered stages are electrically connected to each other by an even carry line (see fig. 5).
Regarding claim 5, Jeong discloses further comprising: a first gate line disposed in the display area and extending in the first direction from the first odd-numbered stage (SL1-see fig. 5); and a second gate line disposed in the display area and extending in the first direction from the first even-numbered stage (SL2-see fig. 5).
Regarding claim 6, Jeong discloses wherein the first gate line is electrically connected to the first pixel circuit portion and the second pixel circuit portion (the first pixel RP may be connected to a first scan line SL1 (see [0069]) and the third pixel GP (second pixel) and the third pixel GP may be connected to the first scan line (odd) or the second scan lines (even)-see [0007], [0070], and claim 1 ), and the second gate line is electrically connected to the third pixel circuit portion and the fourth pixel circuit portion (SL2 is connected to both BP and GP corresponding to first and second columns-see figs. 3 and 10).
Regarding claim 9, Jeong discloses wherein the first color is red, the second color is blue, and the third color is green (RP, BP, and GP-see fig. 2).
Regarding claim 10, Jeong discloses wherein the first color is blue, the second color is red, and the third color is green (BP, RP, and GP-see fig. 2).
Regarding claim 20, Jeong discloses an electronic device, comprising: a display device (see figs. 1-2); and a processor configured to drive the display device (see [0058], [0081]-[0082]), wherein the display device includes: a display panel (display panel 100-see figs. 1-3) including a display area (display area DA-see fig.1) and a peripheral area surrounding at least a portion of the display area (non-display area NDA-see fig. 1); a gate driver disposed in the peripheral area (scan driver 400-see fig. 2) and including odd-numbered stages (STG1, STG3, … see fig. 5) and even-numbered stages (STG2, STG4, … see fig. 5); a first scan start signal line disposed in the peripheral area and configured to apply a first scan start signal to a first odd-numbered stage of the odd-numbered stages (start terminal ST of the first stage STG1 may receive a first start signal from a first start signal line STL1-see fig. 5 with description in [0106] and fig. 7 with description in [0118]-[0122]); a second scan start signal line disposed in the peripheral area and configured to apply a second scan start signal to a first even-numbered stage of the even-numbered stages (start terminal ST of the second stage STG2 may receive a second start signal from a second start signal line STL2-figs. 5 and 13, with description in [0138]-[0142]) after all of the odd-numbered stages are driven (when the even rows are driven, first start signal STS1 may maintain a gate high voltage during one frame. Therefore, the pixels SP arranged in odd rows may maintain a light-off state-see [0132] and [0142]); a first pixel circuit portion disposed in the display area, electrically connected to the first odd-numbered stage (a first pixel RP (red) may be connected to odd-numbered data lines-see [0069]), and connected to a first light-emitting diode that emits a first color (light emitting element E (in each pixel circuit) for a red color (RP)-see [0094] and fig. 4); a second pixel circuit portion disposed in the display area (third pixel GP may be connected to the first scan lines (odd) or the second scan lines (even)-see [0007], [0070], and claim 1), spaced apart from the first pixel circuit portion in a first direction (GP is spaced apart from RP in a row direction (first direction)-see fig. 3), and connected to a second light-emitting diode that emits a second color different from the first color (light emitting element E (in each pixel circuit), in this case, emitting a green color (GP)-see [0094] and fig. 4); a third pixel circuit portion disposed in the display area, electrically connected to the first even-numbered stage, spaced apart from the first pixel circuit portion in a second direction intersecting the first direction (second pixel BP is spaced apart from first pixel RP in a column direction (second direction), and connected to an even scan line (SL2, SL4 … see [0069] and fig. 3), and connected to a third light-emitting diode that emits a third color different from the first and second colors (light emitting element E (in each pixel circuit), in this case, emitting a blue color (BP)-see [0094] and fig. 4); and a fourth pixel circuit portion disposed in the display area, electrically connected to the first even-numbered stage, spaced apart from the third pixel circuit portion in the first direction, and connected to a fourth light-emitting diode that emits the third color (see figs. 3 and 10 and [0069]-GP at intersection of scan line SL2 and data line DL2).
Jeong does not appear to expressly disclose a second pixel circuit portion disposed in the display area, electrically connected to the first odd-numbered stage.
However, Jeong, in for example, [0007], [0070], and claim 1, discloses that the third pixel GP may be connected to either the first scan line or the second scan line.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to couple each third pixel GP to either an odd scan line or an even scan line, as taught by Jeong, which constitutes choosing from a finite number of identified, predictable solutions for connecting the third pixel GP to a scan line, with a reasonable expectation of success.
Claims 4, 7-8, and 11-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Seo et al. (US Pub. 2023/0290313), hereinafter Seo.
Regarding claim 4, Jeong does not appear to expressly disclose wherein the first pixel circuit portion and the third pixel circuit portion are symmetrical in a plan view about a virtual extension line extending in the first direction between the first pixel circuit portion and the third pixel circuit portion.
Seo is relied upon to teach wherein the first pixel circuit portion and the third pixel circuit portion are symmetrical in a plan view about a virtual extension line extending in the first direction between the first pixel circuit portion and the third pixel circuit portion (see fig. 6, wherein each red pixel and an adjacent blue pixel in a column direction is symmetrical about an imaginary line extending in a row direction).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Seo with the invention of Jeong such that the first pixel circuit and the third pixel circuit are symmetrical in plan view about an a virtual line extending in a row direction, as taught by Seo, in order to provide a pixel structure having excellent perceptual image quality (see [0004]).
Regarding claim 7, Seo is further relied upon to teach wherein the first, second, third, and fourth light- emitting diodes are disposed in a Pentile matrix structure (see [0005], [0065], and fig. 6).
Regarding claim 8, Seo is further relied upon to teach wherein at least a portion of the first light-emitting diode overlaps the first pixel circuit portion in a plan view, at least a portion of the second light-emitting diode overlaps the third pixel circuit portion in the plan view, at least a portion of the third light-emitting diode overlaps the second pixel circuit portion in the plan view, and at least a portion of the fourth light-emitting diode overlaps the fourth pixel circuit portion in the plan view (see fig. 6 with description in [0110]).
Regarding claim 11, Jeong discloses further comprising: a data driver disposed in the peripheral area and spaced apart from the display area in a direction opposite to the second direction (see fig. 3-data driver 220).
Jeong does not appear to expressly disclose wherein the data driver includes a first amplifier and a second amplifier spaced apart from the first amplifier in the first direction.
Seo is further relied upon to teach wherein the data driver includes a first amplifier and a second amplifier spaced apart from the first amplifier in the first direction (see figs. 4A-4B and [0088]-[0106]-data driver 12 includes a plurality of source channels (amplifiers) to drive the data lines).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Seo by including built-in buffer amplifiers in each source channel, as taught by Seo, which constitutes combining prior art elements according to known methods to yield predictable results.
Regarding claim 12, Jeong in view of Seo teaches first and second amplifiers spaced apart from each other as in claim 11, and Jeong further teaches further comprising: a first data line extending in the second direction from the first amplifier and disposed in the display area; and a second data line extending in the second direction from the second amplifier and disposed in the display area (data lines DL1 and DL2 extending from the data driver 220-see fig. 3).
Regarding claim 13, Jeong discloses wherein the first data line is electrically connected to the first pixel circuit portion and the third pixel circuit portion (first pixel RP and the second pixel BP (herein third pixel) may be connected to the first data line DL1-see fig. 3 and [0069]), and the second data line is electrically connected to the second pixel circuit portion and the fourth pixel circuit portion (the third pixels GP (herein second pixel) are connected to the second data line DL2-see fig. 3 and [0070]).
Regarding claim 14, Jeong discloses wherein the first amplifier alternately applies a first data voltage and a second data voltage to the first data line (see fig. 7 with description in [0118]-[0123]), and the second amplifier alternately applies the second data voltage and a third data voltage to the second data line (see fig. 13 with description in [0138]-[0143]).
Regarding claim 15, Jeong discloses wherein the first data voltage applied from the first amplifier is applied to the first pixel circuit portion, the second data voltage applied from the first amplifier is applied to the third pixel circuit portion (first pixel RP and second pixel BP are driving by the first data line DL1-see fig. 3 and [0069]), the second data voltage applied from the second amplifier is applied to the fourth pixel circuit portion, and the third data voltage applied from the second amplifier is applied to the second pixel circuit portion (third pixel GP at intersect of the first scan line SL1 and the second data line DL2 (equated to claimed second pixel) and third pixel GP at intersection of the second scan line SL2 and second data line DL2 (equated to claimed fourth pixel) are both supplied by the second data line DL2).
Regarding claim 16, Jeong in view of Seo teaches first and second amplifiers as in claim 11 above, and Jeong further discloses wherein the first amplifier applies the first data voltage to the first data line during a timing when the odd-numbered stages are driven, and applies the second data voltage to the first data line during a timing when the even-numbered stages are driven (see, for example, [0069], which discloses that the first pixel RP is connected to the first data line and the first scan line, and the second pixel BP is connected to the first data line and a second scan line SL2, and fig. 7 illustrate driving the odd lines while the even lines are off, and fig. 13 illustrates driving the even lines while the odd lines are turned off, i.e., the first data line DL1 supplies a first data line to the first pixel RP when the odd line SL1 is on, and supplies another data voltage to the second pixel BP (third pixel) when the even line SL2 is driven), and the second amplifier applies the third data voltage to the second data line during a timing when the odd-numbered stages are driven (i.e., the third pixel GP (second pixel), which may be connected to the first scan line SL1, is supplied a data voltage by the second data line DL2, when SL1 is turned on (as in fig. 7)), and applies the second data voltage to the second data io line during a timing when the even-numbered stages are driven (i.e., the third pixel GP, which may be connected to second scan line SL2, is supplied another data voltage by the second data line when SL2 is turned on (as in fig. 13)).
Regarding claim 17, Jeong discloses a method of driving a display device, comprising: applying a first data voltage to a first data line during a timing when odd-numbered stages are driven (i.e., a first data voltage is applied to first data line DL1 when odd-number stages are driven as in fig. 7-see [0069] and [0118]-[0122]), wherein the display device includes a display panel (display panel 100-see figs. 1-3) including a display area (display area DA-see fig.1) and a peripheral area surrounding at least a portion of the display area (non-display area NDA-see fig. 1), a gate driver disposed in the peripheral area (scan driver 400-see fig. 2) and including the odd-numbered stages (STG1, STG3, … see fig. 5) and even-numbered stages (STG2, STG4, … see fig. 5), and a data driver disposed in the peripheral area (data driver 220-see fig. 3); applying a second data voltage to the first data line during a timing when the even-numbered stages are driven (second pixel BP is connected to the first data line DL1 and a second scan line SL2, and is therefore driven with a data voltage(second data voltage) when even number data lines (specifically SL2) are driven as in fig. 13); applying a third data voltage to a second data line during a timing when the odd-numbered stages are driven (third transistor GP may be connected to the first scan line SL1 and a second data line DL2, and is driven with a data voltage (third data voltage) supplied by the second data line DL2, when odd scan lines are turned on sequentially as in fig. 7 with description in [0118]-[0122]); and applying the second data voltage to the second data line during a timing when the even-numbered stages are driven by the second amplifier (see [0070] and fig. 13 with description in [0138]-[0142]), wherein the odd-number stages are driven sequentially (see fig. 7), and the even-numbered stages are driven sequentially (see fig. 13) after all of the odd-numbered stages are driven (when the even rows are driven, first start signal STS1 may maintain a gate high voltage during one frame. Therefore, the pixels SP arranged in odd rows may maintain a light-off state-see [0132] and [0142]).
Jeong does not appear to expressly disclose the data driver including the first amplifier and a second amplifier spaced apart from the first amplifier in a first direction.
Seo is relied upon to teach wherein the data driver includes a first amplifier and a second amplifier spaced apart from the first amplifier in the first direction (see figs. 4A-4B and [0088]-[0106]-data driver 12 includes a plurality of source channels (amplifiers) to drive the data lines).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Seo by including built-in buffer amplifiers in each source channel, as taught by Seo, which constitutes combining prior art elements according to known methods to yield predictable results.
Regarding claim 18, Jeong discloses further comprising: driving a first odd-numbered stage of the odd-numbered stages using a first scan line (the start terminal ST of the first stage STG1 may receive a first start signal from the first start signal line STL1. The output terminal OUT of the first stage STG1 may be connected to the first scan line SL1-see [0106]); driving a first even-numbered stage of the even-numbered stages using a second scan line (the start terminal ST of the second stage STG2 may receive a second start signal from the second start signal line STL2. The output terminal OUT of the second stage STG2 may be connected to the second scan line SL2-see [0107]); sequentially driving the odd-numbered stages from the first odd-numbered stage to a last odd-numbered stage (see fig. 7 with description in [0118]-[0122]); and sequentially driving the even-numbered stages from the first even-numbered stage to a last even-numbered stage after the odd-numbered stages have been driven (see fig. 13 with description in [0138]-[0142]).
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The references of record fail to teach or suggest “sequentially driving the even-numbered stages from a last even-numbered stage to a first even-numbered stage, wherein a carry line extending from the last odd-numbered stage drives the last even-numbered stage of the even-numbered stages.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571)272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SARDIS F AZONGHA/ Primary Examiner, Art Unit 2627
Prosecution Insights