Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-33 are rejected under 35 U.S.C. 103 as being unpatentable over Im et al., US PGPUB 20230051015 hereinafter referenced as Im, in view of Cho et al., US PGPUB 20200185484 hereinafter referenced as Cho.
As to claim 1, Im discloses a display panel comprising: a substrate (e.g., substrate SUB, fig. 9);
insulating layers on the substrate (e.g., Insulating layers INS1-INS4, fig. 9);
signal lines between the insulating layers (e.g., signal lines SLi, fig. 5);
transistors connected to the signal lines (e.g., transistors T1-T8, fig. 5); and
a light emitting element connected to the transistors (e.g., OLED, FIG. 5),
wherein the signal lines comprise a first initialization line (e.g., initialization line VIL1, fig. 5), a bias line (e.g., bias line BIS, fig. 5), a bias scan line (e.g., bias scan signal EBSi, fig. 5), a light emitting line (e.g., emitting line ELi, fig. 5), a compensation scan line (e.g., compensation scan line GCSi, fig. 5), an initialization scan line (e.g., initialization scan signal GISi, fig. 5), a writing scan line (write scan signal GWSi, fig. 5), and a second initialization line, which extend in a first direction and are arranged in a second direction crossing the first direction (e.g., initialization line VIL2, fig. 5), and
a data line extending in the second direction (data lines DL, fig. 5), and
wherein a driving transistor among the transistors is between the compensation scan line and the initialization scan line on a plane defined by the first direction and the second direction (e.g., first transistor T1, fig. 5; wherein as shown in fig. 28E T1 is located between initialization scan line Gli and compensation scan line GCi).
Im does not disclose the first and second initialization lies are crossed each other.
However, in the same endeavor, Cho discloses first and second initialization lies are crossed each other (as shown in fig. 13, VIL2 is crossing VIL1 through CNL22).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Im, to further include Cho’s initialization lines arrangement, in order to improve the operation stability.
As to claim 21, Im discloses a display panel comprising: signal lines (e.g., signal lines SLi, fig. 5); transistors connected to the signal lines (e.g., transistors T1-T8, fig. 5); and
a light emitting element connected to the transistors (e.g., OLED, FIG. 5),
wherein the signal lines comprise a bias line (e.g., bias line BIS, fig. 5), a first initialization line (e.g., initialization line VIL1, fig. 5), a bias scan line (e.g., bias scan signal EBSi, fig. 5), a light emitting line (e.g., emitting line ELi, fig. 5), a compensation scan line (e.g., compensation scan line GCSi, fig. 5), an initialization scan line (e.g., initialization scan signal GISi, fig. 5), a writing scan line (write scan signal GWSi, fig. 5), and a second initialization line, which extend in a first direction and are arranged in a second direction crossing the first direction (e.g., initialization line VIL2, fig. 5), and
a data line extending in the second direction (data lines DL, fig. 5), and
wherein a driving transistor among the transistors is between the compensation scan line and the initialization scan line on a plane defined by the first direction and the second direction (e.g., first transistor T1, fig. 5; wherein as shown in fig. 28E T1 is located between initialization scan line Gli and compensation scan line GCi).
Im does not disclose the first and second initialization lies are crossed each other.
However, in the same endeavor, Cho discloses first and second initialization lies are crossed each other (as shown in fig. 13, VIL2 is crossing VIL1 through CNL22).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Im, to further include Cho’s initialization lines arrangement, in order to improve the operation stability.
As to claim 27, Im discloses an electronic device comprising: a window (WIN, fig. 2); and
a display panel below the window (display panel DP, fig. 2),
wherein the display panel comprises: a substrate (e.g., substrate SUB, fig. 3);
insulating layers on the substrate (e.g., Insulating layers INS1-INS4, fig. 9);
signal lines between the insulating layers (e.g., signal lines SLi, fig. 5);
transistors connected to the signal lines (e.g., transistors T1-T8, fig. 5); and
a light emitting element connected to the transistors (e.g., OLED, fig. 5),
wherein the signal lines comprise a first initialization line (e.g., initialization line VIL1, fig. 5), a bias line (e.g., bias line BIS, fig. 5), a bias scan line (e.g., bias scan signal EBSi, fig. 5), a light emitting line (e.g., emitting line ELi, fig. 5), a compensation scan line (e.g., compensation scan line GCSi, fig. 5), an initialization scan line (e.g., initialization scan signal GISi, fig. 5), a writing scan line (write scan signal GWSi, fig. 5), and a second initialization line, which extend in a first direction and are arranged in a second direction crossing the first direction (e.g., initialization line VIL2, fig. 5), and
a data line extending in the second direction (data lines DL, fig. 5), and
wherein a driving transistor among the transistors is between the compensation scan line and the initialization scan line on a plane defined by the first direction and the second direction (e.g., first transistor T1, fig. 5; wherein as shown in fig. 28E T1 is located between initialization scan line Gli and compensation scan line GCi).
Im does not disclose the first and second initialization lies are crossed each other.
However, in the same endeavor, Cho discloses first and second initialization lies are crossed each other (as shown in fig. 13, VIL2 is crossing VIL1 through CNL22).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the disclosure of Im, to further include Cho’s initialization lines arrangement, in order to improve the operation stability.
As to claim 2, the combination of Im and Cho discloses the display panel of claim 1. The combination further discloses among the transistors, a compensation transistor connected to the compensation scan line is spaced apart from a first initialization transistor connected to the initialization scan line in the second direction with the driving transistor interposed therebetween (Im, [0130] The third transistor T3 is turned on by the i-th compensation scan signal GCSi applied through the i-th compensation scan line GCi to connect (e.g., electrically connect) the second electrode of the first transistor T1 and the control electrode of the first transistor T1).
As to claim 3, the combination of Im and Cho discloses the display panel of claim 2. The combination further discloses semiconductor layers included in the compensation transistor and the first initialization transistor comprise a metal oxide, and semiconductor layers included in remaining transistors of the transistors comprise polysilicon (Im, [0170] A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, amorphous silicon, or metal oxide).
As to claim 4, the combination of Im and Cho discloses the display panel of claim 3. The combination further discloses the semiconductor layers comprising the metal oxide and the semiconductor layers comprising the polysilicon are different layers (Im, [0170] A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, amorphous silicon, or metal oxide).
As to claim 5, the combination of Im and Cho discloses the display panel of claim 4. The combination further discloses a gate pattern connecting the driving transistor and the compensation transistor, wherein the gate pattern is on a same layer as the first initialization line (Im, [0196] The first gate pattern GPT1 may include first to fourth gate electrodes G1 to G4, seventh and eighth gate electrodes G7 and G8, and an emission line ELi).
As to claim 6, the combination of Im and Cho discloses the display panel of claim 5. The combination further discloses the gate pattern does not overlap, on the plane, the initialization scan line, the compensation scan line, and the writing scan line (e.g. the arrangement of compensation scan line (Im, e.g., compensation scan line GCSi, fig. 5), an initialization scan line (e.g., initialization scan signal GISi, fig. 5), a writing scan line (write scan signal GWSi, fig. 5).
As to claim 7, the combination of Im and Cho discloses the display panel of claim 5. The combination further discloses on the plane, the gate pattern does not overlap the initialization scan line and the writing scan line, and a portion of the gate pattern overlaps the compensation scan line (e.g. the arrangement of compensation scan line (Im, e.g., compensation scan line GCSi, fig. 5), an initialization scan line (e.g., initialization scan signal GISi, fig. 5), a writing scan line (write scan signal GWSi, fig. 5).
As to claim 8, the combination of Im and Cho discloses the display panel of claim 5. The combination further discloses the insulating layers comprise a buffer layer and first to seventh insulating layers that are sequentially laminated, and wherein the display panel further comprises: a first conductive layer on the buffer layer and covered by the first insulating layer; a second conductive layer on the first insulating layer and covered by a second insulating layer; a third conductive layer on the second insulating layer and covered by a third insulating layer; a fourth conductive layer on the third insulating layer and covered by a fourth insulating layer; a fifth conductive layer on the fourth insulating layer and covered by a fifth insulating layer; a sixth conductive layer on the fifth insulating layer and covered by a sixth insulating layer; and a seventh conductive layer on the sixth insulating layer and covered by the seventh insulating layer (Im, [0177] A fifth insulating layer INS5 may be disposed on the second connection electrode CNE2. The fifth insulating layer INS5 may be defined as a second planarization insulating layer. A layer from the buffer layer BFL to the fifth insulating layer INS5 may be defined as a circuit element layer DP-CL. The first to third insulating layers INS1 to INS3 may be inorganic layers. The fourth and fifth insulating layers INS4 and INS5 may be organic layers).
As to claim 9, the combination of Im and Cho discloses the display panel of claim 8. The combination further discloses the semiconductor layers comprising the polysilicon are included in the first conductive layer (Im, [0170] A buffer layer BFL may be disposed on the substrate SUB, and may be an inorganic layer. A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, amorphous silicon, or metal oxide).
As to claim 10, the combination of Im and Cho discloses the display panel of claim 9. The combination further discloses the bias scan line, the light emitting line, the writing scan line, and a gate electrode included in the driving transistor are included in the second conductive layer (Im, [0325] Referring to FIGS. 26, 28B, 28C, 28D, and 28E, a second connection pattern CNP2 may be disposed on the first connection pattern CNP1. The second connection pattern CNP2 may include a second connection electrode CNE2, a first power line PL1, a data line DLj, a reference voltage line VL, and a first initialization line VIL1. The second connection pattern CNP2 may be defined as a second conductive pattern).
As to claim 11, the combination of Im and Cho discloses the display panel of claim 10. The combination further discloses each of the compensation scan line and the initialization scan line comprises a lower layer and an upper layer, wherein a dummy electrode included in the lower layer of the compensation scan line, the lower layer of the initialization scan line, and the driving transistor is included in the third conductive layer, the dummy electrode overlapping the gate electrode in a third direction crossing the first direction and the second direction, and wherein an opening, through which the gate electrode is exposed, is defined in the dummy electrode ([0201] When viewed in a plan view, the dummy electrode DME may partially overlap the first gate electrode G1. An opening OP may be defined in the dummy electrode DME. The capacitor Cst may be formed by the dummy electrode DME and the first gate electrode G1 overlapping each other).
As to claim 12, the combination of Im and Cho discloses the display panel of claim 11. The combination further discloses the semiconductor layers comprising the metal oxide are included in the fourth conductive layer (Im, [0170] A buffer layer BFL may be disposed on the substrate SUB, and may be an inorganic layer. A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, amorphous silicon, or metal oxide).
As to claim 13, the combination of Im and Cho discloses the display panel of claim 12. The combination further discloses the bias line, the upper layer of the compensation scan line, the upper layer of the initialization scan line, and the second initialization line are included in the fifth conductive layer (Im, [0213] The bias scan line EBi may be connected to the eighth gate electrode G8 of the eighth transistor T8 and the seventh gate electrode G7 of the seventh transistor T7 through the first contact hole CH1_9. The bias line BIS may be connected to the eighth source electrode S8 of the eighth transistor T8 through the first contact hole CH1_10).
As to claim 14, the combination of Im and Cho discloses the display panel of claim 13. The combination further discloses the first initialization line and the gate pattern are included in the sixth conductive layer (Im, [0027] The driving unit may include a plurality of elements at a same layer as the first to the fourth transistors).
As to claim 15, the combination of Im and Cho discloses the display panel of claim 14. The combination further discloses the data line is included in the seventh conductive layer (Im, DL1-DLn, fig. 4).
As to claim 16, the combination of Im and Cho discloses the display panel of claim 15. The combination further discloses a first power line configured to provide a first power voltage to the driving transistor, wherein the first power line comprises a lower line included in the sixth conductive layer and extending in the first direction and an upper line included in the seventh conductive layer, extending in the second direction, and connected to the lower line through a contact hole defined in the sixth insulating layer (Im, [0227] the light blocking patterns SP may not overlap (e.g., may not overlap in the thickness direction of the display device DD) the first and second conductive patterns defined by the source electrodes S1 to S8, the drain electrodes D1 to D8, the active areas A1 to A8, the gate electrodes G1 to G8, and the first and second connection patterns CNP1 and CNP2).
As to claim 17, the combination of Im and Cho discloses the display panel of claim 16. The combination further discloses the lower line is connected to the dummy electrode through a contact hole penetrating the third insulating layer, the fourth insulating layer, and the fifth insulating layer (Im, [0306] In a plan view, the first to ninth gate electrodes G1 to G9 may overlap the first to ninth active areas Al to A9, respectively. The dummy electrode DME′ may be disposed between the first, third, fourth, and sixth to ninth transistors T1, T3, T4, T6 to T9 and the second and fifth transistors T2 and T5).
As to claim 18, the combination of Im and Cho discloses the display panel of claim 14. The combination further discloses one end portion of the gate pattern is connected to the gate electrode included in the driving transistor through a first contact hole, the first contact hole overlapping the opening and penetrating the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer, and wherein an opposite end portion of the gate pattern is connected to a semiconductor layer comprising the metal oxide through a second contact hole penetrating the fourth insulating layer and the fifth insulating layer (Im, [0308] Referring to FIGS. 26, 28B, and 28C, a second gate pattern GPT2 may be disposed on the first gate pattern GPT1. The second gate pattern GPT2 may include first, second, third, and fourth dummy electrodes DME1, DME2, DME3, and DME4).
As to claim 19, the combination of Im and Cho discloses the display panel of claim 14. The combination further discloses a first sub-line included in the sixth conductive layer and extending in the first direction; and a second sub-line included in the seventh conductive layer, connected to the first sub- line through a contact hole defined in the sixth insulating layer, and extending in the second direction, wherein the second sub-line is connected to the data line (Im, [0322] The first sub initialization line VIL1′ may be connected to the fourth drain electrode D4 of the fourth transistor T4 through the first contact hole CH1_12).
As to claim 20, the combination of Im and Cho discloses the display panel of claim 1. The combination further discloses the light emitting element comprises a first electrode connected to the driving transistor, a second electrode on the first electrode, and a light emitting layer between the first electrode and the second electrode (Im, [0028] In an embodiment of the present disclosure, a display device includes: a light emitting element including an anode, a cathode, and a light emitting layer between the anode and the cathode).
As to claim 22, the combination of Im and Cho discloses the display panel of claim 21. The combination further discloses on the plane, the bias line is above the first initialization line, and wherein the bias scan line is below the first initialization line (Im, [0137] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line EBi).
As to claim 23, the combination of Im and Cho discloses the display panel of claim 22. The combination further discloses on the plane, the writing scan line is below the initialization scan line, and the second initialization line is below the writing scan line (Im, [0144] After the i-th initialization scan signal GISi is activated, the i-th write scan signal GWSi and the i-th compensation scan signal GCSi may be activated).
As to claim 24, the combination of Im and Cho discloses the display panel of claim 23. The combination further discloses on the plane, the second initialization line is below the initialization scan line, and the writing scan line is below the second initialization line (Im, [0137] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line EBi).
As to claim 25, the combination of Im and Cho discloses the display panel of claim 21. The combination further discloses on the plane, the first initialization line is above the bias line, and wherein the bias scan line is below the bias line (Im, [0213] The bias scan line EBi may be connected to the eighth gate electrode G8 of the eighth transistor T8 and the seventh gate electrode G7 of the seventh transistor T7 through the first contact hole CH1_9. The bias line BIS may be connected to the eighth source electrode S8 of the eighth transistor T8 through the first contact hole CH1_10).
As to claim 26, the combination of Im and Cho discloses the display panel of claim 25. The combination further discloses on the plane, the second initialization line is below the initialization scan line, and the writing scan line is below the second initialization line (Im, [0137] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line EBi).
As to claim 28, the combination of Im and Cho discloses the electronic device of claim 27. The combination further discloses among the transistors, a compensation transistor connected to the compensation scan line is spaced apart from a first initialization transistor connected to the initialization scan line in the second direction with the driving transistor interposed therebetween (Im, [0130] The third transistor T3 is turned on by the i-th compensation scan signal GCSi applied through the i-th compensation scan line GCi to connect (e.g., electrically connect) the second electrode of the first transistor T1 and the control electrode of the first transistor T1).
As to claim 29, the combination of Im and Cho discloses the electronic device of claim 28. The combination further discloses semiconductor layers included in the compensation transistor and the first initialization transistor comprise a metal oxide, and semiconductor layers included in remaining transistors of the transistors comprise polysilicon (Im, [0170] A buffer layer BFL may be disposed on the substrate SUB, and may be an inorganic layer. A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, amorphous silicon, or metal oxide).
As to claim 30, the combination of Im and Cho discloses the electronic device of claim 29. The combination further discloses the semiconductor layers comprising the metal oxide and the semiconductor layers comprising the polysilicon are different layers (Im, [0170] A buffer layer BFL may be disposed on the substrate SUB, and may be an inorganic layer. A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, amorphous silicon, or metal oxide) .
As to claim 31, the combination of Im and Cho discloses the electronic device of claim 30. The combination further discloses a gate pattern connecting the driving transistor and the compensation transistor, wherein the gate pattern is on a same layer as the first initialization line (Im, [0308] Referring to FIGS. 26, 28B, and 28C, a second gate pattern GPT2 may be disposed on the first gate pattern GPT1. The second gate pattern GPT2 may include first, second, third, and fourth dummy electrodes DME1, DME2, DME3, and DME4).
As to claim 32, the combination of Im and Cho discloses the electronic device of claim 31. The combination further discloses the gate pattern does not overlap, on the plane, the initialization scan line, the compensation scan line, and the writing scan line (Im, [0308] Referring to FIGS. 26, 28B, and 28C, a second gate pattern GPT2 may be disposed on the first gate pattern GPT1. The second gate pattern GPT2 may include first, second, third, and fourth dummy electrodes DME1, DME2, DME3, and DME4).
As to claim 33, the combination of Im and Cho discloses the electronic device of claim 31. The combination further discloses on the plane, the gate pattern does not overlap the initialization scan line and the writing scan line, and a portion of the gate pattern overlaps the compensation scan line (Im, [0308] Referring to FIGS. 26, 28B, and 28C, a second gate pattern GPT2 may be disposed on the first gate pattern GPT1. The second gate pattern GPT2 may include first, second, third, and fourth dummy electrodes DME1, DME2, DME3, and DME4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al., US PGPUB 20200243016 discloses a display device driven in one of a first mode and a second mode includes a first pixel area which includes first pixels, a second pixel area which includes the second pixels, a first boundary area which is included in the second pixel area and to be positioned between boundary portions of the first pixel area and the second pixel area, and a luminance controller which controls first boundary data corresponding to the first boundary area so that luminance of the first boundary area is gradually changed corresponding to a first data signal applied to the first pixels and the second pixels when the display device is driven in the second mode.
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/SAHLU OKEBATO/Primary Examiner, Art Unit 2625
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