Detailed Action
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claim 20 is rejected under 35 U.S.C. 112(b) (pre-AIA 35 U.S.C. 112, second paragraph), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 20 recites the limitations “…the output carry signal has a first swing range between the first high power voltage and the low power voltage …… a signal of a second control node and a signal of a third control node in response to a second high power voltage, which is greater than the first high power voltage, and the low power voltage, such that the signal of the second control node and the signal of the third control node each have a second swing range between the first high power voltage and the low power voltage, the second swing range being greater than the first swing range ……” The limitations recited in claim 20 are contradictory to each other. Specifically, if both the first swing range and the second swing range are between the first high power voltage and the low power voltage, the first swing range should be same as or equal to the second swing range.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 19-20 are rejected under 35 U.S.C. 103 as unpatentable over NOH (US 20260162616 A1) in view of NAKAJIMA (US 6664943 B1).
Regarding claim 19, NOH discloses a driver (Fig. 2; gate driver) comprising: a first stage and a second stage connected in series (Fig. 2; e.g., a first stage ST(n) and a second stage ST(n+1) connected in series), each of the first and second stages (e.g., Fig. 12) comprising: an input circuit (input circuit INC) configured to transmit a previous carry signal (previous carry signal C(n-1)) to a first control node (node Q(n)) in response to a clock signal (clock signal CLK1); a carry output circuit (circuit comprising transistors M05 and M06) configured to generate a present carry signal (present carry signal C(n)) based on a first high power voltage (high voltage GVDD1) and a low power voltage (low voltage GVSS1) in response to a signal of the first control node (node Q(n)); a level shifter (circuit comprising transistors M01-M04) configured to generate a signal of a second control node (signal of node N1) and a signal of a third control node (signal of node N2) in response to a second high power voltage (high voltage GVDD0), and the low power voltage (low voltage GVSS0 have a same voltage level as GVSS1; [0136]); and an output circuit (circuit comprising transistors M01-M04) configured to generate an output signal (output signal OUT(n) or OUTB(n)) based on the second high power voltage (high voltage GVDD0) and the low power voltage (low voltage GVSS0), wherein the output circuit (circuit comprising transistors M01-M04) of the first stage is configured to generate the output signal (output signal OUT(n)) in response to the signal of the second control node (signal of node N1), wherein the input circuit (input circuit INC) of the second stage (second stage ST(n+1)) is configured to receive the present carry signal (carry signal C(n)) of the first stage (first stage ST(n)), and wherein the output circuit (circuit comprising transistors M01-M04) of the second stage is configured to generate the output signal (output signal OUTB(n)) in response to the signal of the third control node (signal of node N2).
NOH discloses the first high power voltage (high voltage GVDD1) and the second high power voltage (high voltage GVDD0), and the first high power voltage GVDD1 is different from the second high power voltage GVDD0 ([0136]). NOH does not disclose the second high power voltage GVDD0 is greater than the first high power voltage GVDD1. However, NAKAJIMA discloses a circuit (e.g., Figs. 12 and 30) similar to that disclosed by NOH, wherein the second high power voltage VDD2 is greater than the first high power voltage VDD1 (col. 28, lines 24-25 and col. 29, lines 42-43; VDD2>VDD1). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from NAKAJIMA to the gate driver of NOH to generate a gate signal with a higher voltage level.
Regarding claim 20, NOH discloses a driver (Fig. 2; gate driver) comprising: an input circuit (input circuit INC) configured to transmit an input carry signal (previous carry signal C(n-1)) to a first control node (node Q(n)) in response to a clock signal (clock signal CLK1); a carry output circuit (circuit comprising transistors M05 and M06) configured to generate an output carry signal (carry signal C(n)) based on a first high power voltage (high voltage GVDD1) and a low power voltage (low voltage GVSS1) in response to a signal of the first control node (node Q(n)) such that the output carry signal (carry signal C(n)) has a first swing range between the first high power voltage (high voltage GVDD1) and the low power voltage (low voltage GVSS1); a level shifter (circuit comprising transistors M01-M04) configured to generate a signal of a second control node (signal of node N1) and a signal of a third control node (signal of node N2) in response to a second high power voltage (high voltage GVDD0), and the low power voltage (low voltage GVSS0 have a same voltage level as GVSS1; [0136]), such that the signal of the second control node (signal of node N1) and the signal of the third control node (signal of node N2) each have a second swing range between the first high power voltage (high voltage GVDD0) and the low power voltage (low voltage GVSS0), and an output circuit (circuit comprising transistors M01-M04) configured to generate an output signal (output signal OUT(n) or OUTB(n)) based on the second high power voltage (high voltage GVDD0) and the low power voltage (low voltage GVSS0)in response to the signal of the second control node (signal of node N1) or the signal of the third control node (signal of node N2) such that the output signal has the second swing range (swing range between the high voltage GVDD0 and the low power voltage GVSS0).
NOH discloses the first high power voltage (high voltage GVDD1) and the second high power voltage (high voltage GVDD0), and the first high power voltage GVDD1 is different from the second high power voltage GVDD0 ([0136]). NOH does not disclose the second high power voltage GVDD0 is greater than the first high power voltage GVDD1. However, NAKAJIMA discloses a circuit (e.g., Figs. 12 and 30) similar to that disclosed by NOH, wherein the second high power voltage VDD2 is greater than the first high power voltage VDD1 (col. 28, lines 24-25 and col. 29, lines 42-43; VDD2>VDD1). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from NAKAJIMA to the gate driver of NOH to generate a gate signal with a higher voltage level.
7. Claims 1-9 and 17-18 are rejected under 35 U.S.C. 103 as unpatentable over NOH (US 20260162616 A1) in view of NAKAJIMA (US 6664943 B1) and further in view of BONG (US 20260141864 A1) or IN (US 20230377523 A1).
Regarding claim 1, NOH discloses a driver (Fig. 2; gate driver)) comprising a stage (one stage ST) which comprises: an input circuit (input circuit INC) configured to transmit a previous carry signal (previous carry signal C(n-1)) to a first control node (node Q(n)) in response to a clock signal (clock signal CLK1); a carry output circuit (circuit comprising transistors M05 and M06) configured to generate a present carry signal (carry signal C(n)) based on a first high power voltage (high voltage GVDD1) and a low power voltage (low voltage GVSS1) in response to a signal of the first control node (node Q(n)); a level shifter (circuit comprising transistors M01-M04) configured to generate a signal of a second control node (signal of node N1) and a signal of a third control node (signal of node N2) in response to a second high power voltage (high voltage GVDD0), and the low power voltage (low voltage GVSS0 have a same voltage level as GVSS1; [0136]); and an output circuit (circuit comprising transistors M01-M04) (circuit comprising transistors M01-M04) configured to generate an output signal (output signal OUT(n) or OUTB(n)) based on the second high power voltage (high voltage GVDD0) and the low power voltage (low voltage GVSS0) in response to the signal of the second control node (signal of node N1) or the signal of the third control node (signal of node N2).
NOH discloses the first high power voltage (high voltage GVDD1) and the second high power voltage (high voltage GVDD0), and the first high power voltage GVDD1 is different from the second high power voltage GVDD0 ([0136]). NOH does not disclose the second high power voltage GVDD0 is greater than the first high power voltage GVDD1. However, NAKAJIMA discloses a circuit (e.g., Figs. 12 and 30) similar to that disclosed by NOH, wherein the second high power voltage VDD2 is greater than the first high power voltage VDD1 (col. 28, lines 24-25 and col. 29, lines 42-43; VDD2>VDD1). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from NAKAJIMA to the gate driver of NOH to generate a gate signal with a higher voltage level.
NOH discloses an input circuit (input circuit INC) configured to transmit a previous carry signal (previous carry signal C(n-1)) to a first control node (node Q(n)) in response to a clock signal (clock signal CLK1) but does not disclose in response to a first clock signal (clock signal CLK1) and a second clock signal. However, BONG discloses a gate driver and a stage of the gate driver (Fig. 7) comprising comprises: an input circuit (input circuit comprising transistors Ts3 and Ts4) configured to transmit a previous carry signal (previous carry signal SC1(n-1)) to a first control node (node Q2) in response to a first clock signal (clock signal SCLK1) and a second clock signal (clock signal SCLKB1) having a phase different from a phase of the first clock signal (e.g., Fig. 8; clock signal SCLK1 and clock signal SCLKB1 have different phases). As another reference, IN discloses a gate driver and a stage of the gate driver (Fig. 13) comprising comprises: an input circuit (input circuit 231) configured to transmit a previous carry signal (previous carry signal CR[k-1]) to a first control node (node QB) in response to a first clock signal (clock signal CLK1) and a second clock signal (clock signal CLK2) having a phase different from a phase of the first clock signal (e.g., Fig. 14; clock signal CLK1 and clock signal CLK2 have different phases). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to combine the teaching from BONG or IN with NOH and NAKAJIMA, which would provide an input circuit to control and transmit a carry signal between adjacent two stages of a gate driver, which is capable of generating a gate signal with a higher voltage level.
Regarding claim 2, NOH in view of NAKAJIMA and further in view of BONG or IN discloses the driver of claim 1, NOH discloses wherein the driver comprises a plurality of the stages comprising at least one odd-numbered stage and at least one even-numbered stage connected in series (Fig. 2; e.g., a first stage ST(n) and a second stage ST(n+1) connected in series), wherein, based on the stage being an odd-numbered stage among the plurality of the stages connected in series, the output circuit is configured to output the output signal in response to the signal of the second control node (output signal OUT(n) based on the second node N1), and wherein, based on the stage being an even-numbered stage, the output circuit is configured to output the output signal in response to the signal of the third control node (output signal OUTB(n) based on the third node N2). In addition, IN (e.g., Figs. 3 and 13-14) discloses similar features as claimed.
Regarding claim 3, NOH in view of NAKAJIMA and further in view of BONG or IN discloses the driver of claim 2, NOH discloses wherein, based on the stage being the odd-numbered stage, a phase of the present carry signal is opposite to a phase of the output signal, and wherein, based on the stage being the even-numbered stage, a phase of the present carry signal is substantially the same as a phase of the output signal (Fig. 14; phase of present carry signal C(n) and output signals OUT(n) and OUTB(n)). In addition, IN (e.g., Figs. 3 and 13-14) discloses similar features as claimed.
Regarding claim 4, NOH in view of NAKAJIMA and further in view of BONG or IN discloses the driver of claim 2, NOH discloses wherein, based on the stage being the odd-numbered stage, a phase of the signal of the first control node is substantially the same as the phase of the output signal, and wherein, based on the stage being the even-numbered stage, a phase of the signal of the first control node is opposite to the phase of the output signal (Fig. 14; phase of signal of control node Q(n) and output signals OUT(n) and OUTB(n)). In addition, IN (e.g., Figs. 3 and 13-14) discloses similar features as claimed.
Regarding claim 5, NOH in view of NAKAJIMA and further in view of BONG or IN discloses the driver of claim 1, IN discloses wherein each of a high level of the previous carry signal, a high level of the present carry signal, a high level of the first clock signal, and a high level of the second clock signal is the first high power voltage (Fig. 14; previous carry signal CR[k-1], a high level of the present carry signal CR[k], first clock signal CLK1, and second clock signal CLK2 have high power voltage VGH), wherein each of a low level of the previous carry signal, a low level of the present carry signal, a low level of the first clock signal, and a low level of the second clock signal is the low power voltage (Fig. 14; previous carry signal CR[k-1], a high level of the present carry signal CR[k], first clock signal CLK1, and second clock signal CLK2 have low power voltage VGL), HOH discloses wherein a high level of the output signal is the second high power voltage, and wherein a low level of the output signal is the low power voltage (Fig. 13; high voltage GVDD0 and low voltage GVSS0). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to combine the teaching from IN with NOH and NAKAJIMA for the same reason above.
Regarding claim 6, NOH in view of NAKAJIMA and further in view of BONG or IN discloses the driver of claim 5, wherein a high level of the signal of the first control node is the first high power voltage, and wherein a low level of the signal of the first control node is the low power voltage (high voltage VGH or GVDD1 and low voltage VHL or GVSS1).
Regarding claim 7, NOH in view of NAKAJIMA and further in view of BONG or IN discloses the driver of claim 5, NOH discloses wherein each of a high level of the signal of the second control node and a high level of the signal of the third control node is the second high power voltage (high voltage GVDD0 at node N1 and node N2), and wherein each of a low level of the signal of the second control node and a low level of the signal of the third control node is the low power voltage (low voltage GVSS0 at node N1 and node N2).
Regarding claim 8, NOH in view of NAKAJIMA and further in view of BONG on IN discloses the driver of claim 1, BONG (Fig. 7) discloses wherein the input circuit comprises: a first transistor (transistor Ts4) comprising a control electrode configured to receive the first clock signal (clock signal SCLK1), a first electrode configured to receive the previous carry signal (previous carry signal SC1(n-1)), and a second electrode connected to the first control node (node Q2); and a second transistor (transistor Ts3) comprising a control electrode configured to receive the second clock signal (clock signal SCLKB1), a first electrode configured to receive the previous carry signal (previous carry signal SC1(n-1)), and a second electrode connected to the first control node (node Q2).
Regarding claim 9, NOH in view of NAKAJIMA and further in view of BONG on IN discloses the driver of claim 1, IN (Fig. 13) discloses wherein the carry output circuit comprises: a first transistor (transistor T10) comprising a control electrode connected to the first control node (node QB), a first electrode configured to receive the first high power voltage (high voltage VGH) and a second electrode connected to a carry output node (carry output node CR[k]); and a second transistor (transistor T11) comprising a control electrode connected to the first control node (node QB), a first electrode configured to receive the low power voltage (low voltage VGL) and a second electrode connected to the carry output node (carry output node CR[k]).
Regarding claim 17, NOH in view of NAKAJIMA and further in view of BONG or IN discloses a display apparatus. NOH discloses the display apparatus comprising: a display panel comprising a pixel (Fig. 1; display panel 100 comprising pixels 101); a gate driver configured to output a gate signal to the pixel (Fig. 1; gate driver 120); a data driver configured to output a data voltage to the pixel (Fig. 1; data driver 110); and an emission driver configured to output an emission signal to the pixel (Figs. 1 and 16-17; gate driver 120 acts as an emission driver), wherein at least one of the gate driver and the emission driver comprises the stage (Figs. 3 and 12) of claim 1.
Regarding claim 18, NOH in view of NAKAJIMA and further in view of BONG or IN discloses an electronic device. NOH discloses an electronic apparatus comprising: a display panel comprising a pixel (Fig. 1; display panel 100 comprising pixels 101); a gate driver configured to output a gate signal to the pixel (Fig. 1; gate driver 120); a data driver configured to output a data voltage to the pixel (Fig. 1; data driver 110); an emission driver configured to output an emission signal to the pixel (Figs. 1 and 16-17; gate driver 120 acts as an emission driver); a driving controller (Fig. 1; controller 130) configured to control the gate driver, the data driver and the emission driver (Fig. 1); and a processor (Fig. 1; host system 200; [0079]) configured to output input image data and an input control signal to the driving controller, wherein at least one of the gate driver and the emission driver comprises the stage (Fig. 2) of claim 1.
Allowable Subject Matter
8. Claims 10-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The present invention is directed to a gate driver of a display device. The closet prior arts, NOH (US 20260162616 A1), NAKAJIMA (US 6664943 B1) BONG (US 20260141864 A1), and IN (US 20230377523 A1), individually or in combination, discloses a gate driver of a display device. The gate driver comprising a stage which comprises: an input circuit configured to transmit a previous carry signal to a first control node in response to a first clock signal and a second clock signal having a phase different from a phase of the first clock signal; a carry output circuit configured to generate a present carry signal based on a first high power voltage and a low power voltage in response to a signal of the first control node; a level shifter configured to generate a signal of a second control node and a signal of a third control node in response to a second high power voltage, which is greater than the first high power voltage, and the low power voltage; and an output circuit configured to generate an output signal based on the second high power voltage and the low power voltage in response to the signal of the second control node or the signal of the third control node, but fails to teach wherein the carry output circuit further comprises: a capacitor comprising a first electrode configured to receive the first high power voltage and a second electrode connected to the first control node, and wherein the carry output circuit further comprises: a capacitor comprising a first electrode configured to receive the second high power voltage and a second electrode connected to the first control node. In addition, the closet prior arts fail to teach wherein the level shifter comprises: a first transistor comprising a control electrode connected to the second control node, a first electrode configured to receive the second high power voltage and a second electrode connected to a first intermediate node; a second transistor comprising a control electrode connected to the carry output node, a first electrode connected to the first intermediate node and a second electrode connected to the third control node; a third transistor comprising a control electrode connected to the carry output node, a first electrode configured to receive the low power voltage and a second electrode connected to the third control node; a fourth transistor comprising a control electrode connected to the third control node, a first electrode configured to receive the second high power voltage and a second electrode connected to a second intermediate node; a fifth transistor comprising a control electrode connected to the first control node, a first electrode connected to the second intermediate node and a second electrode connected to the second control node; and a sixth transistor comprising a control electrode connected to the first control node, a first electrode configured to receive the low power voltage and a second electrode connected to the second control node. Furthermore, the closet prior art fail to teach wherein, based on the stage being an odd-numbered stage, the odd-numbered stage comprises: a first transistor comprising a control electrode configured to receive the first clock signal, a first electrode configured to receive the previous carry signal and a second electrode connected to the first control node; a second transistor comprising a control electrode configured to receive the second clock signal, a first electrode configured to receive the previous carry signal and a second electrode connected to the first control node; a third transistor comprising a control electrode connected to the first control node, a first electrode configured to receive the first high power voltage and a second electrode connected to a carry output node; a fourth transistor comprising a control electrode connected to the first control node, a first electrode configured to receive the low power voltage and a second electrode connected to the carry output node; a fifth transistor comprising a control electrode connected to the second control node, a first electrode configured to receive the second high power voltage and a second electrode connected to a first intermediate node; a sixth transistor comprising a control electrode connected to the carry output node, a first electrode connected to the first intermediate node and a second electrode connected to the third control node; a seventh transistor comprising a control electrode connected to the carry output node, a first electrode configured to receive the low power voltage and a second electrode connected to the third control node; an eighth transistor comprising a control electrode connected to the third control node, a first electrode configured to receive the second high power voltage and a second electrode connected to a second intermediate node; a ninth transistor comprising a control electrode connected to the first control node, a first electrode connected to the second intermediate node and a second electrode connected to the second control node; a tenth transistor comprising a control electrode connected to the first control node, a first electrode configured to receive the low power voltage and a second electrode connected to the second control node; an eleventh transistor comprising a control electrode connected to the second control node, a first electrode configured to receive the second high power voltage and a second electrode connected to an output node; and a twelfth transistor comprising a control electrode connected to the second control node, a first electrode configured to receive the low power voltage and a second electrode connected to the output node, wherein the first transistor, the third transistor, the fifth transistor, the sixth transistor, the eighth transistor, the ninth transistor and the eleventh transistor of the odd-numbered stage are P-type transistors, respectively, and wherein the second transistor, the fourth transistor, the seventh transistor, the tenth transistor and the twelfth transistor of the odd-numbered stage are N-type transistors, respectively.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
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