DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Priority
2. Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 09/22/2025 is being considered by the Examiner.
Disposition of the Claims
4. The instant application was effectively filed on November 19, 2024, wherein claims 1, 3, 4, 6, 10-12, 15-18 and 20 are currently pending and claims 2, 5, 7-9, 13-14 and 19 are withdrawn from consideration without traverse as drawn to non-elected species (see response to election/restriction requirement dated 06/18/2026).
Claim Objections
Claim 20 is objected to because of the following informalities: claim 20 recites “A control circuit comprising: an input transistor; an output transistor; a holding capacitor; a first terminal; a second terminal; a third terminal; a fourth terminal; and an output terminal, wherein one conduction terminal of the output transistor is connected to the first terminal, the other conduction terminal is connected to the output terminal, one conduction terminal of the input transistor is connected to the second terminal, the other conduction terminal is connected to a control terminal of the output transistor, the control terminal is connected to the third terminal, one electrode of the holding capacitor is connected to a control terminal of the output transistor, the other electrode is connected to the output terminal, and the control circuit further includes an inspection circuit element connected to the output terminal and the fourth terminal” for clarity purposes Examiner suggests amending claim 20 as follows:
A control circuit comprising: an input transistor; an output transistor; a holding capacitor; a first terminal; a second terminal; a third terminal; a fourth terminal; and an output terminal, wherein one conduction terminal of the output transistor is connected to the first terminal, the other conduction terminal of the output transistor is connected to the output terminal, one conduction terminal of the input transistor is connected to the second terminal, the other conduction terminal of the input transistor is connected to a control terminal of the output transistor, the control terminal of the output transistor is connected to the third terminal, one electrode of the holding capacitor is connected to a control terminal of the output transistor, the other electrode of the holding capacitor is connected to the output terminal, and the control circuit further includes an inspection circuit element connected to the output terminal and the fourth terminal.
. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation “the element electrode” There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 6, 10-11 and 16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jung et al. US PG-PUB 20250259577 A1 (hereinafter Jung).
Regarding claim 1, Jung teaches A circuit substrate (See Fig. 5) comprising: a control circuit including an input transistor (Fig. 5; transistor 11), an output transistor (Fig. 5; transistor 12), and an output node (Fig. 5; anode pad 121-2), wherein one conduction terminal of the input transistor is connected to a control terminal of the output transistor (Fig. 5; transistor 11 is connected to gate of transistor 12), one conduction terminal of the output transistor is connected to the output node (Fig. 5; one of the electrodes of transistor 12 is connected to the anode pads 121-2 via connection wiring 51), and the circuit substrate further includes an inspection circuit element connected to the output node (See Fig. 5; test transistor 131 with inspection device 200 connected to anode pad 121-2 via connection wiring 52).
Regarding claim 3, Jung teaches The circuit substrate according to claim 1, Jung further teaches wherein the control circuit includes a detection terminal (Fig. 5 and Para. [0055]; inspection device), one electrode of the inspection circuit element is connected to the output node (See Fig. 5; test transistor 131 with inspection device 200 connected to anode pad 121-2 via connection wiring 52), and the other electrode of the inspection circuit element is connected to the detection terminal (Fig. 5; connected to detection wiring unto inspection device 200).
Regarding claim 4, Jung teaches The circuit substrate according to claim 1, Jung further teaches wherein the control circuit includes a control circuit group provided in an array (See Fig. 1).
Regarding claim 6, Jung teaches The circuit substrate according to claim 3, Jung teaches further comprising: a plurality of data wiring lines (See Fig. 1 and Para. [0061]; data lines data(n)); a plurality of scanning wiring lines (See Fig. 1 and Para. [0061]; scan lines scan(n)); and a plurality of power source wiring lines (Fig. 1; each pixel circuit is connected to Vdd), wherein the other conduction terminal of the input transistor is connected to any one of the plurality of data wiring lines (Fig. 5; transistor 11 has an electrode connected to data line), a control terminal of the input transistor is connected to any one of the plurality of scanning wiring lines (Fig. 5 and Para. [0095]; the display panel 100 may apply a gate signal to a gate terminal of a transistor 11 of the pixel circuit 111 to turn on the transistor 11), the other conduction terminal of the output transistor is connected to any one of the plurality of power source wiring lines (Fig. 5; other electrode of transistor 12 is connected to Vdd).
Regarding claim 10, Jung teaches The circuit substrate according to claim 3, Jung teaches further comprising: a plurality of data wiring lines (See Fig. 1 and Para. [0061]; data lines data(n)); a plurality of scanning wiring lines See Fig. 1 and Para. [0061]; scan lines scan(n)), a plurality of power source wiring lines (Fig. 1; each pixel circuit is connected to Vdd); and a plurality of detection wiring lines (see Fig. 1 and 5, and Para. [0055]; separate detection wiring provided for each of the test transistors 131, 132, and 133), wherein the other conduction terminal of the input transistor is connected to any one of the plurality of data wiring lines (Fig. 5; transistor 11 has an electrode connected to data line), a control terminal of the input transistor is connected to any one of the plurality of scanning wiring lines (Fig. 5 and Para. [0095]; the display panel 100 may apply a gate signal to a gate terminal of a transistor 11 of the pixel circuit 111 to turn on the transistor 11), the other conduction terminal of the output transistor is connected to any one of the plurality of power source wiring lines (Fig. 5; other electrode of transistor 12 is connected to Vdd), and the detection terminal is connected to any one of the plurality of detection wiring lines (See Fig. 1 and 5; terminal inspection device 200 is connected to the detection wiring).
Regarding claim 11, Jung teaches The circuit substrate according to claim 3, Jung further teaches wherein the inspection circuit element is an inspection transistor (Fig. 5; transistor 131), one conduction terminal of the inspection transistor is connected to the output node (Fig. 5; connected to anode pad 121-2), and the other conduction terminal of the inspection transistor is connected to the detection terminal (Fig. 5; connected to inspection device 200 via detection wiring).
Regarding claim 16, Jung teaches The circuit substrate according to claim 1, Jung teaches further comprising: an element electrode connected to the output node (Fig. 5; 51 connected to anode pad 121-2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 15 and 20 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Jung et al. US PG-PUB 20250259577 A1 (hereinafter Jung) in view Lee et al. US PG-PUB 20260038399 A1 (hereinafter Lee).
Regarding claim 15, Jung teaches The circuit substrate according to claim 1, Jung further teaches wherein the control circuit includes a holding capacitor (Fig. 5; capacitor 13), one electrode of the holding capacitor is connected to the control terminal of the output transistor (Fig. 5; capacitor 13 is connected to gate of output transistor 12),
Jung fails to further disclose and the other electrode of the holding capacitor is connected to the output node.
However, in the same field of endeavor, Lee teaches input and output transistor (Fig. 3; transistors T1 and DRT), control circuit includes a holding capacitor (Fig. 3; capacitor Cst), one electrode of the holding capacitor is connected to the control terminal of the output transistor (Fig. 3; capacitor Cst is connected to gate of output transistor DRT), and the other electrode of the holding capacitor is connected to the output node (Fig. 3; capacitor Cst is connected to output node N2).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teachings of Jung with the teachings as taught by Lee in order to maintain data voltage Lee-(Para. [0107]).
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Regarding claim 20, Jung teaches A control circuit (Fig. 5) comprising: an input transistor (Fig. 5; transistor 11); an output transistor (Fig. 5; transistor 12); a holding capacitor (Fig. 5; capacitor 13); a first terminal; a second terminal; a third terminal; a fourth terminal (See Fig. 5; first, second, third, fourth terminal); and an output terminal (Fig. 5; output terminal), wherein one conduction terminal of the output transistor is connected to the first terminal (See Fig. 5 above an electrode of transistor 12 is connected to first terminal), the other conduction terminal of the is connected to the output terminal (See Fig. 5 above), one conduction terminal of the input transistor is connected to the second terminal (See Fig. 5 above an electrode of transistor 11 is connected to second terminal), the other conduction terminal is connected to a control terminal of the output transistor (see Fig. 5 above the other electrode of transistor 11 is connected to gate terminal of output transistor 12), the control terminal is connected to the third terminal (See Fig. 5 above), one electrode of the holding capacitor is connected to a control terminal of the output transistor (See Fig. 5; above, capacitor 13 connected to gate electrode of output transistor 12), and the control circuit further includes an inspection circuit element connected to the output terminal and the fourth terminal (Fig. 5; test transistor 131 connected to fourth terminal in inspection device 200).
Jung fails to further disclose and the other electrode of the holding capacitor is connected to the output terminal
However, in the same field of endeavor, Lee teaches input and output transistor (Fig. 3; transistors T1 and DRT), control circuit includes a holding capacitor (Fig. 3; capacitor Cst), one electrode of the holding capacitor is connected to the control terminal of the output transistor (Fig. 3; capacitor Cst is connected to gate of output transistor DRT), and the other electrode of the holding capacitor is connected to the output terminal (Fig. 3; capacitor Cst is connected to output node N2).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teachings of Jung with the teachings as taught by Lee in order to maintain data voltage Lee-(Para. [0107]).
Claims 17 and 18 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Jung et al. US PG-PUB 20250259577 A1 (hereinafter Jung) in view Tachino et al. US PG-PUB 20200078790 A1 (hereinafter Tachino).
Regarding claim 17, Jung fails to further disclose An electrowetting device comprising: the circuit substrate according to claim 1; a counter substrate facing the circuit substrate; and a conductive liquid disposed between the circuit substrate and the counter substrate.
However, in the same field of endeavor, Tachino teaches An electrowetting device (electrowetting device 100) comprising: the circuit substrate according to claim 1; a counter substrate facing the circuit substrate (Fig. 1; counter substrate 20 facing TFT substrate 11); and a conductive liquid disposed between the circuit substrate and the counter substrate (Fig. 1 and Para. [0041]; liquid droplet 42).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teachings of Jung with the teachings as taught by Tachino in order to apply and control a desired voltage Tachino-(Para. [0005]).
Regarding claim 18, Jung as modified by Tachino teaches The electrowetting device according to claim 17, Tachino further teaches wherein the counter substrate includes a counter electrode at a position facing the element electrode (Fig. 1; electrode 24 faces electrode 14).
Thus, it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine the teachings of Jung with the teachings as taught by Tachino in order to apply and control a desired voltage Tachino-(Para. [0005]).
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 12, none of the references cited either alone or in any obvious combination teaches and/or suggest “a plurality of inspection wiring lines and a control terminal of the inspection transistor is connected to any one of the plurality of inspection wiring lines”.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY ONYEKABA whose telephone number is (571)270-7633. The examiner can normally be reached on 9-5.
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/AMY ONYEKABA/Primary Examiner, Art Unit 2628
Prosecution Insights