DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 7 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 7 is direct to “the address period” in which both write gate signal and control gate signal is maintain at inactivation level. But the previous claim 6, which claim 7 is dependent from, states in the address period the data voltage is applied to the pixel. Meaning the write gate signal would not maintain at inactivation level. For example, see Applicant figure 12 which shows “the address period”, clearly both signals GW and GR are not maintain at inactivation level. The Examiner assumed that the claim was to be directed to the Applicant’s figure 14 which shows “the self-scan period” having both signals GW and GR maintained at inactivation level. Therefore, for rejection purposes the Examiner assumed the claim to incorrectly state “the address period” (Fig. 12) instead of “the self-scan period” (Fig. 14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-9, 14, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2024/0046872 A1) in view of Lee (US 2023/0260448 A1).
Claim 1, Yang (Fig. 1-18) discloses a display device (Fig. 1; Paragraph [0187]) comprising:
a display panel (A; Fig. 1; Paragraph [0047]; wherein discloses a display area A) including a pixel (PIX; Fig. 1);
a gate emission driver (DB; Fig. 1; Paragraph [0047]; wherein discloses a driving module; DB; Fig. 6) which outputs a gate signal (Gate; Fig. 6; Gate; Fig. 9) and an emission signal (EM; Fig. 6; EM; Fig. 9) to the pixel (Pix; Fig. 1; Fig. 8);
wherein the gate emission driver (DB; Fig. 1; Paragraph [0047]; wherein discloses a driving module; DB; Fig. 6) includes a control gate signal generator (DC2; Fig. 6) which generates a control gate signal (Gate’; Fig. 6; Paragraph [0088]) and a write gate signal generator (DC1; Fig. 6) which generates a write gate signal (Gate; Fig. 6),
wherein the write gate signal generator (DC1; Fig. 6) generates the write gate signal (Gate; Fig. 6) based on a carry clock signal (CK1; Fig. 6) and a first clock signal (CK2; Fig. 6), and
wherein the control gate signal generator (DC2; Fig. 6) generates the control gate signal (Gate’; Fig. 6) based on the carry clock signal (CK1; Fig. 6).
Yang does not expressly disclose a data driver which applies a data voltage to the display panel; and
a driving controller which controls the gate emission driver and the data driver,
wherein the pixel includes:
a driving transistor which generates a driving current based on the data voltage;
a write transistor which applies the data voltage to a control electrode of the driving transistor in response to the write gate signal;
an initialization transistor which applies a reference voltage to the control electrode of the driving transistor in response to the control gate signal; and
a light emitting element which emits light based on the driving current.
Lee (Fig. 1-21) discloses a data driver (720; Fig. 20) which applies a data voltage (VDAT; Fig. 20) to the display panel (710; Fig. 20); and
a driving controller (750; Fig. 20) which controls (EMCTRL, SCTRL, and DCTRL; Fig. 20) the gate emission driver (740 and 730; Fig. 20) and the data driver (720; Fig. 20),
wherein the pixel (600; Fig. 19) includes:
a driving transistor (T1; Fig. 19) which generates a driving current (Paragraph [0069]) based on the data voltage (DL: Fig. 19);
a write transistor (T2; Fig. 19) which applies the data voltage (DL; Fig. 19) to a control electrode (N1; Fig. 19) of the driving transistor (T1; Fig. 19) in response to the write gate signal (GW; Fig. 19);
an initialization transistor (T3; Fig. 19) which applies a reference voltage (VREF; Fig. 19) to the control electrode (N1; Fig. 19) of the driving transistor (T1; Fig. 19) in response to the control gate signal (GR; Fig. 19); and
a light emitting element (EL; Fig. 19) which emits light based on the driving current (Paragraph [0069]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang’s display device by applying a pixel circuit, as taught by Lee, so to use a display device with a pixel circuit for providing a current characteristic of the first transistor is changed, a voltage of the second node (e.g., the source node) may be changed to compensate for the change of the current characteristic, and thus the pixel may emit light with the desired luminance (Paragraph [0040]).
Claim 14, Yang (Fig. 1-18) discloses a display device (Fig. 1; Paragraph [0187]) comprising:
a display panel (A; Fig. 1; Paragraph [0047]; wherein discloses a display area A) including a pixel (PIX; Fig. 1);
a gate emission driver (DB; Fig. 1; Paragraph [0047]; wherein discloses a driving module; DB; Fig. 18) which outputs a gate signal (Gate; Fig. 6; Gate; Fig. 18) and an emission signal (EM; Fig. 6; EM; Fig. 18) to the pixel (Pix; Fig. 1; Fig. 8);
wherein the gate emission driver (DB; Fig. 18) includes:
a first emission control signal generator (DC3; Fig. 18; wherein a first unit of DC3 generates a first emission signal for the first row) which generates the first emission signal (EM; Fig. 18) based on a first clock signal (CK1; Fig. 18) and a second clock signal (CK2; Fig. 18);
a control gate signal generator (DC2; Fig. 18) which generates the control gate signal (Gate’/RST1; Fig. 18; Paragraph [0088]; wherein discloses Gate’ from adjacent row used for RST1 in figures 8 and 9) based on the first clock signal (CK1; Fig. 18) and the second clock signal (CK2; Fig. 18);
a second emission control signal generator (DC3; Fig. 18; wherein a second unit of DC3 generates a second emission signal for the second row) which generates the second emission signal (EM; Fig. 18) based on a first clock signal (CK1; Fig. 18) and a second clock signal (CK2; Fig. 18); and
an initialization gate signal generator (DC1; Fig. 18) which generates the initialization gate signal (Gate/RST2; Fig. 18; Paragraph [0089]; wherein discloses Gate from adjacent row used for RST2 in figures 8 and 9) based on the first clock signal (CK1; Fig. 18) and the second clock signal (CK2; Fig. 18).
Yang does not expressly disclose a data driver which applies a data voltage to the display panel; and
a driving controller which controls the gate emission driver and the data driver,
wherein the pixel includes:
a first transistor including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node;
a second transistor which applies the data voltage to the first node in response to a write gate signal;
a third transistor which applies a reference voltage to the first node in response to a control gate signal;
a fourth transistor which applies a first power voltage to the second node in response to a second emission signal;
a fifth transistor which connects the third node and a fourth node to each other in response to a first emission signal;
a sixth transistor which applies an initialization voltage to the fourth node in response to an initialization gate signal;
a first capacitor including a first electrode connected to the first node and a second electrode connected to the third node; and
a light emitting element including a first electrode connected to the fourth node and a second electrode which receives a second power voltage.
Lee (Fig. 1-21) discloses a data driver (720; Fig. 20) which applies a data voltage (VDAT; Fig. 20) to the display panel (710; Fig. 20); and
a driving controller (720; Fig. 20) which controls (EMCTRL, SCTRL, and DCTRL; Fig. 20) the gate emission driver (740 and 730; Fig. 20) and the data driver (720; Fig. 20),
wherein the pixel (600; Fig. 19) includes:
a first transistor (T1; Fig. 16) including a control electrode connected to a first node (N1; Fig. 16), a first electrode connected to a second node (T1; Fig. 16; wherein figure shows an electrode connected to a node between transistors T1 and T7) and a second electrode (T1; Fig. 16) connected to a third node (N2; Fig. 15);
a second transistor (T2; Fig. 16) which applies the data voltage (DL; Fig. 16) to the first node (N1; Fig. 16) in response to the write gate signal (GW; Fig. 16);
a third transistor (T3; Fig. 16) which applies the reference voltage (VREF; Fig. 16) to the first node (N1; Fig. 16) in response to the control gate signal (GR; Fig. 16);
a fourth transistor (T7; Fig. 16) which applies a first power voltage (ELVDD; Fig. 16) to the second node (T1; Fig. 16; wherein figure shows an electrode connected to a node between transistors T1 and T7) in response to a second emission signal (EM2; Fig. 16);
a fifth transistor (T5; Fig. 16) which connects the third node (N2; Fig. 16) and a fourth node (Fig. 16; wherein figure shows a node between transistors T5, T6, and anode of EL) to each other in response to a first emission signal (EM; Fig. 16);
a sixth transistor (T6; Fig. 16) which applies an initialization voltage (VINT; Fig. 16) to the fourth node (Fig. 16; wherein figure shows a node between transistors T5, T6, and anode of EL) in response to an initialization gate signal (GI; Fig. 16);
a first capacitor (Cst; Fig. 16) including a first electrode connected to the first node (N1; Fig. 16) and a second electrode connected to the third node (N2; Fig. 16); and
a light emitting element (EL; Fig. 16) including a first electrode connected to the fourth node (Fig. 16; wherein figure shows a node between transistors T5, T6, and anode of EL) and a second electrode which receives a second power voltage (ELVSS; Fig. 16).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang’s display device by applying a pixel circuit, as taught by Lee, so to use a display device with a pixel circuit for providing a current characteristic of the first transistor is changed, a voltage of the second node (e.g., the source node) may be changed to compensate for the change of the current characteristic, and thus the pixel may emit light with the desired luminance (Paragraph [0040]).
Claim 18, Yang (Fig. 1-18) discloses an electronic device (Fig. 1; Paragraph [0187]) comprising:
a display panel (A; Fig. 1; Paragraph [0047]; wherein discloses a display area A) including a pixel (PIX; Fig. 1);
a gate emission driver (DB; Fig. 1; Paragraph [0047]; wherein discloses a driving module; DB; Fig. 6) which outputs a gate signal (Gate; Fig. 6; Gate; Fig. 9) and an emission signal (EM; Fig. 6; EM; Fig. 9) to the pixel (Pix; Fig. 1; Fig. 8);
wherein the gate emission driver (DB; Fig. 1; Paragraph [0047]; wherein discloses a driving module; DB; Fig. 6) includes a control gate signal generator (DC2; Fig. 6) which generates a control gate signal (Gate’; Fig. 6; Paragraph [0088]) and a write gate signal generator (DC1; Fig. 6) which generates a write gate signal (Gate; Fig. 6),
wherein the write gate signal generator (DC1; Fig. 6) generates the write gate signal (Gate; Fig. 6) based on a carry clock signal (CK1; Fig. 6) and a first clock signal (CK2; Fig. 6), and
wherein the control gate signal generator (DC2; Fig. 6) generates the control gate signal (Gate’; Fig. 6) based on the carry clock signal (CK1; Fig. 6).
Yang does not expressly disclose a data driver which applies a data voltage to the display panel; and
a driving controller which controls the gate emission driver and the data driver,
a processor which outputs the input control signal to the driving controller,
wherein the pixel includes:
a driving transistor which generates a driving current based on the data voltage;
a write transistor which applies the data voltage to a control electrode of the driving transistor in response to the write gate signal;
an initialization transistor which applies a reference voltage to the control electrode of the driving transistor in response to the control gate signal; and
a light emitting element which emits light based on the driving current.
Lee (Fig. 1-21) discloses a data driver (720; Fig. 20) which applies a data voltage (VDAT; Fig. 20) to the display panel (710; Fig. 20); and
a driving controller (750; Fig. 20) which controls (EMCTRL, SCTRL, and DCTRL; Fig. 20) the gate emission driver (740 and 730; Fig. 20) and the data driver (720; Fig. 20),
a processor (Paragraph [0126]; wherein discloses “The controller 750 (e.g., a timing controller) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (“GPU”), an application processor (“AP”) or a graphics card)”) which outputs the input control signal (IDAT/CTRL; Fig. 20) to the driving controller (750; Fig. 20),
wherein the pixel (600; Fig. 19) includes:
a driving transistor (T1; Fig. 19) which generates a driving current (Paragraph [0069]) based on the data voltage (DL: Fig. 19);
a write transistor (T2; Fig. 19) which applies the data voltage (DL; Fig. 19) to a control electrode (N1; Fig. 19) of the driving transistor (T1; Fig. 19) in response to the write gate signal (GW; Fig. 19);
an initialization transistor (T3; Fig. 19) which applies a reference voltage (VREF; Fig. 19) to the control electrode (N1; Fig. 19) of the driving transistor (T1; Fig. 19) in response to the control gate signal (GR; Fig. 19); and
a light emitting element (EL; Fig. 19) which emits light based on the driving current (Paragraph [0069]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang’s display device by applying a pixel circuit, as taught by Lee, so to use a display device with a pixel circuit for providing a current characteristic of the first transistor is changed, a voltage of the second node (e.g., the source node) may be changed to compensate for the change of the current characteristic, and thus the pixel may emit light with the desired luminance (Paragraph [0040]).
Claims 2 and 19, Yang (Fig. 1-18) discloses wherein the write gate signal generator (DC1; Fig. 6) is connected to a carry clock line (CK1; Fig. 6) which transmits the carry clock signal (CLK; Fig. 12 and 13), and
wherein the control gate signal generator (DC2; Fig. 6) is connected to the carry clock line (CK1; Fig. 6).
Claim 8, Lee (Fig. 1-21) discloses wherein the pixel (400; Fig. 16) includes:
a first transistor (T1; Fig. 16) including a control electrode connected to a first node (N1; Fig. 16), a first electrode connected to a second node (T1; Fig. 16; wherein figure shows an electrode connected to a node between transistors T1 and T7) and a second electrode (T1; Fig. 16) connected to a third node (N2; Fig. 15);
a second transistor (T2; Fig. 16) which applies the data voltage (DL; Fig. 16) to the first node (N1; Fig. 16) in response to the write gate signal (GW; Fig. 16);
a third transistor (T3; Fig. 16) which applies the reference voltage (VREF; Fig. 16) to the first node (N1; Fig. 16) in response to the control gate signal (GR; Fig. 16);
a fourth transistor (T7; Fig. 16) which applies a first power voltage (ELVDD; Fig. 16) to the second node (T1; Fig. 16; wherein figure shows an electrode connected to a node between transistors T1 and T7) in response to a second emission signal (EM2; Fig. 16);
a fifth transistor (T5; Fig. 16) which connects the third node (N2; Fig. 16) and a fourth node (Fig. 16; wherein figure shows a node between transistors T5, T6, and anode of EL) to each other in response to a first emission signal (EM; Fig. 16);
a sixth transistor (T6; Fig. 16) which applies an initialization voltage (VINT; Fig. 16) to the fourth node (Fig. 16; wherein figure shows a node between transistors T5, T6, and anode of EL) in response to an initialization gate signal (GI; Fig. 16);
a first capacitor (Cst; Fig. 16) including a first electrode connected to the first node (N1; Fig. 16) and a second electrode connected to the third node (N2; Fig. 16); and
a light emitting element (EL; Fig. 16) including a first electrode connected to the fourth node (Fig. 16; wherein figure shows a node between transistors T5, T6, and anode of EL) and a second electrode which receives a second power voltage (ELVSS; Fig. 16), and
wherein the first transistor (T1; Fig. 16) is the driving transistor (Paragraph [0069]), the second transistor (T2; Fig. 16) is the write transistor (Paragraph [0071]), and the third transistor (T3; Fig. 16) is the initialization transistor (Paragraph [0072]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang’s display device by applying a pixel circuit, as taught by Lee, so to use a display device with a pixel circuit for providing a current characteristic of the first transistor is changed, a voltage of the second node (e.g., the source node) may be changed to compensate for the change of the current characteristic, and thus the pixel may emit light with the desired luminance (Paragraph [0040]).
Claim 9, Yang (Fig. 1-18) discloses wherein the gate emission driver (BD; Fig. 16B) further includes a first emission control signal generator (DC3; Fig. 16B; wherein figure shows a first unit which outputs a first emission signal EM) which generates the first emission signal (EM; Fig. 16B), a second emission control signal generator (DC3; Fig. 16B; wherein figure shows a second unit which outputs a second emission signal EM) which generates the second emission signal (DC3; Fig. 16B; wherein figure shows a second unit which outputs a second emission signal EM), and an initialization gate signal generator (DC2; Fig. 6B; Paragraph [0088]) which generates the initialization gate signal (RST1; Fig. 8; Paragraph [0088]),
wherein the first emission control signal generator (DC3; Fig. 16B; wherein figure shows a first unit which outputs a first emission signal EM) generates the first emission signal (EM; Fig. 16B) based on a third clock signal (CK1’; Fig. 16B) and a fourth clock signal (CK2’; Fig. 16B),
wherein the second emission control signal generator (DC3; Fig. 16B; wherein figure shows a second unit which outputs a second emission signal EM) generates the second emission signal (EM; Fig. 16B) based on the third clock signal (CK1’; Fig. 16B) and the fourth clock signal (CK2’; Fig. 16B), and
wherein the initialization gate signal generator (DC2; Fig. 16B) generates the initialization gate signal (RST1; Fig. 8; Paragraph [0088]) based on the third clock signal (CK1’; Fig. 16B) and the fourth clock signal (CK2’; Fig. 16B).
Claims 3-5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2024/0046872 A1) in view of Lee (US 2023/0260448 A1) as applied to claims 1 and 19 above, and further in view of Kim (US 2020/0066203 A1).
Claims 3 and 20, Yang (Fig. 1-18) discloses wherein the write gate signal generator (DC1; Fig. 6) generates the write gate signals (Gate; Fig. 6) based on the carry clock signal (CK1; Fig. 6) and the first clock signal (CK2; Fig. 6).
Yang in view of Lee does not expressly disclose wherein the write gate signal generator generates the write gate signals based on the carry clock signal, the first clock signal and a second clock signal,
wherein the write gate signal generator includes:
a write gate signal controller which outputs a carry signal based on the carry clock signal;
a first write gate signal outputter which outputs a first write gate signal based on the carry signal and the first clock signal; and
a second write gate signal outputter which outputs a second write gate signal based on the carry signal and a second clock signal.
Kim (Fig. 1-6) discloses wherein the write gate signal generator (210; Fig. 3 and 5) generates the write gate signals (SCL1 and SCL2; Fig. 3; SC1 and SC2; Fig. 5) based on the carry clock signal (CRCK1; Fig. 3; CRCT; Fig. 5), the first clock signal (SCCK1; Fig. 3; SCCT1; Fig. 5) and a second clock signal (SCCK2; Fig. 3; SCCT2; Fig. 5),
wherein the write gate signal generator (210; Fig. 3 and 5) includes:
a write gate signal controller (215; Fig. 5) which outputs a carry signal (CR; Fig. 5) based on the carry clock signal (CRCT; Fig. 5);
a first write gate signal outputter (211; Fig. 5) which outputs a first write gate signal (SC1; Fig. 5) based on the carry signal (IN1; Fig. 5; Fig. 3; wherein figure 3 shows IN1 terminal receives a carry signal from the previous stage) and the first clock signal (SCCT1; Fig. 5); and
a second write gate signal outputter (213; Fig. 5) which outputs a second write gate signal (SC1; Fig. 5) based on the carry signal (IN1; Fig. 5; Fig. 3; wherein figure 3 shows IN1 terminal receives a carry signal from the previous stage) and a second clock signal (SCCT2; Fig. 5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Lee’s display device by applying a gate driving circuit, as taught by Kim, so to use a display device with a gate driving circuit for providing a gate driving circuit for reducing a dead space of a display device (Paragraph [0008]).
Claim 4, Kim (Fig. 1-6) discloses wherein the display panel (600; Fig. 1) includes first (SCL1; Fig. 1) to N-th pixel-rows (SCLn; Fig. 1) which are sequentially arranged (Fig. 1), and
wherein the first write gate signal (SCL1; Fig. 1 and 3) is applied to the first pixel-row (PX of first row; Fig. 1), and the second write gate signal (SCL2; Fig. 1 and 3) is applied to the second pixel-row (PX of second row; Fig. 1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Lee’s display device by applying a gate driving circuit, as taught by Kim, so to use a display device with a gate driving circuit for providing a gate driving circuit for reducing a dead space of a display device (Paragraph [0008]).
Claim 5, Yang (Fig. 1-18) discloses wherein the control gate signal generator (DC2; Fig. 6) outputs the control gate signal (Gate’; Fig. 6) to the first pixel-row and the second pixel-row (PIX; Fig. 1; Paragraph [0088]; wherein discloses single circuit provides both signals RST1 and Gate’ of figure 9 to different rows of pixels).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2024/0046872 A1) in view of Lee (US 2023/0260448 A1) as applied to claim 1 above, and further in view of Jeon (US 2017/0206837 A1).
Claim 6, Yang in view of Lee discloses the display device of claim 1.
Yang in view of Lee does not expressly disclose wherein a frame period in which the display panel is driven includes an address period and a self-scan period,
wherein in the address period, the data voltage is applied to the pixel, and the pixel emits light based on the data voltage,
wherein in the self-scan period, the pixel emits light based on the data voltage of the address period, and
wherein in the self-scan period, the carry clock signal has direct current voltage.
Jeon (Fig. 1-13) discloses wherein a frame period (DM2; Fig. 7) in which the display panel (Fig. 3) is driven includes an address period (FPs; Fig. 7) and a self-scan period (FPr; Fig. 7),
wherein in the address period (FPs; Fig. 7), the data voltage (Paragraph [0207]) is applied to the pixel (PXL; Fig. 3), and the pixel emits light (Fig. 2B) based on the data voltage (120; Fig. 3),
wherein in the self-scan period (FPr; Fig. 7), the pixel emits light (Fig. 2B) based on the data voltage (120; Fig. 3) of the address period (FPs; Fig. 7), and
wherein in the self-scan period (FPr; Fig. 7), the carry clock signal (CLK1 or CLK2; Fig. 7) has direct current voltage (Fig. 7; wherein figure shows during FPr the clock signals are reduced to a low direct current voltage).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Lee’s display device by applying a driving method, as taught by Jeon, so to use a display device with a driving method for providing a display device, e.g., an organic light emitting display device, capable of operating with satisfactorily low power consumption (Paragraph [0007]).
Claim 7, Jeon (Fig. 1-13) discloses wherein in the address period (See U.S.C 112 rejection above; The Examiner believes that this limitation should have been --the self-scan period-- not “the address period” as claimed; FPr; Fig. 7), the write gate signal (Sk; Fig. 9) maintains an inactivation level (SS2; Fig. 7; wherein figure shows scan signal is maintained at an inactivation level), and the control gate signal (Sk-1; Fig. 9) maintains an inactivation level (SS1; Fig. 7; wherein figure shows scan signal is maintained at an inactivation level).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Lee’s display device by applying a driving method, as taught by Jeon, so to use a display device with a driving method for providing a display device, e.g., an organic light emitting display device, capable of operating with satisfactorily low power consumption (Paragraph [0007]).
Claims 10-12, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2024/0046872 A1) in view of Lee (US 2023/0260448 A1) as applied to claims 9 and 14 above, and further in view of Jeong (US 2023/0027673 A1).
Claim 10, Yang in view of Lee discloses the display device of claim 9.
Yang in view of does not expressly disclose wherein the second emission control signal generator includes second-first to second-K-th emission control signal sub-generators,
wherein the initialization gate signal generator includes first to K-th initialization gate signal sub-generators, and
wherein the second-first to second-K-th emission control signal sub-generators and first to K-th initialization gate signal sub-generators are arranged alternately with each other.
Jeong (Fig. 1-16) discloses wherein the second emission control signal generator (40 or 40’; Fig. 15) includes second-first to second-K-th emission control signal sub-generators (EMS1-EMS4; Fig. 7),
wherein the initialization gate signal generator (31 or 31’; Fig. 15) includes first to K-th initialization gate signal sub-generators (G1S1-GIS4; Fig. 7), and
wherein the second-first to second-K-th emission control signal sub-generators (EMS1-EMS4; Fig. 7) and first to K-th initialization gate signal sub-generators (G1S1-GIS4; Fig. 7) are arranged alternately with each other (Fig. 7).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Lee’s display device by applying a drive circuit arrangement, as taught by Jeong, so to use a display device with a drive circuit arrangement for providing a minimizing a dead space by reducing the sizes of scan drivers and/or emission drivers and operating two or more areas to display images at different image frequencies (Paragraph [0006]).
Claim 11, Jeong (Fig. 1-16) discloses wherein a write gate line (GW1-GW16; Fig. 10), which transmits the write gate signal (GW; Fig. 4), extends in a first direction (Fig. 10; wherein figure shows gate line GW extending in horizontal direction),
wherein the first initialization gate signal sub-generator (GIS1; Fig. 7) is spaced apart from the second-first emission control signal sub-generator (EMS1; Fig. 7;) in a second direction (Fig. 7; wherein figure shows driving stages being spaced in the vertical direction) different from the first direction (Fig. 7; wherein first direction is the horizontal direction),
wherein the second-second emission control signal sub-generator (EMS2; Fig. 7) is spaced apart from the first initialization gate signal sub-generator (GIS1; Fig. 7) in a second direction (Fig. 7; wherein figure shows driving stages being spaced in the vertical direction), and
wherein the second initialization gate signal sub-generator (GIS2; Fig. 7) is spaced apart from the second-second emission control signal sub-generator (EMS2; Fig. 7) in the second direction (Fig. 7; wherein figure shows driving stages being spaced in the vertical direction).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Lee’s display device by applying a drive circuit arrangement, as taught by Jeong, so to use a display device with a drive circuit arrangement for providing a minimizing a dead space by reducing the sizes of scan drivers and/or emission drivers and operating two or more areas to display images at different image frequencies (Paragraph [0006]).
Claim 12, Yang (Fig. 1-18) discloses wherein the first emission control signal generator (DC3; Fig. 6) includes first to K-th emission control signal sub-generators (Fig. 6; wherein figure shows a plurality of emission control signal sub-generators), and
wherein the first to K-th emission control signal sub-generators (Fig. 6; wherein figure shows a plurality of emission control signal sub-generators) are sequentially arranged in the second direction (Fig. 6; wherein figure shows unit arranged sequentially arranged in the vertical direction).
Claim 15, Yang in view of Lee discloses the display device of claim 14.
Yang in view of Lee does not expressly disclose wherein a write gate line, which transmits the write gate signal, extends in a first direction,
wherein the initialization gate signal generator is spaced apart from the second emission control signal generator in a second direction different from the first direction, and
wherein the control gate signal generator is spaced apart from the first emission control signal generator in the second direction.
Jeong (Fig. 1-16) discloses wherein a write gate line (GW1-GWw; Fig. 1), which transmits the write gate signal (GW; Fig. 4), extends in a first direction (Fig. 1; wherein figure shows GW line extending in horizontal direction across the display area),
wherein the initialization gate signal generator (33; Fig. 1; GWS1-GWS16; Fig. 10; Fig. 2; wherein figure shows transistor T7 receiving signal GW) is spaced apart from the second emission control signal generator (40’; Fig. 15) in a second direction (Fig. 7 and 10; wherein figure 7 shows a space between adjacent emission units EMS1 and EMS2, and figure 10 shows no spacing between adjacent gate writing units GWS3-GWS4; therefore the disclosed arrangement taught by Jeong would read on the claim limitation that the GWS3 and EMS1 units are space apart in the vertical direction) different from the first direction (Fig. 7; wherein the first direction is horizontal direction across the display area), and
wherein the control gate signal generator (31; Fig. 1; GIS1-GIS4; Fig. 7) is spaced apart from the first emission control signal generator (EMS1-EMS4; Fig. 7) in the second direction (Fig. 7; wherein figure shows unit EMS1 and GIS1 being spaced apart in the vertical direction).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Lee’s display device by applying a drive circuit arrangement, as taught by Jeong, so to use a display device with a drive circuit arrangement for providing a minimizing a dead space by reducing the sizes of scan drivers and/or emission drivers and operating two or more areas to display images at different image frequencies (Paragraph [0006]).
Claim 16, Yang in view of Lee discloses the display device of claim 14.
Yang in view of Lee does not expressly disclose wherein the display panel includes first to N-th pixel-rows which are sequentially located,
wherein the write gate signal includes first to N-th write gate signals,
wherein the first write gate signal is applied to the first pixel-row, the second write gate signal is applied to the second pixel-row, the third write gate signal is applied to the third pixel-row, and the fourth write gate signal is applied to the fourth pixel-row,
wherein a timing of the first emission signal applied to the first pixel-row is consistent with a timing of the first emission signal applied to the second pixel-row, wherein a timing of the first emission signal applied to the third pixel-row is consistent with a timing of the first emission signal applied to the fourth pixel-row, and
wherein the timing of the first emission signal applied to the first pixel-row is inconsistent with the timing of the first emission signal applied to the third pixel-row.
Jeong (Fig. 1-16) discloses wherein the display panel (Fig. 7 and 10) includes first to N-th pixel-rows (Fig. 7 and 10; wherein figure shows at least 16 pixel rows) which are sequentially located (Fig. 7 and 10),
wherein the write gate signal (Fig. 10) includes first to N-th write gate signals (GW1-GW16),
wherein the first write gate signal (GW7; Fig. 10) is applied to the first pixel-row (Fig. 10; wherein figure shows a second to last pixel row (GW7) within a first area AR1), the second write gate signal (GW8; Fig. 10) is applied to the second pixel-row (Fig. 10; wherein figure shows a last pixel row (GW8) within a first area AR1), the third write gate signal (GW9; Fig. 10) is applied to the third pixel-row (Fig. 10; wherein figure shows a first pixel row (GW9) within a second area AR2), and the fourth write gate signal (GW9; Fig. 10) is applied to the fourth pixel-row (Fig. 10; wherein figure shows a second pixel row (GW10) within a second area AR2),
wherein a timing of the first emission signal (EM2; Fig. 7) applied to the first pixel-row (Fig. 10; wherein figure shows a second to last pixel row within a first area AR1 connected to emission EM2) is consistent with a timing of the first emission signal (EM2; Fig. 7) applied to the second pixel-row (Fig. 10; wherein figure shows a last pixel row within a first area AR1 connected to emission EM2), wherein a timing of the first emission signal (EM3; Fig. 7) applied to the third pixel-row (Fig. 10; wherein figure shows a first pixel row within a second area AR2 connected to emission EM3) is consistent with a timing of the first emission signal (EM3; Fig. 7) applied to the fourth pixel-row (Fig. 10; wherein figure shows a second pixel row within a second area AR2 connected to emission EM3), and
wherein the timing of the first emission signal (EM2; Fig. 7) applied to the first pixel-row (Fig. 10; wherein figure shows a second to last pixel row within a first area AR1 connected to emission EM2) is inconsistent (Paragraph [0062]) with the timing of the first emission signal (EM3; Fig. 7) applied to the third pixel-row (Fig. 10; wherein figure shows a first pixel row within a second area AR2 connected to emission EM3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Lee’s display device by applying a drive circuit arrangement, as taught by Jeong, so to use a display device with a drive circuit arrangement for providing a minimizing a dead space by reducing the sizes of scan drivers and/or emission drivers and operating two or more areas to display images at different image frequencies (Paragraph [0006]).
Claim 17, Yang in view of Lee discloses the display device of claim 14.
Yang in view of Lee does not expressly disclose wherein the display panel includes first to N-th pixel-rows which are sequentially arranged,
wherein the write gate signal includes first to N-th write gate signals,
wherein the first signal includes first-first to first-K-th emission signals,
wherein the second signal includes first-first to second-K-th emission signals, wherein the control gate signal includes first to K-th control gate signals,
wherein the initialization gate signal includes first to K-th initialization gate signals,
wherein the first write gate signal is applied to the first pixel-row, and the second write gate signal is applied to the second pixel-row, and
wherein the first-first emission signal, the second-first emission signal, the first control gate signal and the first initialization gate signal are applied to the first pixel-row and the second pixel-row.
Jeong (Fig. 1-16) discloses wherein the display panel (Fig. 7 and 10) includes first to N-th pixel-rows (Fig. 7 and 10; wherein figure shows at least 16 pixel rows) which are sequentially arranged (Fig. 7 and 10),
wherein the write gate signal (33; Fig. 15) includes first to N-th write gate signals (GW1-GWw; Fig. 15),
wherein the first signal (40; Fig. 15) includes first-first to first-K-th emission signals (EM1-EMt; Fig. 15),
wherein the second signal (40’; Fig. 15) includes first-first to second-K-th emission signals (EM1-EMt; Fig. 15),
wherein the control gate signal (GIq; Fig. 2; 31; Fig. 15) includes first to K-th control gate signals (GI1-GIu; Fig. 15),
wherein the initialization gate signal (GW; Fig. 2; 33’; Fig. 15) includes first to K-th initialization gate signals (GW1-GWw; Fig. 15),
wherein the first write gate signal (GW1; Fig. 10) is applied to the first pixel-row (Fig. 10; wherein figure shows GW1 being applied to the first pixel row), and the second write gate signal (GW2; Fig. 10) is applied to the second pixel-row (Fig. 10; wherein figure shows GW2 being applied to the second pixel row), and
wherein the first-first emission signal (40; Fig. 15; EM1; Fig. 7), the second-first emission signal (40’; Fig. 15; EM1; Fig. 7), the first control gate signal (31; Fig. 15; (GI1; Fig. 7) and the first initialization gate signal (33’; Fig. 15; GW2; Fig. 10) are applied to the first pixel-row and the second pixel-row (Fig. 7 and 10; wherein figure shows each unit applies output signals to multiple pixel rows).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view of Lee’s display device by applying a drive circuit arrangement, as taught by Jeong, so to use a display device with a drive circuit arrangement for providing a minimizing a dead space by reducing the sizes of scan drivers and/or emission drivers and operating two or more areas to display images at different image frequencies (Paragraph [0006]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al (US 2024/0046872 A1) in view of Lee (US 2023/0260448 A1) as applied to claim 9 above, and further in view of Yang et al (US 2019/0180688 A1).
Claim 13, Lee (Fig. 1-21) discloses wherein the pixel (400; Fig. 16) further includes:
wherein the second transistor (T2; Fig. 16) includes a control electrode which receives the write gate signal (GW; Fig. 16), a first electrode which receives the data voltage (DL; Fig. 16) and a second electrode connected to the first node (N1; Fig. 16),
wherein the third transistor (T3; Fig. 16) includes a control electrode which receives the control gate signal (GR; Fig. 16), a first electrode which receives the reference voltage (VREF; Fig. 16) and a second electrode connected to the first node (N1; Fig. 16),
wherein the fourth transistor (T7; Fig. 16) includes a control electrode which receives the second emission signal (EM2; Fig. 16), a first electrode which receives the first power voltage (ELVDD; Fig. 16) and a second electrode connected to the second node (Fig. 16; wherein figure shows a node between transistors T1 and T7),
wherein the fifth transistor (T5; Fig. 16) includes a control electrode which receives the first emission signal (EM; Fig. 16), a first electrode connected to the third node (N2; Fig. 16) and a second electrode connected to the fourth node (Fig. 16; wherein figure shows a node between transistors T5, T6, and anode of EL),
wherein the sixth transistor (T6; Fig. 16) includes a control electrode which receives the initialization gate signal (GI; Fig. 16), a first electrode which receives the initialization voltage (VINT; Fig. 16) and a second electrode connected to the fourth node (Fig. 16; wherein figure shows a node between transistors T5, T6, and anode of EL).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang’s display device by applying a pixel circuit, as taught by Lee, so to use a display device with a pixel circuit for providing a current characteristic of the first transistor is changed, a voltage of the second node (e.g., the source node) may be changed to compensate for the change of the current characteristic, and thus the pixel may emit light with the desired luminance (Paragraph [0040]).
Yang in view Lee does not expressly disclose wherein the pixel further includes a second capacitor,
wherein the first transistor further includes a second control electrode connected to the third node,
wherein the second capacitor includes a first electrode which receives the first power voltage and a second electrode connected to the third node.
Yang (Fig. 1-13) discloses wherein the pixel (PXB; Fig. 6) further includes a second capacitor (C2; Fig. 6),
wherein the first transistor (T1’; Fig. 5) further includes a second control electrode (Paragraph [0099]) connected to the third node (N2; Fig. 6),
wherein the second capacitor (C2; Fig. 6) includes a first electrode which receives the first power voltage (ELVDD; Fig. 6) and a second electrode connected to the third node (N2; Fig. 6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Yang in view Lee’s display device by applying a second capacitor, as taught by Yang, so to use a display device with a second capacitor for providing a pixel capable of improving image quality (Paragraph [0006]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Adam J Snyder/Primary Examiner, Art Unit 2623 06/24/2026
Prosecution Insights