DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 10, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2008/0111777 A1) in view of Asano (US 2011/0032238 A1).
Claim 1, Kim (Fig. 1-3) discloses a display device (Fig. 1; Paragraph [0016]) comprising:
a pixel (110; Fig. 1) located in a display area (100; Fig. 1) where an image is displayed (Paragraph [0005]), the pixel (110; Fig. 1 and 2) comprising a first sub-pixel comprising a first pixel circuit (Fig. 2; wherein figure shows a red subpixel), a second sub-pixel comprising a second pixel circuit (Fig. 2; wherein figure shows a green subpixel), and a third sub-pixel comprising a third pixel circuit (Fig. 2; wherein figure shows a blue subpixel);
a first emission control line (E3; Fig. 2) electrically connected (SR; Fig. 3) to the first pixel circuit (Fig. 2; wherein figure shows a red subpixel);
a second emission control line (E4; Fig. 2) electrically connected (SG and SB2; Fig. 2) to the second pixel circuit (Fig. 2; wherein figure shows a green subpixel) and the third pixel circuit (Fig. 2; wherein figure shows a blue subpixel).
Kim does not expressly disclose first power lines electrically connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit, the first power lines being arranged along a first direction in the display area and extending in a second direction,
wherein the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged along the first direction in the display area,
wherein the first pixel circuit overlaps a first power line of the first power lines, and
wherein the second pixel circuit and the third pixel circuit overlap an other first power line of the first power lines and have a symmetrical shape with respect to the other first power line.
Asano (Fig. 1-22) discloses first power lines (Vcc; Fig. 11) electrically connected to the first pixel circuit (Fig. 11; wherein the first pixel circuit in this figure is located in on the right), the second pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located in the middle), and the third pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located on the left), the first power lines (Vcc; Fig. 11) being arranged along a first direction in the display area (Fig. 11; wherein figure shows first power lines Vcc arranged along a horizontal direction) and extending in a second direction (Fig. 11; wherein figure shows first power lines Vcc extending in a vertical direction),
wherein the first pixel circuit (Fig. 11; wherein the first pixel circuit in this figure is located in on the right), the second pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located in the middle), and the third pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located on the left) are arranged along the first direction in the display area (Fig. 11; wherein figure shows subpixel circuits 101A arranged along a horizontal direction),
wherein the first pixel circuit (Fig. 11; wherein the first pixel circuit in this figure is located in on the right) overlaps a first power line (VCCL103; Fig. 11) of the first power lines (Vcc; Fig. 11), and
wherein the second pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located in the middle) and the third pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located on the left) overlap an other first power line (VCCL101; Fig. 11) of the first power lines (Vcc; Fig. 11) and have a symmetrical shape (Fig. 11; wherein figure shows the two subpixels 101A are symmetrically arranged with respect to VCCL101) with respect to the other first power line (VCCL101; Fig. 11).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim’s display device by applying a pixel arrangement, as taught by Asano, so to use a display device with a pixel arrangement for providing a display device able to prevent crosstalk between pixels by relatively simple layout, able to prevent the occurrence of uneven luminance in the displayed image, able to stably and correctly supply a current of a desired value to the light emitting element of each pixel without regard to the variation of the threshold value of the active elements inside the pixels, and as a result able to display a high quality image (Paragraph [0051]).
Claim 20, Kim (Fig. 1-3) discloses an electronic device (Fig. 1; Paragraph [0016]) comprising:
a display device (100; Fig. 1) comprising a display area where an image is displayed (Fig. 1; wherein figure shows display unit which is comprised of pixel units to display image supplied by data signals),
wherein the display device (100; Fig. 1) comprising:
a pixel (110; Fig. 1) located in a display area (100; Fig. 1) where an image is displayed (Paragraph [0005]), the pixel (110; Fig. 1 and 2) comprising a first sub-pixel comprising a first pixel circuit (Fig. 2; wherein figure shows a red subpixel), a second sub-pixel comprising a second pixel circuit (Fig. 2; wherein figure shows a green subpixel), and a third sub-pixel comprising a third pixel circuit (Fig. 2; wherein figure shows a blue subpixel);
a first emission control line (E3; Fig. 2) electrically connected (SR; Fig. 3) to the first pixel circuit (Fig. 2; wherein figure shows a red subpixel);
a second emission control line (E4; Fig. 2) electrically connected (SG and SB2; Fig. 2) to the second pixel circuit (Fig. 2; wherein figure shows a green subpixel) and the third pixel circuit (Fig. 2; wherein figure shows a blue subpixel).
Kim does not expressly disclose first power lines electrically connected to the first pixel circuit, the second pixel circuit, and the third pixel circuit, the first power lines being arranged along a first direction in the display area and extending in a second direction,
wherein the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged along the first direction in the display area,
wherein the first pixel circuit overlaps a first power line of the first power lines, and
wherein the second pixel circuit and the third pixel circuit overlap an other first power line of the first power lines and have a symmetrical shape with respect to the other first power line.
Asano (Fig. 1-22) discloses first power lines (Vcc; Fig. 11) electrically connected to the first pixel circuit (Fig. 11; wherein the first pixel circuit in this figure is located in on the right), the second pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located in the middle), and the third pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located on the left), the first power lines (Vcc; Fig. 11) being arranged along a first direction in the display area (Fig. 11; wherein figure shows first power lines Vcc arranged along a horizontal direction) and extending in a second direction (Fig. 11; wherein figure shows first power lines Vcc extending in a vertical direction),
wherein the first pixel circuit (Fig. 11; wherein the first pixel circuit in this figure is located in on the right), the second pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located in the middle), and the third pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located on the left) are arranged along the first direction in the display area (Fig. 11; wherein figure shows subpixel circuits 101A arranged along a horizontal direction),
wherein the first pixel circuit (Fig. 11; wherein the first pixel circuit in this figure is located in on the right) overlaps a first power line (VCCL103; Fig. 11) of the first power lines (Vcc; Fig. 11), and
wherein the second pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located in the middle) and the third pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located on the left) overlap an other first power line (VCCL101; Fig. 11) of the first power lines (Vcc; Fig. 11) and have a symmetrical shape (Fig. 11; wherein figure shows the two subpixels 101A are symmetrically arranged with respect to VCCL101) with respect to the other first power line (VCCL101; Fig. 11).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim’s display device by applying a pixel arrangement, as taught by Asano, so to use a display device with a pixel arrangement for providing a display device able to prevent crosstalk between pixels by relatively simple layout, able to prevent the occurrence of uneven luminance in the displayed image, able to stably and correctly supply a current of a desired value to the light emitting element of each pixel without regard to the variation of the threshold value of the active elements inside the pixels, and as a result able to display a high quality image (Paragraph [0051]).
Claim 2, Asano (Fig. 1-22) discloses wherein the second pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located in the middle) and the third pixel circuit (Fig. 11; wherein the second pixel circuit in this figure is located on the left) are commonly connected to the other first power line (VCCL101; Fig. 11) and have a symmetrical shape (Fig. 11; wherein figure shows the two subpixels 101A are symmetrically arranged with respect to VCCL101) with respect to the other first power line (VCCL101; Fig. 11).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim’s display device by applying a pixel arrangement, as taught by Asano, so to use a display device with a pixel arrangement for providing a display device able to prevent crosstalk between pixels by relatively simple layout, able to prevent the occurrence of uneven luminance in the displayed image, able to stably and correctly supply a current of a desired value to the light emitting element of each pixel without regard to the variation of the threshold value of the active elements inside the pixels, and as a result able to display a high quality image (Paragraph [0051]).
Claim 3, Kim (Fig. 1-3) discloses further comprising data lines (D2; Fig. 2) arranged along the first direction (Fig. 2; wherein figure shows first direction as horizontal direction) in the display area (100; Fig. 1), the data lines (D2; Fig. 2) comprising a first data line electrically connected to the first pixel circuit (Fig. 2; wherein figure shows a data line D2 connected to the transistor MR2), a second data line electrically connected to the second pixel circuit (Fig. 2; wherein figure shows a data line D2 connected to the transistor MG2), and a third data line electrically connected to the third pixel circuit (Fig. 2; wherein figure shows a data line D2 connected to the transistor MB2).
Claim 4, Kim (Fig. 1-3) discloses wherein each of the first pixel circuit (Fig. 2; wherein figure shows a red subpixel), the second pixel circuit (Fig. 2; wherein figure shows a green subpixel), and the third pixel circuit (Fig. 2; wherein figure shows a blue subpixel) comprises:
a first transistor (MR1, MG1, and MB1; Fig. 2) configured to adjust a driving current (Paragraph [0029]) in response to a data voltage transmitted from the first data line (Fig. 2; wherein figure shows a data line D2 connected to the transistor MR2), the second data line (Fig. 2; wherein figure shows a data line D2 connected to the transistor MG2), or the third data line (Fig. 2; wherein figure shows a data line D2 connected to the transistor MB2); and
a second transistor (MR2, MG2, and MB2; Fig. 2) electrically connected between the first data line (Fig. 2; wherein figure shows a data line D2 connected to the transistor MR2), the second data line (Fig. 2; wherein figure shows a data line D2 connected to the transistor MG2), or the third data line (Fig. 2; wherein figure shows a data line D2 connected to the transistor MB2) and the first transistor (MR1, MG1, and MB1; Fig. 2).
Claim 10, Kim (Fig. 1-3) discloses wherein the first emission control line (E3; Fig. 2) and the second emission control line (E4; Fig. 2) are adjacent to each other in the second direction (Fig. 2; wherein figure shows the second direction as the vertical direction) and extend in the first direction (Fig. 2; wherein figure shows the first direction as the horizontal direction).
Claim 17, Asano (Fig. 1-22) discloses wherein the first data line (SGL103; Fig. 9) is located between a data line (SGL102; Fig. 9) electrically connected to a third sub-pixel (101; Fig. 9; wherein pixel arrangement repeats) of another pixel (Fig. 9) adjacent to the first sub-pixel (101; Fig. 9; wherein pixel arrangement repeats) in the first direction (Fig. 9; wherein figure shows first direction as horizontal direction) and the first power line (VCCL103; Fig. 9),
wherein (Fig. 9; wherein pixel arrangement repeats) the second data line (SGL101; Fig. 9) is located between the first power line (VCCL103; Fig. 9) and the other first power line (VCCL101; Fig. 9), and
wherein the third data line (SGL102; Fig. 9) is located between the other first power line (VCL101; Fig. 9) and a data line (SGL103; Fig. 9) electrically connected to a first sub-pixel (101; Fig. 9; wherein pixel arrangement repeats) of another pixel (Fig. 9) adjacent to the third sub-pixel (101; Fig. 9; wherein pixel arrangement repeats) in the first direction (Fig. 9; wherein figure shows first direction as horizontal direction).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim’s display device by applying a pixel arrangement, as taught by Asano, so to use a display device with a pixel arrangement for providing a display device able to prevent crosstalk between pixels by relatively simple layout, able to prevent the occurrence of uneven luminance in the displayed image, able to stably and correctly supply a current of a desired value to the light emitting element of each pixel without regard to the variation of the threshold value of the active elements inside the pixels, and as a result able to display a high quality image (Paragraph [0051]).
Claims 5-6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2008/0111777 A1) in view of Asano (US 2011/0032238 A1) as applied to claim 4 above, and further in view of Dong et al (US 2026/0182172 A1).
Claim 5, Kim in view of Asano discloses the display device of claim 4.
Kim in view of Asano does not expressly disclose wherein the first transistor comprises an active layer, a gate electrode overlapping a part of the active layer, and a source electrode and a drain electrode electrically connected to different portions of the active layer.
Dong (Fig. 1-29) discloses wherein the first transistor (T3; Fig. 1) comprises an active layer (301; Fig. 4), a gate electrode (T30; Fig. 6; Paragraph [0103]) overlapping a part of the active layer (301; Fig. 4 and 6), and a source electrode (T31; Fig. 1 and 6) and a drain electrode (T32; Fig 1 and 6) electrically connected to different portions of the active layer (301; Fig. 4 and 6).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano’s display device by applying a pixel circuit arrangement, as taught by Dong, so to use a display device with a pixel circuit arrangement for providing to reduce the leakage current (Paragraph [0069]).
Claim 6, Dong (Fig. 1-29) discloses wherein the first transistors (T3; Fig. 1) of the first pixel circuit (Fig. 4; wherein figure shows semiconductor layer 103 of transistor T3 of the first pixel arranged at the left position), the second pixel circuit (Fig. 4; wherein figure shows semiconductor layer 103 of transistor T3 of the second pixel arranged at the second position), and the third pixel circuit (Fig. 4; wherein figure shows semiconductor layer 103 of transistor T3 of the third pixel arranged at the third position) are arranged sequentially along the first direction (Fig. 4; wherein figure shows first direction as the horizontal direction),
wherein the drain electrode (T32; Fig. 6) of the first transistor (T3; Fig. 1 and 6) in the first pixel circuit (Fig. 4; wherein figure shows transistor T3 of the first pixel arranged at the left position) and the source electrode (T31; Fig. 6) of the first transistor (T3; Fig. 1) in the second pixel circuit (Fig. 4; wherein figure shows transistor T3 of the second pixel arranged at the second position) are adjacent to each other in the first direction (Fig. 4; wherein figure shows first direction as the horizontal direction), and
wherein the drain electrode (T32; Fig. 6) of the first transistor (T3; Fig. 1) in the second pixel circuit (Fig. 4; wherein figure shows transistor T3 of the second pixel arranged at the second position) and the drain electrode (T32; Fig. 6) of the first transistor (T3; Fig. 1) in the third pixel circuit (Fig. 4; wherein figure shows transistor T3 of the third pixel arranged at the third position) are adjacent to each other in the first 9adirection (Fig. 4; wherein figure shows first direction as the horizontal direction).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano’s display device by applying a pixel circuit arrangement, as taught by Dong, so to use a display device with a pixel circuit arrangement for providing to reduce the leakage current (Paragraph [0069]).
Claim 8, Kim in view of Asano discloses the display device of claim 4.
Kim in view of Asano does not expressly disclose wherein each of the first pixel circuit, the second pixel circuit, and the third pixel circuit further comprises a third transistor and a fourth transistor comprising an oxide semiconductor, which are commonly connected to a gate electrode of the first transistor through a first connection electrode, and
wherein the third transistor and the fourth transistor of the second pixel circuit are adjacent to the third transistor and the fourth transistor of the third pixel circuit in the first direction.
Dong (Fig. 1-29) discloses wherein each of the first pixel circuit (Fig. 4; wherein figure shows the first pixel arranged at the left position), the second pixel circuit (Fig. 4; wherein figure shows the second pixel arranged at the second position), and the third pixel circuit (Fig. 4; wherein figure shows the third pixel arranged at the third position) further comprises a third transistor (T2; Fig. 1 and 6) and a fourth transistor (T1; Fig. 1 and 6) comprising an oxide semiconductor (301; Fig. 4), which are commonly connected (T1 and T2; Fig. 1) to a gate electrode (T30; Fig. 1) of the first transistor (T3; Fig. 1) through a first connection electrode (N1; Fig. 1) , and
wherein the third transistor (T2; Fig. 1 and 6) and the fourth transistor (T1; Fig. 1 and 6) of the second pixel circuit are adjacent (Fig. 4; wherein figure shows the second pixel arranged at the second position) to the third transistor (T2; Fig. 1 and 6) and the fourth transistor (T1; Fig. 1 and 6) of the third pixel circuit (Fig. 4; wherein figure shows the third pixel arranged at the third position) in the first direction (Fig. 4 and 6; wherein figure shows first direction as the horizontal direction).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano’s display device by applying a pixel circuit arrangement, as taught by Dong, so to use a display device with a pixel circuit arrangement for providing to reduce the leakage current (Paragraph [0069]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2008/0111777 A1) in view of Asano (US 2011/0032238 A1) as applied to claim 4 above, and further in view of Mou et al (US 2022/0399417 A1).
Claim 7, Kim in view of Asano discloses the display device of claim 4.
Kim in view of Asano does not expressly disclose wherein a size of the first transistor in the first pixel circuit is different from a size of the first transistor in each of the second pixel circuit and the third pixel circuit.
Mou (Fig. 1A-12) discloses wherein a size of the first transistor (T1; Fig. 9A) in the first pixel circuit (110; Fig. 9A) is different from a size of the first transistor (T1; Fig. 9A) in each of the second pixel circuit (120; Fig. 9A) and the third pixel circuit (120; Fig. 9A).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano’s display device by applying different sized driving transistors, as taught by Mou, so to use a display device with different sized driving transistors for improving the brightness of a display device including the array substrate by optimizing channel width-length ratios of driving transistors of sub-pixels with different colors on the array substrate (Paragraph [0067]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2008/0111777 A1) in view of Asano (US 2011/0032238 A1) and Dong et al (US 2026/0182172 A1) as applied to claim 8 above, and further in view of Choi et al (US 2022/0122549 A1).
Claim 9, Kim in view of Asano and Dong discloses the display device of claim 8.
Kim in view of Asano and Dong does not expressly disclose wherein the first power line covers the first transistor, the third transistor, and the fourth transistor in the first pixel circuit, and
wherein the other first power line covers the first transistors, the third transistors, and the fourth transistors in the second pixel circuit and the third pixel circuit.
Choi (Fig. 1-42) discloses wherein the first power line (5730; Fig. 41) covers the first transistor (T1; Fig. 35 and 38), the third transistor (T3; Fig. 35 and 38), and the fourth transistor (T4_2; Fig. 35 and 38) in the first pixel circuit (Fig. 35), and
wherein the other first power line (1730; Fig. 13) covers the first transistors (T1; Fig. 2 and 8), the third transistors (T3; Fig. 2 and 11), and the fourth transistors (T4; Fig. 2 and 11) in the second pixel circuit (PCP1; Fig. 7) and the third pixel circuit (PCP2; Fig. 7).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano and Dong’s display device by applying a layering method, as taught by Choi, so to use a display device with a layering method for improving the display quality of the display device, the conductive patterns included in the pixel circuit part have been densely formed (Paragraph [0003]).
Claims 11-13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2008/0111777 A1) in view of Asano (US 2011/0032238 A1) as applied to claims 1 and 10 above, and further in view of Choi et al (US 2022/0122549 A1).
Claim 11, Kim in view of Asano discloses the display device of claim 10.
Kim in view of Asano does not expressly disclose wherein each of the first pixel circuit, the second pixel circuit, and the third pixel circuit further comprises a fifth transistor and a sixth transistor comprising respective active layers crossing the first emission control line and the second emission control line and respective gate electrodes overlapping parts of the respective active layers.
Choi (Fig. 1-42) discloses wherein each of the first pixel circuit (PX1; Fig. 34; PCP1; Fig. 37), the second pixel circuit (PX1; Fig. 1; PCP1; Fig. 7), and the third pixel circuit (PX2; Fig. 1; PCP2; Fig. 7) further comprises a fifth transistor (T5; Fig. 2 and 35) and a sixth transistor (T6; Fig. 2 and 35) comprising respective active layers (1100; Fig. 7; 5100; Fig. 37) crossing the first emission control line (5240; Fig. 38) and the second emission control line (1230; Fig. 8) and respective gate electrodes (Fig. 38 and 8) overlapping parts of the respective active layers (1100; Fig. 7; 5100; Fig. 37).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano’s display device by applying a layering method, as taught by Choi, so to use a display device with a layering method for improving the display quality of the display device, the conductive patterns included in the pixel circuit part have been densely formed (Paragraph [0003]).
Claim 12, Choi (Fig. 1-42) discloses wherein the active layer (1100; Fig. 7; 5100; Fig. 37) of the fifth transistor (T5; Fig. 8; T5; Fig. 38) extends from one end of the active layer (1100; Fig. 7; 5100; Fig. 37) of the first transistor (T1; Fig. 8; T1; Fig. 38), has a U (1100; Fig. 7; 5100; Fig. 37; wherein figure shows a U shape) or Y shape around the first emission control line (5240; Fig. 38) and the second emission control line (1230; Fig. 8), and crosses the first emission control line (5240; Fig. 38) and the second emission control line (1230; Fig. 8), and
wherein the active layer (1100; Fig. 7; 5100; Fig. 37) of the sixth transistor (T6; Fig. 8; T6; Fig. 38) extends from an other end of the active layer (1100; Fig. 7; 5100; Fig. 37) of the first transistor (T1; Fig. 8; T1; Fig. 38), and is electrically connected to a light emitting element (OLED1; Fig. 2) located above the first pixel circuit (PX1; Fig. 34; PCP1; Fig. 37), the second pixel circuit (PX1; Fig. 1; PCP1; Fig. 7), or the third pixel circuit (PX2; Fig. 1; PCP2; Fig. 7).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano’s display device by applying a layering method, as taught by Choi, so to use a display device with a layering method for improving the display quality of the display device, the conductive patterns included in the pixel circuit part have been densely formed (Paragraph [0003]).
Claim 13, Choi (Fig. 1-42) discloses wherein one end of the active layer layer (1100; Fig. 7; 5100; Fig. 37) of the fifth transistor (T5; Fig. 8; T5; Fig. 38) is electrically connected to the first power line (ELVDD; Fig. 35) or the other first power line ELVDD; Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano’s display device by applying a layering method, as taught by Choi, so to use a display device with a layering method for improving the display quality of the display device, the conductive patterns included in the pixel circuit part have been densely formed (Paragraph [0003]).
Claim 18, Kim in view of Asano discloses the display device of claim 1.
Kim in view of Asano does not expressly disclose wherein the first sub-pixel further comprises a first light emitting element electrically connected to the first pixel circuit through a first anode contact hole overlapping the first pixel circuit,
wherein the second sub-pixel further comprises a second light emitting element electrically connected to the second pixel circuit through a second anode contact hole overlapping the second pixel circuit,
wherein the third sub-pixel further comprises a third light emitting element electrically connected to the third pixel circuit through a third anode contact hole overlapping the third pixel circuit, and
wherein the other first power line passes through a region between the second anode contact hole and the third anode contact hole.
Choi (Fig. 1-42) discloses wherein the first sub-pixel (PX1; Fig. 36) further comprises a first light emitting element (EL1; Fig. 36) electrically connected to the first pixel circuit (PCP1; Fig. 36) through a first anode (ADE1; Fig. 36) contact hole (5740; Fig. 41) overlapping the first pixel circuit (PCP1; Fig. 36),
wherein the second sub-pixel (PX1; Fig. 5) further comprises a second light emitting element (EL1; Fig. 5) electrically connected to the second pixel circuit (PCP1; Fig. 5) through a second anode (ADE1; Fig. 5) contact hole (1740; Fig. 13) overlapping the second pixel circuit (PCP1; Fig. 5),
wherein the third sub-pixel (PX2; Fig. 5) further comprises a third light emitting element (EL2; Fig. 5) electrically connected to the third pixel circuit (PCP2; Fig. 5) through a third anode (ADE2; Fig. 5) contact hole (1740; Fig. 13) overlapping the third pixel circuit (PCP2; Fig. 5), and
wherein the other first power line (1730; Fig. 13) passes through a region between the second anode contact hole (1740 for PCP1; Fig. 13) and the third anode contact hole (1740 for PCP2; Fig. 13).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano’s display device by applying a layering method, as taught by Choi, so to use a display device with a layering method for improving the display quality of the display device, the conductive patterns included in the pixel circuit part have been densely formed (Paragraph [0003]).
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2008/0111777 A1) in view of Asano (US 2011/0032238 A1) and Choi et al (US 2022/0122549 A1) as applied to claims 11 and 13 above, and further in view of Choi et al (US 2023/0268465 A1).
Claim 14, Kim in view of Asano and Choi (US 2022/0122549 A1) discloses the display device of claim 13.
Kim in view of Asano and Choi (US 2022/0122549 A1) does not expressly disclose wherein the second sub-pixel and the third sub-pixel further comprise one second connection electrode overlapping the other first power line and extending in the first direction in a region where the second pixel circuit and the third pixel circuit are located, and
wherein the active layers of the fifth transistors in the second pixel circuit and the third pixel circuit are commonly connected to the one second connection electrode and are electrically connected to the other first power line through the one second connection electrode.
Choi (US 2023/0268465 A1) (Fig. 1-15) discloses wherein the second sub-pixel (PCA1; Fig. 6-14) and the third sub-pixel (PCA1; Fig. 6-14) further comprise one second connection electrode (NM21; Fig. 13) overlapping the other first power line (PL; Fig. 14) and extending in the first direction (x; Fig. 13) in a region where the second pixel circuit (PCA1; Fig. 8) and the third pixel circuit (PCA2; Fig. 8) are located (Fig. 8), and
wherein the active layers (A5; Fig. 7) of the fifth transistors (T5; Fig. 2) in the second pixel circuit (PCA1; Fig. 7; wherein connected to adjacent subpixel) and the third pixel circuit (PCA2; Fig. 7; wherein connected to adjacent subpixel) are commonly connected (T5; Fig. 2) to the one second connection electrode (NM21; Fig. 13) and are electrically connected to the other first power line (PL: Fig. 14) through the one second connection electrode (NM21; Fig. 13).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano and Choi (US 2022/0122549 A1)’s display device by applying a subpixel circuit arrangement, as taught by Choi (US 2023/0268465 A1), so to use a display device with a subpixel circuit arrangement for reducing occurrence of fine cracks may be reduced by reducing a display transformation rate due to external impacts (Paragraph [0179]).
Claim 15, Kim in view of Asano and Choi (US 2022/0122549 A1) discloses the display device of claim 11.
Kim in view of Asano and Choi (US 2022/0122549 A1) does not expressly disclose wherein the gate electrodes of the fifth transistor and the sixth transistor in the first pixel circuit are formed as one conductive pattern overlapping the first emission control line, and
wherein the one conductive pattern is electrically connected to the first emission control line through one contact hole located between the fifth transistor and the sixth transistor.
Choi (US 2023/0268465 A1) (Fig. 1-15) discloses wherein the gate electrodes (G5 and G6; Fig. 8) of the fifth transistor (T5; Fig. 2) and the sixth transistor (T6; Fig. 8) in the first pixel circuit (PCA1; Fig. 8) are formed as one conductive pattern (EMLa; Fig. 8) overlapping the first emission control line (EMLb; Fig. 13), and
wherein the one conductive pattern (EMLa; Fig. 8) is electrically connected to the first emission control line (EMLb; Fig. 13) through one contact hole (Paragraph [0170]) located between the fifth transistor (G5; Fig. 8) and the sixth transistor (G6; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano and Choi (US 2022/0122549 A1)’s display device by applying a subpixel circuit arrangement, as taught by Choi (US 2023/0268465 A1), so to use a display device with a subpixel circuit arrangement for reducing occurrence of fine cracks may be reduced by reducing a display transformation rate due to external impacts (Paragraph [0179]).
Claim 15, Kim in view of Asano and Choi (US 2022/0122549 A1) discloses the display device of claim 11.
Kim in view of Asano and Choi (US 2022/0122549 A1) does not expressly disclose wherein the gate electrodes of the fifth transistors and the sixth transistors in the second pixel circuit and the third pixel circuit are formed as one conductive pattern overlapping the second emission control line, and
wherein the one conductive pattern is electrically connected to the second emission control line through one contact hole located between the second pixel circuit and the third pixel circuit.
Choi (US 2023/0268465 A1) (Fig. 1-15) discloses wherein the gate electrodes (G5 and G6; Fig. 8) of the fifth transistors (T5; Fig. 2) and the sixth transistors (T6; Fig. 2) in the second pixel circuit (PCA1; Fig. 8) and the third pixel circuit (PCA2; Fig. 8) are formed as one conductive pattern (EMLa; Fig. 8) overlapping the second emission control line (EMLb; Fig. 13), and
wherein the one conductive pattern (EMLa; Fig. 8) is electrically connected to the second emission control line (EMLb; Fig. 13) through one contact hole (Fig. 13; wherein figures shows at least one contact hole) located between the second pixel circuit (PCA1; Fig. 13) and the third pixel circuit (PCA2; Fig. 13).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano and Choi (US 2022/0122549 A1)’s display device by applying a subpixel circuit arrangement, as taught by Choi (US 2023/0268465 A1), so to use a display device with a subpixel circuit arrangement for reducing occurrence of fine cracks may be reduced by reducing a display transformation rate due to external impacts (Paragraph [0179]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2008/0111777 A1) in view of Asano (US 2011/0032238 A1) and Choi et al (US 2022/0122549 A1) as applied to claim 18 above, and further in view of Lee et al (US 2021/0328002 A1).
Claim 19, Kim in view of Asano and Choi discloses the display device of claim 18.
Kim in view of Asano and Choi does not expressly disclose further comprising a second power line located between the first pixel circuit and the second pixel circuit, or between the pixel and another pixel adjacent to the pixel in the first direction,
wherein the second power line is electrically connected to the first light emitting element, the second light emitting element, and the third light emitting element through a cathode contact hole.
Lee (Fig. 1-13) discloses further comprising a second power line (VSL2; Fig. 9) located between the first pixel circuit and the second pixel circuit (Paragraph [0148]), or between the pixel and another pixel (Paragraph [0148]) adjacent to the pixel in the first direction (x; Fig. 9),
wherein the second power line (VSL2; Fig. 9; VSL; Fig. 11) is electrically connected to the first light emitting element (PC1; Fig. 11), the second light emitting element (PC2; Fig. 11), and the third light emitting element (PC3; Fig. 11) through a cathode contact hole (CNT; Fig. 4, 5, and 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kim in view of Asano and Choi’s display device by applying a common voltage arrangement, as taught by Lee, so to use a display device with a common voltage arrangement for providing display devices in which a voltage drop of a common electrode is prevented (Paragraph [0004]).
Conclusion
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/Adam J Snyder/Primary Examiner, Art Unit 2623 07/16/2026
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