DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US. Pub. No. 2022/0283457, hereinafter “Li”) in view of He et al. (US. Pub. No. 2021/0257429, hereinafter “He”).
As to claim 1, Li discloses a display device [figure 1, display device], comprising:
a display panel [figure 1, display panel including a display area (where pixels are) having a subpixel R/G/B and a non-display area NDA outside DA] including a display area having a subpixel and a non-display area outside of the display area; and
a driving circuit [paragraph 25, supplies the data voltage signals to the data lines 3 through a driver Integrated Circuit (IC) provided on the board] configured to drive the display panel,
wherein the non-display area includes:
a first test transistor configured to selectively detect an operation characteristic of a transistor among a plurality of subpixel transistors included in a subpixel circuit [figures 1-2, test unit 4 include a first test transistor M1 to selectively detect an operation characteristic of a transistor (of subpixel R) among a plurality of subpixel transistors in a subpixel circuit 1, paragraph 40, the source electrode 43 of the switching transistor of the test unit 4 is coupled to the sub-pixel 11 through the data line 3, that is, when an operating level is written to the gate electrode 41 of the switching transistor, the test signal written to the drain electrode 44 of the switching transistor is written to the sub-pixel 11 through the data line 3; meanwhile, the display transistor in the sub-pixel 11 is also in an operating state, so that the test signal written to the data line 3 is written to the pixel electrode, so as to test the sub-pixel 11 by testing a display effect of the sub-pixel 11]; and
a second test transistor configured to selectively detect an operation characteristic of a transistor among the plurality of subpixel transistors included in the subpixel circuit [figures 1-2, test unit 4 include a second test transistor M2 to selectively detect an operation characteristic of a transistor (of subpixel G) among a plurality of subpixel transistors in a subpixel circuit 1, paragraph 40, the source electrode 43 of the switching transistor of the test unit 4 is coupled to the sub-pixel 11 through the data line 3, that is, when an operating level is written to the gate electrode 41 of the switching transistor, the test signal written to the drain electrode 44 of the switching transistor is written to the sub-pixel 11 through the data line 3; meanwhile, the display transistor in the sub-pixel 11 is also in an operating state, so that the test signal written to the data line 3 is written to the pixel electrode, so as to test the sub-pixel 11 by testing a display effect of the sub-pixel 11].
Li does not expressly disclose a first test transistor having a different size among a plurality of subpixel transistors included in a subpixel circuit; and
a second test transistor having a different position of a gate electrode among the plurality of subpixel transistors included in the subpixel circuit.
He teaches a first transistor and a second transistor in a non-display area [figure 4, a first transistor 20 and a second transistor 30 located in non-display area (NAA)], wherein the first transistor having a different size among a plurality of subpixel transistors included in a subpixel circuit [figure 4, 20 having a different size among a plurality of subpixel transistors 60 included in a subpixel circuit] and the second transistor having a different position of a gate electrode among the plurality of subpixel transistors included in the subpixel circuit [figure 4, 30 having a different position of a gate electrode 32 among the plurality of subpixel transistors 60 included in the subpixel circuit].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Li to have the first test transistor having a different size among a plurality of subpixel transistors included in a subpixel circuit, and the second transistor having a different position of a gate electrode among the plurality of subpixel transistors included in the subpixel circuit, as taught by He, in order to achieve high performance of the display panel (He, paragraph 29).
As to claim 21, Li discloses a display panel [figure 1, display panel including a display area (where pixels are) having a subpixel R/G/B and a non-display area NDA outside DA], comprising:
a display area [figure 1, a display area (where pixels are) having a subpixel R/G/B] including a subpixel; and
a non-display area [figure 1, a non-display area NDA outside DA] outside of the display area,
wherein the non-display area includes:
a first test area including a first test transistor, the first test transistor being configured to selectively detect an operation characteristic of a transistor among a plurality of subpixel transistors constituting a subpixel circuit [figures 1-2, test unit 4 include a first test area including a first test transistor M1 to selectively detect an operation characteristic of a transistor (of subpixel R) among a plurality of subpixel transistors in a subpixel circuit 1, paragraph 40, the source electrode 43 of the switching transistor of the test unit 4 is coupled to the sub-pixel 11 through the data line 3, that is, when an operating level is written to the gate electrode 41 of the switching transistor, the test signal written to the drain electrode 44 of the switching transistor is written to the sub-pixel 11 through the data line 3; meanwhile, the display transistor in the sub-pixel 11 is also in an operating state, so that the test signal written to the data line 3 is written to the pixel electrode, so as to test the sub-pixel 11 by testing a display effect of the sub-pixel 11]; and
a second test area including a second test transistor, the second test transistor being configured to selectively detect an operation characteristic of a transistor among the plurality of subpixel transistors [figures 1-2, test unit 4 include a second test area including a second test transistor M2 to selectively detect an operation characteristic of a transistor (of subpixel G) among a plurality of subpixel transistors in a subpixel circuit 1, paragraph 40, the source electrode 43 of the switching transistor of the test unit 4 is coupled to the sub-pixel 11 through the data line 3, that is, when an operating level is written to the gate electrode 41 of the switching transistor, the test signal written to the drain electrode 44 of the switching transistor is written to the sub-pixel 11 through the data line 3; meanwhile, the display transistor in the sub-pixel 11 is also in an operating state, so that the test signal written to the data line 3 is written to the pixel electrode, so as to test the sub-pixel 11 by testing a display effect of the sub-pixel 11].
Li does not expressly disclose a first test transistor having a different channel layer size among a plurality of subpixel transistors constituting a subpixel circuit; and
a second test transistor having a different gate electrode position among the plurality of subpixel transistors.
He teaches a first transistor and a second transistor in a non-display area [figure 4, a first transistor 20 and a second transistor 30 located in non-display area (NAA)], wherein the first transistor having a different channel layer size among a plurality of subpixel transistors constituting in a subpixel circuit [figure 4, 20 having a different size among a plurality of subpixel transistors 60 constituting in a subpixel circuit] and the second transistor having a different gate electrode position among the plurality of subpixel transistors included in the subpixel circuit [figure 4, 30 having a different gate electrode position 32 among the plurality of subpixel transistors 60 included in the subpixel circuit].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Li to have the first test transistor having a different channel layer size among a plurality of subpixel transistors constituting a subpixel circuit, and the second transistor having a different gate electrode position among the plurality of subpixel transistors, as taught by He, in order to achieve high performance of the display panel (He, paragraph 29).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Na et al. (US. Pub. No. 2015/0356920, hereinafter “Na”).
As to claim 22, Li discloses a display panel [figure 1, display panel including a display area (where pixels are) having a subpixel R/G/B and a non-display area NDA outside DA] comprising:
a plurality of subpixels [figure 1, a plurality of subpixels 11 to display an image] configured to display an image; and
a test transistor configured to detect operation characteristics of at least two different transistors included in a same subpixel circuit corresponding to one of the plurality of subpixels [figure 1, a test unit comprising transistor to detect operation characteristics of at least two different transistors (transistors of sub-pixels R, G and B) included in a same subpixel circuit 11, paragraph 40, the source electrode 43 of the switching transistor of the test unit 4 is coupled to the sub-pixel 11 through the data line 3, that is, when an operating level is written to the gate electrode 41 of the switching transistor, the test signal written to the drain electrode 44 of the switching transistor is written to the sub-pixel 11 through the data line 3; meanwhile, the display transistor in the sub-pixel 11 is also in an operating state, so that the test signal written to the data line 3 is written to the pixel electrode, so as to test the sub-pixel 11 by testing a display effect of the sub-pixel 11].
Li does not expressly disclose wherein the at least two different transistors have different structures.
Na teaches two different transistors in a same subpixel circuit have different structures [figure 2, T2 and T3 in a same subpixel circuit having different structures as seen in figure 6 (T2 has U shape electrode, T3 has I shape electrode)].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Li to the at least two different transistors have different structures, as taught by Na, in order to provide a display in which subpixels are optimized and use area is maximized, thereby realizing a high-resolution display (Na, paragraph 9).
Claim(s) 23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Na, further in view of Moon et al. (US. Pub. No. 2021/0202634, hereinafter “Moon”).
As to claim 23, Li, as modified by Na, discloses the display panel of claim 22.
Li, as modified by Na, does not disclose wherein the test transistor includes:
a first upper gate electrode;
a second upper gate electrode; and
a lower gate electrode,
wherein the first upper gate electrode and the second upper gate electrode overlap with the lower gate electrode.
Moon teaches a transistor [figure 1, transistor 330] includes:
a first upper gate electrode [figure 1, a first upper gate electrode 333];
a second upper gate electrode [figure 1, a second upper gate electrode 152]; and
a lower gate electrode [figure 1, a lower gate electrode 151],
wherein the first upper gate electrode and the second upper gate electrode overlap with the lower gate electrode [figure 1, 333 and 152 overlap with 151].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Li to have the test transistor includes: a first upper gate electrode; a second upper gate electrode; and a lower gate electrode, wherein the first upper gate electrode and the second upper gate electrode overlap with the lower gate electrode, as taught by Moon, since it is a use of known technique to improve similar devices in the same way.
As to claim 25, Li, as modified by Na, discloses the display panel of claim 22.
Li, as modified by Na, does not disclose wherein the test transistor includes:
a first lower gate electrode;
a second lower gate electrode; and
an upper gate electrode,
wherein the upper gate electrode overlaps with a part of the first lower gate electrode and a part of the second lower gate electrode.
Moon teaches a transistor [figure 1, transistor 330] includes:
a first lower gate electrode [figure 1, a first lower gate electrode 152];
a second lower gate electrode [figure 1, a first lower gate electrode 151]; and
an upper gate electrode [figure 1, an upper gate electrode 333],
wherein the upper gate electrode overlaps with a part of the first lower gate electrode and a part of the second lower gate electrode [figure 1, 333 and 152 overlap with 151].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have modified the display device of Li to have the test transistor includes: a first lower gate electrode; a second lower gate electrode; and an upper gate electrode, wherein the upper gate electrode overlaps with a part of the first lower gate electrode and a part of the second lower gate electrode, as taught by Moon, since it is a use of known technique to improve similar devices in the same way.
Allowable Subject Matter
Claims 2-20, 24 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, made of record, singularly or in combination, teaches or fairly suggests the features presented in the combination limitations of dependent claims 2, 8, 15, 18, 24 and 26, such as “wherein the first test transistor includes: a base metal layer; a first insulation layer disposed on an upper portion of the base metal layer; a lower gate electrode disposed on an upper portion of the first insulation layer; a second insulation layer disposed on an upper portion of the lower gate electrode; a plurality of upper gate electrodes disposed on an upper portion of the second insulation layer; and a connection line electrically connecting the lower gate electrode and the base metal layer”, recited by claim 2; “wherein the second test transistor includes: a base metal layer; a first insulation layer disposed on an upper portion of the base metal layer; a first lower gate electrode disposed on an upper portion of the first insulation layer; a second insulation layer disposed on an upper portion of the first lower gate electrode; a second lower gate electrode disposed on an upper portion of the second insulation layer; a third insulation layer disposed on an upper portion of the second lower gate electrode; an upper gate electrode disposed on an upper portion of the third insulation layer; a first connection line electrically connecting the first lower gate electrode and the base metal layer; and a second connection line electrically connecting the second lower gate electrode and the base metal layer”, recited by claim 8; “a third test transistor configured to selectively detect an operation characteristic of a transistor having a different channel layer size and an operation characteristic of a transistor having a different gate electrode position among the plurality of subpixel transistors included in the subpixel circuit”, recited by claim 15; “a fourth test transistor configured to selectively detect an operation characteristic of three or more transistors having different channel layer sizes and different gate electrode positions among the plurality of subpixel transistors included in the subpixel circuit”, recited by claim 18; “wherein the test transistor is configured to: detect a first operation characteristic of a first transistor included in the same subpixel circuit having a first channel width corresponding to a width of the first upper gate electrode by selecting the first upper gate electrode and the lower gate electrode, and detect a second operation characteristic of a second transistor included in the same subpixel circuit having a second channel width corresponding to a width of the second upper gate electrode by selecting the second upper gate electrode and the lower gate electrode, wherein the first channel width is different than the second channel width”, recited by claim 24; and “wherein the test transistor is configured to: detect a first operation characteristic of a first transistor included in the same subpixel by selecting the first lower gate electrode and the upper gate electrode, and detect a second operation characteristic of a second transistor included in the same subpixel circuit by selecting the second lower gate electrode and the upper gate electrode, wherein the first transistor and the second transistor have lower gate electrodes disposed on different layers within the same subpixel circuit”, recited by claim 26.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ju et al. (US. Pub. No. 2023/0146971) is considered as pertinent art to claims 1, 21 and 22 as seen in figure 3, wherein text pixels 220 are located in the non-display area.
Lee et al. (US. Pub. No. 2021/0248938) is also considered as pertinent art to claims 1, 21 and 22 relating to test transistor T1-To as seen in figure 2.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAN-YING YANG whose telephone number is (571)272-2211. The examiner can normally be reached Monday-Friday, 8am-5pm, EST.
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/NAN-YING YANG/ Primary Examiner, Art Unit 2629
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