DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 13-14 are objected to because of the following informalities:
Regarding claims 13-14, the limitations “a first node” and “a second node” should be amended to read ---the first node---and ---the second node---.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9, 11-13 and 19-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yoshida et al. (US 2019/0164509).
Regarding claim 1, Yoshida discloses a shift register (Fig. 6; [0056], [0072], e.g., a shift register) comprising:
a plurality of unit circuits (e.g., a plurality of unit circuits SR1-SRn), each of the plurality of unit circuits including
a first circuit to which a set signal is input (Fig. 9, [0082]-[0083], [0088], e.g., a set signal SET is input to a first circuit 41),
a second circuit to which a reset signal is input (e.g., a reset signal RESET is input to a second circuit 42), a first transistor ([0084], e.g., a first transistor 47), a second transistor (e.g., a second transistor 46),
a first node connected to a gate terminal of the first transistor (e.g., a first node netA is connected to a gate of the first transistor 47), a second node connected to a gate terminal of the second transistor (e.g., a second node netB is connected to a gate of the second transistor 46), and a third transistor whose gate terminal is connected to the first node (e.g., a gate of a third transistor 44 is connected to the first node netA), and a third transistor whose gate terminal is connected to the first node (e.g., a gate terminal of a third transistor 44 is connected to first node netA),
wherein each of the plurality of unit circuits includes a third circuit ([0091], e.g., a third circuit x3), the second node is connected to a first power supply via the third transistor and the third circuit (e.g., the second node netB is connected to a first power supply Vgl2 via the third transistor 44 and the third circuit x3), and a control signal is input to the third circuit (e.g., a control signal from the first node netA is input to the third circuit x3).
Regarding claim 2, Yoshida further discloses the shift register according to claim 1, wherein the third circuit includes a fourth transistor (Fig. 9; e.g., the third circuit is a fourth transistor x3), the second node is connected to the first power supply via the third transistor and the fourth transistor (e.g., the second node netB is connected to a first power supply Vgl2 via the third transistor 44 and the fourth transistor x3, and the control signal is input to a gate terminal of the fourth transistor (e.g., a control signal from the first node netA is input to the gate terminal of the fourth transistor x3).
Regarding claim 3, Yoshida further discloses the shift register according to claim 2, wherein the fourth transistor is turned off by the control signal during an active period of the reset signal ([0086], e.g., when the reset pulse signal is input, the node netA is set to the low level so that the fourth transistor x3 is turned off).
Regarding claim 4, Yoshida further discloses the shift register according to claim 2, wherein the control signal and the reset signal are in an opposite phase relationship during an active period of the reset signal ([0086], e.g., when the reset pulse signal is input, the node netA is set to the low level thus the control signal from the node netA and the reset signal are in an opposite phase during an active period of the reset signal).
Regarding claim 5, Yoshida further discloses the shift register according to claim 2, wherein the fourth transistor is turned on by the control signal during an active period of the set signal (Figs 9A-9B; [0086], e.g., the fourth transistor x3 is turned on during an active period of the set signal SET).
Regarding claim 6, Yoshida further discloses the shift register according to claim 1, wherein each of the plurality of unit circuits includes an output terminal connected to one conduction terminal of the first transistor (Fig. 9; e.g., an output terminal GOUT is connected to one conduction terminal of the first transistor 47) and one conduction terminal of the second transistor (e.g., one conduction terminal of the second transistor 46).
Regarding claim 9, Yoshida further discloses the shift register according to claim 1, wherein the reset signal is an output of a unit circuit located following the current stage (see Fig. 6).
Regarding claim 11, Yoshida further discloses the shift register according to claim 1, wherein each of the plurality of unit circuits includes a fifth transistor including a gate terminal connected to the second node (Fig. 9; e.g., a gate terminal of fifth transistor x4 is connected to the second node netB), and the first node is connected to the first power supply via the fifth transistor ([0093], e.g., the first node netA is connected to the first power supply Vgl2 via the fifth transistor x4).
Regarding claim 12, Yoshida further discloses the shift register according to claim 1, wherein each of the plurality of unit circuits includes a sixth transistor including a gate terminal to which an initialization signal is input (Fig. 9; e.g., a gate terminal of a sixth transistor 43 is connected to VDD), and the second node is connected to a second power supply via the sixth transistor (e.g., the second node netB is connected to VDD via the sixth transistor 43).
Regarding claim 13, Yoshida further discloses the shift register according to claim 1, wherein the first circuit includes a set transistor to which the set signal is input and which is connected to a first node (Fig. 9; e.g., a set transistor 41 is connected to the first node netA), and the second circuit includes a reset transistor to which the reset signal is input and which is connected to a second node (e.g., a reset transistor 42 is connected to the second node netB).
Regarding claim 19, Yoshida further discloses a display device comprising: the shift register according to claim 1 ([0123]).
Regarding claim 20, Yoshida discloses a method of driving a shift register (Fig. 6; [0056], [0072], e.g., a shift register) comprising:
a plurality of unit circuits (e.g., a plurality of unit circuits SR1-SRn),
each of the plurality of unit circuits including a first circuit to which a set signal is input, a second circuit to which a reset signal is input, a first transistor, a second transistor (Fig. 9, [0082]-[0083], [0088], e.g., a set signal SET is input to a first circuit 41), a second circuit to which a reset signal is input (e.g., a reset signal RESET is input to a second circuit 42), a first transistor ([0084], e.g., a first transistor 47), a second transistor (e.g., a second transistor 46),
a first node connected to a gate terminal of the first transistor (e.g., a first node netA is connected to a gate of the first transistor 47), a second node connected to a gate terminal of the second transistor (e.g., a second node netB is connected to a gate of the second transistor 46), and a third transistor whose gate terminal is connected to the first node (e.g., a gate of a third transistor 44 is connected to the first node netA), a third transistor whose gate terminal is connected to the first node (e.g., a gate terminal of a third transistor 44 is connected to first node netA), and a fourth transistor ([0091], e.g., a fourth transistor x3), the second node being connected to a first power supply via the third transistor and the fourth transistor (e.g., the second node netB is connected to a first power supply Vgl2 via the third transistor 44 and the fourth transistor x3), wherein the fourth transistor is turned off during an active period of the reset signal ([0086], e.g., when the reset pulse signal is input, the node netA is set to the low level so that the fourth transistor x3 is turned off).
Allowable Subject Matter
Claims 7-8, 10, 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for indicating allowable subject matter is that claim 7 recites “wherein clock signals of a plurality of phases are input to the plurality of unit circuits, one of the clock signals of the plurality of phases is input to another conduction terminal of the first transistor, and another conduction terminal of the second transistor is connected to the first power supply” which, in combination with the other recited features, are not taught and/or suggested either singularly or in combination within the prior art.
The primary reason for indicating allowable subject matter is that claim 14 recites “wherein the first circuit includes a set auxiliary transistor to which the set signal is input and which is connected to a second node, and the second circuit includes a reset auxiliary transistor to which the reset signal is input and which is connected to a first node” which, in combination with the other recited features, are not taught and/or suggested either singularly or in combination within the prior art.
The primary reason for indicating allowable subject matter is that claim 15 recites “wherein each of the plurality of unit circuits includes a seventh transistor including a gate terminal connected to the first node, an eighth transistor including a gate terminal connected to the second node, and a third node, the third node is connected to the first power supply via the fifth transistor, the third node is connected to a second power supply via the seventh transistor, and the third node is connected to the first node via the eighth transistor” which, in combination with the other recited features, are not taught and/or suggested either singularly or in combination within the prior art.
The primary reason for indicating allowable subject matter is that claim 16 recites “wherein each of the plurality of unit circuits includes a fourth circuit connected to the output terminal, a switching signal that is set to be in an active state during at least a part of a touch detection period is input to the fourth circuit, the fourth circuit fixes the output terminal to a potential of the first power supply during a period in which the switching signal is in an active state, and the switching signal is input to the third circuit as the control signal” which, in combination with the other recited features, are not taught and/or suggested either singularly or in combination within the prior art.
The primary reason for indicating allowable subject matter is that claim 17 recites “wherein the control signal turns off the fourth transistor during a shift operation period and turns on the fourth transistor during a shift stop period” which, in combination with the other recited features, are not taught and/or suggested either singularly or in combination within the prior art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sasaki et al. (US 2022/0246104) discloses a shift register comprising a plurality of unit circuits, each of the plurality of unit circuits including a first circuit to which a set signal is input, a second circuit to which a reset signal is input, a first transistor, a second transistor, a first node connected to a gate terminal of the first transistor, a second node connected to a gate terminal of the second transistor, and a third transistor whose gate terminal is connected to the first node, wherein the second node is connected to a first power supply via the third transistor (Figs 6-7).
Takahashi (US 2013/0033468) discloses a shift register comprising a plurality of unit circuits, each of the plurality of unit circuits including a first circuit to which a set signal is input, a second circuit to which a reset signal is input, a first transistor, a second transistor, a first node connected to a gate terminal of the first transistor, a second node connected to a gate terminal of the second transistor, and a third transistor, wherein the second node is connected to a first power supply via the third transistor (Figs 4-6).
Qing et al. (US 2014/0064439) discloses a shift register wherein a first circuit includes a set transistor and a set auxiliary transistor and a second circuit includes a reset transistor and a reset auxiliary transistor (Figs 9-10).
HAO et al. (US 2018/0174548) discloses a shift register wherein a resister is connected between a first transistor and a second transistor to avoid a short circuit between a first power supply end and a second power supply end (Figs 5-7).
GU et al. (US 2017/0199617) discloses a shift register provided in a display device equipped with a touch sensor (Figs 2-7).
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/HONG ZHOU/Primary Examiner, Art Unit 2629
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