Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Amendment filed on 06/25/2026.
In the instant Amendment, claim 1 has been amended and claim 9 has been cancelled. Claims 1 and 11 are independent claims. Claims 1-8 and 10-19 have been examined and are pending. This Action is made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 06/25/2026, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicants’ arguments with respect to claims 1-19 have been considered but are moot in view of the new ground(s) of rejection.
Priority
This application is a continuation-in-part, and claims the benefit of, U.S. Application Serial No. 18/397,790 filed December 27, 2023, which claims benefit of U.S. Provisional Application Serial No. 63/541,599, filed September 29, 2023, and this application claims the benefit of U.S. Provisional Application Serial No. 63/868,798 filed August 22, 2025, the entire disclosures of which are incorporated herein by reference.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Adham (US 2019/0165956); in view of Esbensen (US 2022/0004648) and further in view of Lin (US 2021/0232744).
Regarding claim 1, Adham discloses a multimodal integrated circuit (IC) chip with native-speed encrypted data processing for use in cryptography (Adham abstract; Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) generator. Unstable bits of the plurality of key bits are identified, and a security key is generated based on the plurality of key bits, wherein the security key excludes the identified unstable bits. See also par. 0027 and 0046), the IC chip comprising:
a chip substrate (Adham par. 0015; Integrated circuit (IC) devices generally include electronic circuits formed on a semiconductor substrate, or “chip,” formed of a semiconductor material such as silicon);
a memory positioned on the chip substrate, wherein when key bits from key data are stored on the memory (Adham par. 0025; The unstable bit information is used to generate a security key or multiple keys. The identified unstable bits may be stored in the unstable bit memory 110, such as a nonvolatile memory provided on chip), unauthorized access of the key bits is prevented (Adham par. 0047; A memory stores unstable bits of the plurality of key bits, and a controller is configured to generate a security key in response to receiving a challenge, wherein generating the security key includes accessing the memory and excluding the unstable bits from the security key); and
at least one processing device positioned on the chip substrate (Adham par. 0018, 0019 and 0048; As noted above, the security key is provided in response to a received challenge, and is unique to the particular IC device 10 due to inherent variations resulting from the manufacturing process for the device. In some examples, the PUF generator 120 includes a memory array, such as an SRAM memory array, where the memory cells of the array generate key bits of the security key. The size of the SRAM array may be determined based on the size of the required security key(s). The processing memory 122 is an SRAM. A request for a security key is received in the form of a challenge. A challenge-response processor 124 handles such a request).
Adham teaches, a processor is configured to compare the first and second occurrences of the first key bit to identify an unstable key bit (Adham par. 0015 and 0048). However, Adham does not explicitly disclose wherein unauthorized access of the key bits is prevented by physically blocking a read out of the key bits from the chip substrate ; and key data is processable with the at least one processing device based on an externally-originating operation.
However, in an analogous art, Esbensen teaches wherein unauthorized access of the key bits is prevented by physically blocking a read out of the key bits from the chip substrate (Esbensen par. 0159 and 0170; The block of random bits used during encryption to be destroyed or deleted after encryption, namely, to prevent that block of random bits for being accessible to someone who inadvertently gains access to the TRNG disk 1112A on the device 1140. By destroying the block of random bits that's used during encryption, even if the device 1140 falls into untrusted hands, the specific block of random bits used for encryption cannot be discovered. This ensures that the only decryption of the encrypted data can occur by an authorized party. n other examples, the system and method can be used to prevent data stored on a particular device from being accessed by someone who has physical control over that device yet does not have permission to access the data).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Esbensen with the method and system of Adham, wherein unauthorized access of the key bits is prevented by physically blocking a read out of the key bits from the chip substrate to provide users with a means for securing data using random a plurality of random bits (Esbensen abstract).
Adham and Esbensen teach, a processor is configured to compare the first and second occurrences of the first key bit to identify an unstable key bit (Adham par. 0015 and 0048) and the controller unit 306 has access to a random number generator which located external to it (Esbensen par. 00600). However, Adham and Esbensen do not explicitly disclose wherein key data is processable with the at least one processing device based on an externally-originating operation.
However, in an analogous art, Lin teaches wherein key data is processable with the at least one processing device based on an externally-originating operation (Lin par. 0026, 0070 and 0417; Another aspect of the disclosure provides the standard commodity logic drive in a multi-chip package comprising the plural standard commodity FPGA IC chips, the dedicated I/O chip, the dedicated control chip and the one or more non-volatile memory IC chips, for use in different applications requiring logic, computing and/or processing functions by field programming. The communication between the chips of the logic drive and the communication between each chip of the logic drive and the external or outside (of the logic drive) are described as follows: (1) the dedicated I/O chip communicates directly with the other chip or chips of the logic drive, and also communicates directly with the external or outside (circuits) (of the logic drive). The on-chip security circuit is used for preventing from the unintended copy, use or reverse engineering. The on-chip security circuit on the FPGA IC chip in the non-volatile programmable logic device provides the on-chip bitstream decryption based on a decryption key stored in the dedicated memory cells on the FPGA IC chip. The encrypted bitstream are stored in the non-volatile memory chip of the non-volatile programmable logic device, and to be used for configuring the FPGA IC chip of the non-volatile programmable logic device. The encrypted bitstream from the non-volatile memory chip are input into the FPGA IC chip for the programmable interconnection (switches including pass-no-pass switching gates and multiplexers) and/or programmable logic circuits, cells, elements or blocks (including LUTs and multiplexers) on the FPGA IC chip. for the dedicated control chip 260, dedicated control and I/O chip 266, DCIAC chip 267 or DCDI/OIAC chip 268 in the control block 360, one of its large I/O circuits 341 may receive or drive a control command from or to the external circuitry 271 outside the logic drive 300. See also par. 0420).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Lin with the method and system of Adham and Esbensen, wherein at least one processing device positioned on the chip substrate, wherein key data is processable with the at least one processing device based on an externally-originating operation to provide a standardized commodity logic drive in a multi-chip package comprising plural FPGA IC chips and one or more non-volatile memory IC chips for use in different applications requiring logic, computing and/or processing functions by field programming (Lin par. 0004).
Regarding claim 2, Adham, Esbensen and Lin disclose the IC chip of claim 1,
Lin further discloses wherein the at least one processing device further comprises at least one of: a central processing unit (CPU) or a field programmable gate array (FPGA) (Lin par. 0002 and 0034; The Field Programmable Gate Array (FPGA) semiconductor integrated circuit (IC) has been used for development of new or innovated applications, or for small volume applications or business demands. Another aspect of the disclosure provides the logic drive in a multi-chip package comprising plural standard commodity FPGA IC chips and one or more non-volatile IC chips, further comprising a processing and/or computing IC chip, for example, a Central Processing Unit (CPU) chip).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Lin with the method and system of Adham and Esbensen, wherein at least one processing device positioned on the chip substrate, wherein key data is processable with the at least one processing device based on an externally-originating operation to provide a standardized commodity logic drive in a multi-chip package comprising plural FPGA IC chips and one or more non-volatile memory IC chips for use in different applications requiring logic, computing and/or processing functions by field programming (Lin par. 0004).
Regarding claim 3, Adham, Esbensen and Lin disclose the IC chip of claim 2,
Lin further discloses wherein when the at least one processing device is a FPGA, the FPGA executes operations in parallel to a processor (Lin par. 0036; The standard commodity FPGA IC chips provide (1) programmable-metal-line (field-programmable) interconnects for (field-programmable) functions, processors and operations and (2) fixed-metal-line (non-field-programmable) interconnects for (non-field-programmable) functions, processors and operations. Once the programmable-metal-line interconnects in or of the FPGA IC chips are programmed, the FPGA IC chips together with the processing and/or computing IC chip or chips in the same logic drive provide powerful functions and operations in applications, for example, Artificial Intelligence (AI), machine learning, deep learning, big data, Internet Of Things (JOT), Virtual Reality (VR), Augmented Reality (AR), driverless car electronics, Graphic Processing (GP), Digital Signal Processing (DSP), Micro Controlling (MC), and/or Central Processing (CP)).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Lin with the method and system of Adham and Esbensen, wherein at least one processing device positioned on the chip substrate, wherein key data is processable with the at least one processing device based on an externally-originating operation to provide a standardized commodity logic drive in a multi-chip package comprising plural FPGA IC chips and one or more non-volatile memory IC chips for use in different applications requiring logic, computing and/or processing functions by field programming (Lin par. 0004).
Regarding claim 4, Adham, Esbensen and Lin disclose the IC chip of claim 2,
Lin further discloses wherein the at least one processing device further comprises a combined CPU FPGA (Lin par. 0034; Another aspect of the disclosure provides the logic drive in a multi-chip package comprising plural standard commodity FPGA IC chips and one or more non-volatile IC chips, further comprising a processing and/or computing IC chip, for example, a Central Processing Unit (CPU) chip. See also par. 0036).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Lin with the method and system of Adham and Esbensen, wherein at least one processing device positioned on the chip substrate, wherein key data is processable with the at least one processing device based on an externally-originating operation to provide a standardized commodity logic drive in a multi-chip package comprising plural FPGA IC chips and one or more non-volatile memory IC chips for use in different applications requiring logic, computing and/or processing functions by field programming (Lin par. 0004).
Regarding claim 5, Adham, Esbensen and Lin disclose the IC chip of claim 4,
Lin further discloses wherein the FPGA of the combined CPU FPGA executes operations in parallel to the CPU of the combined CPU FPGA (Lin par. 0034 and 0036; Another aspect of the disclosure provides the logic drive in a multi-chip package comprising plural standard commodity FPGA IC chips and one or more non-volatile IC chips, further comprising a processing and/or computing IC chip, for example, a Central Processing Unit (CPU) chip. The standard commodity FPGA IC chips provide (1) programmable-metal-line (field-programmable) interconnects for (field-programmable) functions, processors and operations and (2) fixed-metal-line (non-field-programmable) interconnects for (non-field-programmable) functions, processors and operations. Once the programmable-metal-line interconnects in or of the FPGA IC chips are programmed, the FPGA IC chips together with the processing and/or computing IC chip or chips in the same logic drive provide powerful functions and operations in applications).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Lin with the method and system of Adham and Esbensen, wherein at least one processing device positioned on the chip substrate, wherein key data is processable with the at least one processing device based on an externally-originating operation to provide a standardized commodity logic drive in a multi-chip package comprising plural FPGA IC chips and one or more non-volatile memory IC chips for use in different applications requiring logic, computing and/or processing functions by field programming (Lin par. 0004).
Regarding claim 6, Adham, Esbensen and Lin disclose the IC chip of claim 1,
Adham further discloses wherein the externally-originating operation is encrypted (Adham par. 0040; The database is generated from test data collected at a plurality of test stages. As noted above, saving unstable bits in an on-chip memory may reduce the amount of data eventually saved on an external server. FIG. 6 illustrates an example process 430 that may be used to generate one or more security keys).
Lin further disclose the encrypted bitstream are stored in the non-volatile memory chip of the non-volatile programmable logic device, and to be used for configuring the FPGA IC chip of the non-volatile programmable logic device (Lin par. 0070).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Lin with the method and system of Adham and Esbensen, wherein at least one processing device positioned on the chip substrate, wherein key data is processable with the at least one processing device based on an externally-originating operation to provide a standardized commodity logic drive in a multi-chip package comprising plural FPGA IC chips and one or more non-volatile memory IC chips for use in different applications requiring logic, computing and/or processing functions by field programming (Lin par. 0004).
Regarding claim 10, Adham, Esbensen and Lin disclose the IC chip of claim 1,
Lin further discloses wherein the unauthorized access of the key bits is prevented by preventing unauthorized access from Artificial Intelligence (AI) devices (Lin par. 0033; They may write software codes to program the logic drive comprising the plural of standard commodity FPGA IC chips for their desired applications, for example, in applications of Artificial Intelligence (AI), machine learning, deep learning, big data, Internet Of Things (JOT), Virtual Reality (VR), Augmented Reality (AR), car electronics, Graphic Processing (GP), Digital Signal Processing (DSP), Micro Controlling (MC), and/or Central Processing (CP)).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Lin with the method and system of Adham and Esbensen, wherein at least one processing device positioned on the chip substrate, wherein key data is processable with the at least one processing device based on an externally-originating operation to provide a standardized commodity logic drive in a multi-chip package comprising plural FPGA IC chips and one or more non-volatile memory IC chips for use in different applications requiring logic, computing and/or processing functions by field programming (Lin par. 0004).
Regarding claims 11-16; claims 11-16 are directed to a method associated with the IC chip claimed in claims 1-6 respectively. Claims 11-16 are similar in scope to claims 1-6 respectively, and are therefore rejected under similar rationale respectively.
Regarding claim 19, Adham, Esbensen and Lin disclose The method of claim 11,
Adham further discloses wherein a read out of the key bits from the memory is blocked to prevent the unauthorized access of the key bits (Adham par. 0047; A memory stores unstable bits of the plurality of key bits, and a controller is configured to generate a security key in response to receiving a challenge, wherein generating the security key includes accessing the memory and excluding the unstable bits from the security key).
Claims 7-8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Adham (US 2019/0165956), in view of Esbensen (US 2022/0004648), in view of Lin (US 2021/0232744) and further in view of Lan (US 2010/0110282).
Regarding claim 7, Adham, Esbensen and Lin disclose the IC chip of claim 1,
Adham, Esbensen and Lin failed to disclose but Lan discloses further comprising at least one sensor positioned on the chip substrate (Lan par. 0010 and claim 8; Position of the image sensor chip and the substrate before the first adhesive deposit).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Lan with the method and system of Adham, Esbensen and Lin, wherein further comprising at least one sensor positioned on the chip substrate to provide places and fixes an image sensor chip in an opening in a substrate (Lan abstract).
Regarding claim 8, Adham, Esbensen, Lin and Lan disclose the IC chip of claim 7,
Lan further discloses wherein the at least one sensor is one or more of: an image sensor, a camera, and a biometric sensor (Lan par. 0034; correspondingly attach the opening 11 of the substrate 10 to an adhesive base 70, and then place the image sensor chip 20 in the opening 11 of the substrate 10. Since the adhesive base 70 is sticking, the adhesive base 70 is used for determining the relative position of the image sensor chip 20 and the substrate 10, and the image sensor chip 20 and the substrate 10 are fixed by the adhesive base 70).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Lan with the method and system of Adham, Esbensen and Lin, wherein further comprising at least one sensor positioned on the chip substrate to provide places and fixes an image sensor chip in an opening in a substrate (Lan abstract).
Regarding claims 17-18; claims 17-18 are directed to a method associated with the IC chip claimed in claims 7-8 respectively. Claims 17-18 are similar in scope to claims 7-8 respectively, and are therefore rejected under similar rationale respectively.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANCHIT K SARKER whose telephone number is (571)270-7907. The examiner can normally be reached M-F 8:30 AM-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FARID HOMAYOUNMEHR can be reached at 571-272-3739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SANCHIT K SARKER/Primary Examiner, Art Unit 2495
Prosecution Insights