DETAILED ACTION
Claims 1-20 filed October 27th, 2025, are pending in the current action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 10, 11, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US2016/0148569) in view of Lee (US2025/0209980)
Consider claim 1, where Park teaches a sub-pixel comprising: a sub-pixel circuit connected to a first power voltage node to which a first power voltage is input, a data line, a first sub-gate line, and a first sub-emission control line; (See Park Fig. 4 and ¶49-56 where there is a first power voltage ELVDD, a data line D1, a first gate line S1 and a first emission control line EM1) a light emitting device having a cathode electrode connected to a second power voltage node to which a second power voltage is input; (See Park Fig. 4 and ¶56 where the organic light emitting diode EL may include an anode electrode connected to the fourth node N4, a cathode electrode connected to the second power voltage ELVSS. The Examiner notes that the drawing is labeled ELVDD and the specification states ELVSS. ELVSS should be the correct label based on the described operation of the circuit in ¶48-56.) and a first transistor connected between an anode electrode of the light emitting device and the sub-pixel circuit, (See Park Fig. 4 and ¶50 where the fifth transistor TR5 may include a gate electrode connected to a second light emission control line and the other electrode connected to a fourth node N4 that is connected to an anode electrode of the organic light emitting diode EL.) wherein: the first transistor turns off in response to a first voltage input to a second sub-emission control line to which a gate electrode of the first transistor is connected, (See Park Figs 4, 5 and ¶63 where in the third period t3, the second light emission control signal EM2 may change to a high level. Accordingly, the connection between the fourth node N4 and the other electrode of the driving transistor TR2 may be interrupted.) and the first transistor turns on in response to a second voltage input to the second sub-emission control line, (See Park Figs. 4, 5 and ¶59 where in the first period t1, the first light emission control signal EM1 and the second light emission control signal EM2 may also be provided as low-level voltages, and the fourth transistor TR4 and the fifth transistor TR5 may be in a turn-on state)
Park teaches a control line EM2 that is supplied a high and low voltage, however Park does not explicitly teach wherein a third voltage having a voltage value different from the first voltage and the second voltage is input to the second sub-emission control line during an emission period in which a driving current is supplied from the sub-pixel circuit to the light emitting device. However, in an analogous field of endeavor Lee teaches wherein a third voltage having a voltage value different from the first voltage and the second voltage is input to the second sub-emission control line during an emission period in which a driving current is supplied from the sub-pixel circuit to the light emitting device. (See Lee Figs. 4, 7 and ¶94-95 where the magnitude of the driving current may be adjusted in response to voltages of the gate electrodes of the third and fourth transistors T3 and T4 (see FIG. 4), that is, the gate high voltages VEH of the emission signals EM1 and EM2. The second gate high voltage Vadj may be determined in response to the luminance difference between adjacent frames. In addition, the second gate high voltage Vadj may be smaller than the first gate high voltage Vori.) Therefore, it would have been obvious for one of ordinary skill in the art to adjust the voltage of Park by adjusting the voltage of the emission signals as taught by Lee. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of restricting the luminance when the image data changes significantly to reduce the magnitude of the change. (See Lee ¶94)
Consider claim 2, where Park in view of Lee teaches the sub-pixel according to claim 1, wherein the third voltage has a voltage value between the first voltage and the second voltage. (See Lee Figs. 4, 7 and ¶94-95 where the magnitude of the driving current may be adjusted in response to voltages of the gate electrodes of the third and fourth transistors T3 and T4 (see FIG. 4), that is, the gate high voltages VEH of the emission signals EM1 and EM2. The second gate high voltage Vadj may be determined in response to the luminance difference between adjacent frames. In addition, the second gate high voltage Vadj may be smaller than the first gate high voltage Vori.)
Consider claim 10, where Park teaches a display device, comprising: sub-pixels connected to data lines, gate lines, and emission control lines; (See Park Fig. 4 and ¶49-56 where there is a first power voltage ELVDD, a data line D1, a first gate line S1 and a first emission control line EM1) a gate driver which drives the gate lines and the emission control lines; and a data driver which drives the data lines, (See Park Fig 1 where there is a data driver 130 and a scan driver 140) wherein: at least one of the sub-pixels comprises: a sub-pixel circuit connected to a first power voltage node to which a first power voltage is input, a data line which is one of the data lines, a first sub-gate line which is one of the gate lines, and a first sub-emission control line which is one of the emission control lines; (See Park Fig. 4 and ¶49-56 where there is a first power voltage ELVDD, a data line D1, a first gate line S1 and a first emission control line EM1) a light emitting device having a cathode electrode connected to a second power voltage node to which a second power voltage is input; (See Park Fig. 4 and ¶56 where the organic light emitting diode EL may include an anode electrode connected to the fourth node N4, a cathode electrode connected to the second power voltage ELVSS. The Examiner notes that the drawing is labeled ELVDD and the specification states ELVSS. ELVSS should be the correct label based on the described operation of the circuit in ¶48-56.) and a first transistor connected between an anode electrode of the light emitting device and the sub-pixel circuit and having a gate electrode connected to a second sub-emission control line which is one of the emission control lines, (See Park Fig. 4 and ¶50 where the fifth transistor TR5 may include a gate electrode connected to a second light emission control line and the other electrode connected to a fourth node N4 that is connected to an anode electrode of the organic light emitting diode EL.) and the gate driver supplies: a first voltage to the second sub-emission control line, wherein the first transistor turns off in response to the first voltage; (See Park Figs 4, 5 and ¶63 where in the third period t3, the second light emission control signal EM2 may change to a high level. Accordingly, the connection between the fourth node N4 and the other electrode of the driving transistor TR2 may be interrupted.) (See Park Figs. 4, 5 and ¶59 where in the first period t1, the first light emission control signal EM1 and the second light emission control signal EM2 may also be provided as low-level voltages, and the fourth transistor TR4 and the fifth transistor TR5 may be in a turn-on state)
Park teaches a control line EM2 that is supplied a high and low voltage, however Park does not explicitly teach wherein a third voltage having a voltage value different from the first voltage and the second voltage to the second sub-emission control line during an emission period in which a driving current is supplied from the sub-pixel to the light emitting device. However, in an analogous field of endeavor Lee teaches a third voltage having a voltage value different from the first voltage and the second voltage to the second sub-emission control line during an emission period in which a driving current is supplied from the sub-pixel to the light emitting device. (See Lee Figs. 4, 7 and ¶94-95 where the magnitude of the driving current may be adjusted in response to voltages of the gate electrodes of the third and fourth transistors T3 and T4 (see FIG. 4), that is, the gate high voltages VEH of the emission signals EM1 and EM2. The second gate high voltage Vadj may be determined in response to the luminance difference between adjacent frames. In addition, the second gate high voltage Vadj may be smaller than the first gate high voltage Vori.) Therefore, it would have been obvious for one of ordinary skill in the art to adjust the voltage of Park by adjusting the voltage of the emission signals as taught by Lee. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of restricting the luminance when the image data changes significantly to reduce the magnitude of the change. (See Lee ¶94)
Consider claim 11, where Park, in view of Lee teaches the display device according to claim 10, wherein the third voltage has a voltage value between the first voltage and the second voltage. (See Lee Figs. 4, 7 and ¶94-95 where the magnitude of the driving current may be adjusted in response to voltages of the gate electrodes of the third and fourth transistors T3 and T4 (see FIG. 4), that is, the gate high voltages VEH of the emission signals EM1 and EM2. The second gate high voltage Vadj may be determined in response to the luminance difference between adjacent frames. In addition, the second gate high voltage Vadj may be smaller than the first gate high voltage Vori.)
Consider claim 20, where Park teaches An electronic device, comprising: a processor; a display module which displays an image according to an image data signal input from the processor; memory which stores data information for an operation of the processor; (See Park Fig. 1 and ¶38-40 where the control unit 120 may receive a control signal CS and video signals R, G, and B from an external system. Here, the video signals R, G, and B include luminance information of the plurality of pixels PX. The luminance may have a predetermined number of gray levels, for example, 1024, 256, or 64 gray levels. The data driving unit 130 may be connected to the plurality of data lines of the display unit 110 and may generate the plurality of data voltages D1 to Dm through sampling and holding and converting the input video data DATA into an analog voltage according to the first driving control signal CONT1.) and a power module which generates power which drives the display module, wherein: the display module comprises: sub-pixels connected to data lines, gate lines, and emission control lines; (See Park Fig. 4 and ¶49-56 where there is a first power voltage ELVDD, a data line D1, a first gate line S1 and a first emission control line EM1) a gate driver which drives the gate lines and the emission control lines; and a data driver which drives the data lines, (See Park Fig 1 where there is a data driver 130 and a scan driver 140) at least one of the sub-pixels comprises: a sub-pixel circuit connected to a first power voltage node to which a first power voltage is input, a data line which is one of the data lines, a first sub-gate line which is one of the gate lines, and a first sub-emission control line which is one of the emission control lines; (See Park Fig. 4 and ¶49-56 where there is a first power voltage ELVDD, a data line D1, a first gate line S1 and a first emission control line EM1) a light emitting device having a cathode electrode connected to a second power voltage node to which a second power voltage is input; (See Park Fig. 4 and ¶56 where the organic light emitting diode EL may include an anode electrode connected to the fourth node N4, a cathode electrode connected to the second power voltage ELVSS. The Examiner notes that the drawing is labeled ELVDD and the specification states ELVSS. ELVSS should be the correct label based on the described operation of the circuit in ¶48-56.) and a first transistor connected between an anode electrode of the light emitting device and the sub-pixel circuit and having a gate electrode connected to a second sub-emission control line which is one of the emission control lines, (See Park Fig. 4 and ¶50 where the fifth transistor TR5 may include a gate electrode connected to a second light emission control line and the other electrode connected to a fourth node N4 that is connected to an anode electrode of the organic light emitting diode EL.) and the gate driver supplies: a first voltage to the second sub-emission control line, wherein the first transistor turns off in response to the first voltage; (See Park Figs 4, 5 and ¶63 where in the third period t3, the second light emission control signal EM2 may change to a high level. Accordingly, the connection between the fourth node N4 and the other electrode of the driving transistor TR2 may be interrupted.) (See Park Figs. 4, 5 and ¶59 where in the first period t1, the first light emission control signal EM1 and the second light emission control signal EM2 may also be provided as low-level voltages
Park teaches a control line EM2 that is supplied a high and low voltage, however Park does not explicitly teach wherein a third voltage having a voltage value different from the first voltage and the second voltage to the second sub-emission control line during an emission period in which a driving current is supplied from the sub-pixel to the light emitting device. However, in an analogous field of endeavor Lee teaches a third voltage having a voltage value different from the first voltage and the second voltage to the second sub-emission control line during an emission period in which a driving current is supplied from the sub-pixel to the light emitting device. (See Lee Figs. 4, 7 and ¶94-95 where the magnitude of the driving current may be adjusted in response to voltages of the gate electrodes of the third and fourth transistors T3 and T4 (see FIG. 4), that is, the gate high voltages VEH of the emission signals EM1 and EM2. The second gate high voltage Vadj may be determined in response to the luminance difference between adjacent frames. In addition, the second gate high voltage Vadj may be smaller than the first gate high voltage Vori.) Therefore, it would have been obvious for one of ordinary skill in the art to adjust the voltage of Park by adjusting the voltage of the emission signals as taught by Lee. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of restricting the luminance when the image data changes significantly to reduce the magnitude of the change. (See Lee ¶94)
Claim(s) 3-4, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. in view of Lee as applied to claim 1, in further view of Park et al. (US2022/392382) (hereinafter referred to as Park2)
Consider claim 3, where Park in view of Lee teaches the sub-pixel according to claim 1, further comprising a second transistor connected between the anode electrode of the light emitting device and an initialization voltage node to which an initialization voltage is input, wherein the second transistor comprises a gate electrode connected to the first sub-gate line. (See Park Fig. 4 and ¶55 where the third transistor TR3 may be an initialization transistor. Here, the third transistor TR3 may include a gate electrode connected to the first scan line SL1, one electrode to which an initialization voltage Vint is applied, and the other electrode connected to the fourth node N4. The third transistor may be turned on by the scan signal to initialize the voltages of the first node N1 and the fourth node N4.)
Park teaches connected to the first sub-gate line; however, Park does not explicitly teach connected to a second sub-gate line. However, in an analogous field of endeavor Park2 teaches connected to a second sub-gate line. (See Park2 Fig. 2 and ¶101 where in the eighth duration DR8, the seventh pixel switching element T7 and the eighth pixel switching element T8 are turned on. In addition, the anode electrode of the light emitting element EE is initialized by the initialization voltage VINT through the seventh pixel switching element T7.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the pixel of Park by including a separate control line as taught by Park2. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of separately controlling the timing application of the initialization voltage.
Consider claim 4, where Park in view of Lee in view of Park2 The sub-pixel according to claim 3, further comprising: a third transistor having a first electrode connected to a first node, a second electrode connected to the first transistor, and a gate electrode connected to a second node; (See Park Fig. 4 and ¶50 where the second transistor TR2 may include a gate electrode connected to the first node N1, one electrode connected to a third node N3, and the other electrode connected to one electrode of the fifth transistor TR5.) a fourth transistor connected between the data line and the second node and having a gate electrode connected to the first sub-gate line; (See Park Fig. 4 and ¶49 where the first transistor TR1 may be turned on by the scan signal S1 having a gate-on voltage that is applied to the scan line SL1 to transfer the data voltage D1 that is applied to the data line DL1 to the first node N1.) a fifth transistor connected between the first power voltage node and the first node and having a gate electrode connected to the first sub-emission control line; (See Park Fig. 4 and ¶52 where the fourth transistor TR4 may include a gate electrode connected to a first light emission control line, one electrode connected to the first power voltage ELVDD, and the other electrode connected to the third node N3.) a first capacitor connected between the first node and the second node; (See Park Fig. 4 and ¶54 where the second capacitor C2 may be connected between the first node N1 and the second node N2. When the voltage of the first node N1 is changed from a reference voltage Vref to a data voltage in a data input period, the second capacitor C2 may perform coupling of the voltage of the second node N2.) and a second capacitor connected between the first node and the first power voltage node. (See Park Fig. 4 and ¶53 where the first capacitor C1 may be connected between the first power voltage ELVDD and a second node N2.)
Consider claim 12, where Park in view of Lee teaches the display device according to claim 10, wherein: the sub-pixel further comprises a second transistor connected between the anode electrode of the light emitting device and an initialization voltage node to which an initialization voltage is input, the second transistor comprises a gate electrode connected to the first sub-gate line which is one of the gate lines, (See Park Fig. 4 and ¶55 where the third transistor TR3 may be an initialization transistor. Here, the third transistor TR3 may include a gate electrode connected to the first scan line SL1, one electrode to which an initialization voltage Vint is applied, and the other electrode connected to the fourth node N4. The third transistor may be turned on by the scan signal to initialize the voltages of the first node N1 and the fourth node N4.)and the sub-pixel circuit comprises: a third transistor having a first electrode connected to a first node, a second electrode connected to the first transistor, and a gate electrode connected to a second node; (See Park Fig. 4 and ¶50 where the second transistor TR2 may include a gate electrode connected to the first node N1, one electrode connected to a third node N3, and the other electrode connected to one electrode of the fifth transistor TR5.) a fourth transistor connected between the data line and the second node and having a gate electrode connected to the first sub-gate line; (See Park Fig. 4 and ¶49 where the first transistor TR1 may be turned on by the scan signal S1 having a gate-on voltage that is applied to the scan line SL1 to transfer the data voltage D1 that is applied to the data line DL1 to the first node N1.) a fifth transistor connected between the first power voltage node and the first node and having a gate electrode connected to the first sub-emission control line; (See Park Fig. 4 and ¶52 where the fourth transistor TR4 may include a gate electrode connected to a first light emission control line, one electrode connected to the first power voltage ELVDD, and the other electrode connected to the third node N3.) a first capacitor connected between the first node and the second node; (See Park Fig. 4 and ¶54 where the second capacitor C2 may be connected between the first node N1 and the second node N2. When the voltage of the first node N1 is changed from a reference voltage Vref to a data voltage in a data input period, the second capacitor C2 may perform coupling of the voltage of the second node N2.) and a second capacitor connected between the first node and the first power voltage node. (See Park Fig. 4 and ¶53 where the first capacitor C1 may be connected between the first power voltage ELVDD and a second node N2.)
Park teaches connected to the first sub-gate line; however, Park does not explicitly teach connected to a second sub-gate line. However, in an analogous field of endeavor Park2 teaches connected to a second sub-gate line. (See Park2 Fig. 2 and ¶101 where in the eighth duration DR8, the seventh pixel switching element T7 and the eighth pixel switching element T8 are turned on. In addition, the anode electrode of the light emitting element EE is initialized by the initialization voltage VINT through the seventh pixel switching element T7.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the pixel of Park by including a separate control line as taught by Park2. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of separately controlling the timing application of the initialization voltage.
Allowable Subject Matter
Claims 5-9, 15-17 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 5 recites: “5. The sub-pixel according to claim 4, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor each comprise a body electrode to which the first power voltage is input.” The Examiner’s search found relevant prior art in Tsuboi et al. (US2020/0143741) where Fig. 3 and ¶47 teaches “The Vdd 208 is applied to the back gate of each of the driving transistor 202, the writing transistor 203, and the light emission control transistor 204.” This would map to the claimed the third transistor, the fourth transistor, and the fifth transistor each comprise a body electrode to which the first power voltage is input. However, Tsuboi is silent with regards toa first and second transistor. Thus, the teachings of Tsuboi fall short of the necessary teachings needed to modify Park, Lee, and Park2 to arrive at the claimed invention.
Claim 6 recites: “6. The sub-pixel according to claim 4, wherein: one horizontal period comprises a first period, a second period, and a third period, and the first transistor is turned off during the first period, turned on during the second period and the third period, and turned on based on the third voltage during the emission period after the third period, wherein the first transistor has a predetermined resistance value based on the third voltage during the emission period.” The Examiner was unable to find the timing of the signals as claimed. Thus, claim 6 is allowed. Claims 7-9 are allowed based upon their dependence from claim 6.
Claim 13 recites a similar limitation to claim 6 and is allowed for similar reasons. Claims 14-19 are allowed based upon their dependence from claim 13.
Conclusion
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WILLIAM LU
Primary Examiner
Art Unit 2624
/WILLIAM LU/Primary Examiner, Art Unit 2624
Prosecution Insights