Prosecution Insights
Last updated: October 02, 2026
Application No. 19/370,558

DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING SAME

Non-Final OA §102§103
Filed
Oct 27, 2025
Priority
Nov 04, 2024 — RE 10-2024-0154533
Examiner
BUKOWSKI, KENNETH
Art Unit
2621
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
Est. Remaining
74%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
558 granted / 820 resolved
+6.0% vs TC avg
Moderate +6% lift
Without
With
+6.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
16 currently pending
Career history
845
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
54.2%
+14.2% vs TC avg
§102
22.6%
-17.4% vs TC avg
§112
16.3%
-23.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 820 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 12-14, 18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noh (US 2024.0257793). Regarding claim 1, Noh disclose: The display device comprising: a sub-pixel connected to a data line, a first sub-light emission control line, a first sub-gate line, and a second sub-gate line, and including a light-emitting element; a gate driver configured to supply a first sub-light emission control signal to the first sub-light emitting control line, to supply a first sub-gate signal to the first sub-gate line, and supply a second sub-gate signal to the second sub-gate line; and a data driver configured to supply a data voltage to the data line, wherein a length of a period in which the second sub-gate signal is supplied during a display scan period is different from a length of a period in which the second sub-gate signal is supplied during a self-scan period; and wherein the second sub-gate signal is provided to control a time at which an electrode of the light-emitting element is initialized (see Fig. 1, 2-5; [0046, 0165]; sub pixel PX connected to data line D; first emission control line E; first sub-gate line S2; second sub-gate line S4; light emitting element LD; gate driver 200/300 to supply EM to E, SC2 to S2, SC4 to S4; data driver 400 to supply DATA to D; length of SC4 in display period DP1 is different than length of SC4 in self-scan period DP2; where sC4 to control time in which VAR initialized LD). Regarding claim 2, the rejection of claim 1 is incorporated herein. Noh further disclose: the sub-pixel comprises: a first transistor configured to control driving current, the first transistor coupled between a first node which receives a first power supply voltage and a second node and including a gate electrode coupled to a third node; a second transistor connected between the data line and the third node and including a gate electrode connected to the first sub-gate line; a third transistor connected between the second node and a fourth node, and including a gate electrode connected to the first sub-light emission control line; and a fourth transistor connected between a node configured to provide an initialization voltage and the fourth node, and including a gate electrode connected to the second sub-gate line, wherein the light-emitting element is connected between the fourth node and a node which receives a second power supply voltage (see [0046]; Fig. 3; first TFT T1; first power supply PL1 between first node N1 and third node N2; second TFT T3 between N2 (via T1) and D, with gate connected to S2; third TFT T6 between second node N3 and fourth node N4; fourth TFT T7 to provide VAR to N4 and S4 connected to gate; where LD is between N4 and second power supply PL2). Regarding claim 3, the rejection of claim 2 is incorporated herein. Noh further disclose: the data voltage is written to the sub-pixel during the display scan period, and the data voltage is not written to the sub-pixel during the self-scan period (see [0165]) Regarding claim 4, the rejection of claim 3 is incorporated herein. Noh further disclose: during the display scan period, the gate driver is configured to supply the second sub-gate signal for a first period; and during the self-scan period, the gate driver is configured to supply the second sub-gate signal for a second period (see [0165]; Fig. 4-5; first period NEP1, second period NEP2) Regarding claim 12, Noh disclose: The display device comprising: a sub-pixel connected to a data line, a first sub-light emission control line, a first sub-gate line, and a second sub-gate line and including a light-emitting element; a gate driver configured to supply a first sub-light emission control signal to the first sub-light emitting control line, to supply a first sub-gate signal to the first sub-gate line, and supply a second sub-gate signal to the second sub-gate line; and a data driver configured to supply a data voltage to the data line; wherein a number of times that the second sub-gate signal is supplied during a display scan period is different from a number of times the second sub-gate signal is supplied during the self-scan period; and wherein the second sub-gate signal is provided to control a time at which an electrode of the light-emitting element is initialized (see Fig. 1, 2-5; [0046, 0165]; sub pixel PX connected to data line D; first emission control line E; first sub-gate line S2; second sub-gate line S4; light emitting element LD; gate driver 200/300 to supply EM to E, SC2 to S2, SC4 to S4; data driver 400 to supply DATA to D; SC4 in display period DP1 is supplied a different number of times than SC4 in self-scan period DP2; where sC4 to control time in which VAR initialized LD). Regarding claims 13-14, claims 13-14 are rejected under the same rationale as claims 2-3. Regarding claim 18, the rejection of claim 14 is incorporated herein. Noh further disclose: a number of times the gate driver supplies the second sub-gate signal during the display scan period is greater than a number of times the gate driver supplies the second sub-gate signal during the self-scan period (see Fig. 4-5). Regarding claim 20, claim 20 is rejected under the same rationale s claim 1, where Noh further disclose: a processor; and a display device including pixels (see Fig. 1; display 1000; pixels PX). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 5-11, 15-17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noh. Regarding claim 5, the rejection of claim 4 is incorporated herein. While Noh is not explicit as to a length of the first period is longer than a length of the second period, however, such disclosure is not claimed or described as essential (e.g., Fig. 8 vs. Fig. 9), thus would be an obvious design choice. Furthermore, it would have been obvious to try by one of ordinary skill in the art at the time of applicant’s filing, since there are a finite number of identified, predictable potential solutions (e.g., varying length of the display scan and self-scan periods) to be pursued by one of ordinary skill in the art with a reasonable expectation of success. Regarding claim 6, the rejection of claim 5 is incorporated herein. Noh discloses the claimed invention, except for a length between an end time of a non-emission period including the first period and an end time of the first period is the same as a length between an end time of a non-emission period including the second period and an end time of the second period. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to ensure a length between an end time of a non-emission period including the first period and an end time of the first period is the same as a length between an end time of a non-emission period including the second period and an end time of the second period, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 7, the rejection of claim 6 is incorporated herein. Noh discloses the claimed invention, except for a length between a start time of the non-emission period including the first period and a start time of the first period is shorter than a length between a start time of the non-emission period including the second period and a start time of the second period. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to ensure a length between a start time of the non-emission period including the first period and a start time of the first period is shorter than a length between a start time of the non-emission period including the second period and a start time of the second period, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 8, the rejection of claim 4 is incorporated herein. While Noh is not explicit as to a length of the first period is shorter than a length of the second period, thus would be an obvious design choice. Furthermore, it would have been obvious to try by one of ordinary skill in the art at the time of applicant’s filing, since there are a finite number of identified, predictable potential solutions (e.g., varying length of the display scan and self-scan periods) to be pursued by one of ordinary skill in the art with a reasonable expectation of success. Regarding claim 9, the rejection of claim 8 is incorporated herein. Noh discloses the claimed invention, except for a length between an end time of a non-emission period including the first period and an end time of the first period is the same as a length between an end time of a non-emission period including the second period and an end time of the second period. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to ensure a length between an end time of a non-emission period including the first period and an end time of the first period is the same as a length between an end time of a non-emission period including the second period and an end time of the second period, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 10, the rejection of claim 9 is incorporated herein. Noh discloses the claimed invention, except for a length between a start time of the non-emission period including the first period and a start time of the first period is longer than a length between a start time of the non-emission period including the second period and a start time of the second period. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to ensure a length between a start time of the non-emission period including the first period and a start time of the first period is longer than a length between a start time of the non-emission period including the second period and a start time of the second period, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 11, the rejection of claim 5 is incorporated herein. Noh disclose: the sub-pixel further comprises: a fifth transistor connected between a node configured to receive the first power supply voltage and the first node, and including a gate electrode connected to a second sub-light emission control line; and a sixth transistor connected between a node configured to receive a reference voltage and the third node, and including a gate electrode connected to a third sub-gate line, and wherein the gate driver is configured to supply a second sub-light emission control signal to the second sub-light emitting control line, and to supply a third sub-gate signal to the third sub-gate line (see Fig. 3; fifth TFT T5 connected between PL1 and N1 with gate connected to second emission control E; sixth TFT T4 connected between N2 and reference voltage PL3 with gate connected to third sub-gate S3; where gate driver 200/300 supplies E and S3). Regarding claim 15, the rejection of claim 14 is incorporated herein. While Noh is not explicit as to a number of times the gate driver supplies the second sub-gate signal during the display scan period is less than a number of times the gate driver supplies the second sub-gate signal during the self-scan period, thus would be an obvious design choice. Furthermore, it would have been obvious to try by one of ordinary skill in the art at the time of applicant’s filing, since there are a finite number of identified, predictable potential solutions (e.g., varying number of times the sub-gate signal is supplied during the display scan and self-scan periods) to be pursued by one of ordinary skill in the art with a reasonable expectation of success. Regarding claim 16-17, the rejection of claim 14 is incorporated herein. Noh discloses the claimed invention, except for a number of toggles of the second sub-gate signal during the display scan period is less than a number of toggles of the second sub-gate signal during the self-scan period, wherein a number of toggles is a number of times a logic level of the second sub-gate signal changes. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to ensure a number of toggles of the second sub-gate signal during the display scan period is less than a number of toggles of the second sub-gate signal during the self-scan period, wherein a number of toggles is a number of times a logic level of the second sub-gate signal changes, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Regarding claim 19, the rejection of claim 15 is incorporated herein. Noh disclose: the sub-pixel further comprises: a fifth transistor connected between a node configured to receive the first power supply voltage and the first node, and including a gate electrode connected to a second sub-light emission control line; and a sixth transistor connected between a node configured to receive a reference voltage and the third node, and including a gate electrode connected to a third sub-gate line, wherein the gate driver is configured to supply a second sub-light emission control signal to the second sub-light emitting control line, and is configured to supply a third sub-gate signal to the third sub-gate line (see Fig. 3; fifth TFT T5 connected between PL1 and N1 with gate connected to second emission control E; sixth TFT T4 connected between N2 and reference voltage PL3 with gate connected to third sub-gate S3; where gate driver 200/300 supplies E and S3). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH BUKOWSKI whose telephone number is (571)270-7913. The examiner can normally be reached Monday - Friday // 0730-1530. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571.272.7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /kenneth bukowski/ Primary Examiner, Art Unit 2621
Read full office action

Prosecution Timeline

Oct 27, 2025
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
74%
With Interview (+6.2%)
2y 11m (~1y 11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 820 resolved cases by this examiner. Grant probability derived from career allowance rate.

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