DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in reply to an application filed on October 30, 2025 regarding Application No. 19/374,401. Claims 1-15 are pending.
Priority
The instant application is a continuation of Application No. 18/924,110, filed on October 23, 2024, now Patent No. US 12,536,940, which claims priority to KR 10-2023-0149476, filed on November 1, 2023.
Acknowledgment is made of Applicants’ claim for foreign priority under 35 U.S.C. 119(a)-(d). A certified copy of the KR 10-2023-0149476 application filed in Korea on November 1, 2023 has been filed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 30, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Office. Please note that the Office has included the application number and art unit number on the IDS. It is noted that copies of the foreign patent documents were previously submitted/included in Application No. 18/924,110 on October 23, 2024 and October 2, 2025.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-2 and 7-15 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-2 and 7-15 of Patent No. US 12,536,940. See table below. This is a statutory double patenting rejection.
Instant Application
US 12,536,940
1.
A display device comprising:
a display panel including a plurality of pixels;
a power management circuit which supplies a power supply voltage to the plurality of pixels through a power supply line;
a current sensing circuit which generates a digital current code by sensing a panel current flowing through the power supply line; and
a controller which determines a peak gray level and a panel load by analyzing input image data, determines a voltage level of the power supply voltage based on the peak gray level and the panel load, and sets a conversion time duration, during which the panel current is converted into the digital current code, based on the voltage level of the power supply voltage.
1. An electronic device comprising:
a processor configured to provide input image data; and
a display device configured to receive the input image data from the processor, and to display an image based on the input image data, the display device comprising:
a display panel including a plurality of pixels;
a power management circuit which supplies a power supply voltage to the plurality of pixels through a power supply line;
a current sensing circuit which generates a digital current code by sensing a panel current flowing through the power supply line; and
a controller which determines a peak gray level and a panel load by analyzing the input image data, determines a voltage level of the power supply voltage based on the peak gray level and the panel load, and sets a conversion time duration, during which the panel current is converted into the digital current code, based on the voltage level of the power supply voltage.
2. The display device of claim 1, wherein the controller sets the conversion time duration in a way such that the conversion time duration is decreased as the voltage level of the power supply voltage increases and the conversion time duration is increased as the voltage level of the power supply voltage decreases.
2. The electronic device of claim 1, wherein the controller sets the conversion time duration in a way such that the conversion time duration is decreased as the voltage level of the power supply voltage increases and the conversion time duration is increased as the voltage level of the power supply voltage decreases.
7. The display device of claim 1, wherein the controller includes:
a peak gray level determining circuit which determines the peak gray level by analyzing the input image data;
a panel load determining circuit which determines the panel load by analyzing the input image data;
a power supply voltage determining circuit which determines the voltage level of the power supply voltage based on the peak gray level and the panel load;
a conversion time determining circuit which determines the conversion time duration based on the voltage level of the power supply voltage; and
a power supply voltage control circuit which provides a voltage code corresponding to the voltage level of the power supply voltage to the power management circuit.
7. The electronic device of claim 1, wherein the controller includes:
a peak gray level determining circuit which determines the peak gray level by analyzing the input image data;
a panel load determining circuit which determines the panel load by analyzing the input image data;
a power supply voltage determining circuit which determines the voltage level of the power supply voltage based on the peak gray level and the panel load;
a conversion time determining circuit which determines the conversion time duration based on the voltage level of the power supply voltage; and
a power supply voltage control circuit which provides a voltage code corresponding to the voltage level of the power supply voltage to the power management circuit.
8. The display device of claim 7, wherein the peak gray level determining circuit determines a maximum gray level among a plurality of gray levels represented by the input image data for the plurality of pixels as the peak gray level.
8. The electronic device of claim 7, wherein the peak gray level determining circuit determines a maximum gray level among a plurality of gray levels represented by the input image data for the plurality of pixels as the peak gray level.
9. The display device of claim 7, wherein the panel load determining circuit calculates the panel load by dividing a sum of a plurality of gray levels represented by the input image data for the plurality of pixels by a maximum gray level sum.
9. The electronic device of claim 7, wherein the panel load determining circuit calculates the panel load by dividing a sum of a plurality of gray levels represented by the input image data for the plurality of pixels by a maximum gray level sum.
10. The display device of claim 7, wherein the power supply voltage determining circuit increases the voltage level of the power supply voltage as the peak gray level increases, and increases the voltage level of the power supply voltage as the panel load increases.
10. The electronic device of claim 7, wherein the power supply voltage determining circuit increases the voltage level of the power supply voltage as the peak gray level increases, and increases the voltage level of the power supply voltage as the panel load increases.
11. The display device of claim 7, wherein the conversion time determining circuit decreases the conversion time duration as the voltage level of the power supply voltage increases, and increases the conversion time duration as the voltage level of the power supply voltage decreases.
11. The electronic device of claim 7, wherein the conversion time determining circuit decreases the conversion time duration as the voltage level of the power supply voltage increases, and increases the conversion time duration as the voltage level of the power supply voltage decreases.
12. The display device of claim 7, wherein the controller further includes:
a power supply voltage-conversion time lookup table which stores the conversion time duration corresponding to the voltage level of the power supply voltage, and
wherein the conversion time determining circuit determines the conversion time duration corresponding to the voltage level of the power supply voltage using the power supply voltage-conversion time lookup table.
12. The electronic device of claim 7, wherein the controller further includes:
a power supply voltage-conversion time lookup table which stores the conversion time duration corresponding to the voltage level of the power supply voltage, and
wherein the conversion time determining circuit determines the conversion time duration corresponding to the voltage level of the power supply voltage using the power supply voltage-conversion time lookup table.
13. The display device of claim 7, wherein the power supply voltage control circuit decreases the voltage code provided to the power management circuit to decrease the voltage level of the power supply voltage in response to an alert signal from a rush current detection circuit.
13. The electronic device of claim 7, wherein the power supply voltage control circuit decreases the voltage code provided to the power management circuit to decrease the voltage level of the power supply voltage in response to an alert signal from a rush current detection circuit.
14. The display device of claim 1, wherein the controller includes:
a global current management circuit which receives the digital current code from the current sensing circuit, determines a target current code corresponding to the panel load, and controls the panel current by comparing the digital current code and the target current code.
14. The electronic device of claim 1, wherein the controller includes:
a global current management circuit which receives the digital current code from the current sensing circuit, determines a target current code corresponding to the panel load, and controls the panel current by comparing the digital current code and the target current code.
15. The display device of claim 1, wherein the controller includes:
an overcurrent protection circuit which receives the digital current code from the current sensing circuit, compares the digital current code with a reference overcurrent code, and controls the power management circuit to stop supplying the power supply voltage when the digital current code is higher than the reference overcurrent code.
15. The electronic device of claim 1, wherein the controller includes:
an overcurrent protection circuit which receives the digital current code from the current sensing circuit, compares the digital current code with a reference overcurrent code, and controls the power management circuit to stop supplying the power supply voltage when the digital current code is higher than the reference overcurrent code.
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/ guidance/eTD-info-I.jsp.
Claims 3-6 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 3-6 of Patent No. US 12,536,940 in view of Oh et al. in US 2014/0084792 A1 (hereinafter Oh).
Note: it appears that “The electronic display device of claim 1...” (emphasis added) is inadvertently recited in claim 3 of US 12,536,940 instead of “The electronic device of claim 1...” (see Application No. 18/924,110: October 2, 2025 Notice of Allowance at p. 3).
Regarding claim 3, U.S. Patent No. US 12,536,940 teaches:
The electronic display device of claim 1, further comprising (claim 3 of US 12,536,940, see also Note above and table below):
a rush current detection circuit which generates an alert signal by comparing the digital current code with a rush current code corresponding to a rush reference current (claim 3 of US 12,536,940, see also table below).
However, it is noted that US 12,536,940 does not teach:
The display device of claim 1, further comprising:.
Oh teaches:
A display device (see Fig. 1), comprising (Oh: Fig. 1 and “[0050] As shown in FIG[]. 1..., an organic light emitting display device comprises... a power controller 180.”):
a rush current detection circuit (180 in Figs. 1 and 3) which generates an alert signal (SDS) by comparing a digital current code with a rush current code corresponding to a rush reference current (Oh: Figs. 1 and 3, “[0059]... The current detection unit 170 detects a current flowing into the panel 160 through the first power line wiring VDD and provides the detected current to the power controller 180....”, “[0060] The power controller 180 generates a shutdown signal SDS according to a current detected by the current detection unit 170. The power controller 180 outputs the shutdown signal SDS when the detected current reaches an overcurrent, thereby turning off the power supply 125. In other words, the whole output of the power supply 125 is shut down.”, “[0061] The current detection unit 170 and the power controller 180 described earlier comprise a short detection circuit which detects occurrence of short circuit at the power supply and in the event of short circuit, turns off the power supply 125. Various factors cause short circuit at power terminals, which include... external factors such as static electricity.”, “[0062] If an excessive current flows into a sub-pixel due to short circuit at power terminals, elements of the corresponding sub-pixel are burnt out.... To prevent the above problem, the short detection circuit controls the power supply 125 in such a way to remove the possibility of generating a fire at the panel 160....”, “[0068] The power controller 180 receives a detected current from the current detection unit 170 and compares the detected current with an internally set current value. If the detected current exceeds the specified current value, a shutdown signal SDS is output and turns off the power supply 125.”, and “[0117]... [T]he power controller described in FIGS. 3, 4, 5, 9, 10, and 14 of the present invention can be incorporated into the timing controller. In this case, the current detection unit further incorporates an analog-to-digital converter which converts a detected analog current value to a digital current value. Accordingly, the power controller included in the timing controller according to the first embodiment can determine based on the digital current value obtained from the analog-to-digital converter whether a detected current value gets out of a range set internally. Meanwhile, the power controller included in the timing controller according to the second embodiment can determine based on the digital current value obtained from the analog-to-digital converter whether a detected current value from a particular block is higher or lower than the current values of the other blocks.”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Oh, such that US 12,536,940 as modified teaches: The display device of claim 1, further comprising: a rush current detection circuit which generates an alert signal by comparing the digital current code with a rush current code corresponding to a rush reference current (electronic device, display device, and rush current detection circuit of US 12,536,940 combined with the display device and rush current detection circuit of Oh), to provide a rush current detection circuit of a display device.
Regarding claims 4-6, these claims are respectively rejected by claims 4-6 of US 12,536,940 in view of Oh. See also table below.
Instant Application
US 12,536,940
3. The display device of claim 1, further comprising:
a rush current detection circuit which generates an alert signal by comparing the digital current code with a rush current code corresponding to a rush reference current.
3. The electronic display device of claim 1, further comprising:
a rush current detection circuit which generates an alert signal by comparing the digital current code with a rush current code corresponding to a rush reference current.
4. The display device of claim 3, wherein the controller controls the power management circuit to decrease the voltage level of the power supply voltage in response to the alert signal.
4. The electronic device of claim 3, wherein the controller controls the power management circuit to decrease the voltage level of the power supply voltage in response to the alert signal.
5. The display device of claim 3, wherein the controller is implemented as a controller integrated circuit, and
wherein the current sensing circuit and the rush current detection circuit are included in a current sensing integrated circuit which is separated from the controller integrated circuit.
5. The electronic device of claim 3, wherein the controller is implemented as a controller integrated circuit, and
wherein the current sensing circuit and the rush current detection circuit are included in a current sensing integrated circuit which is separated from the controller integrated circuit.
6. The display device of claim 5, wherein the current sensing integrated circuit includes a conversion time setting register which sets the conversion time duration, and
wherein the controller sets the conversion time duration by changing a value of the conversion time setting register through inter-integrated circuit communication between the controller integrated circuit and the current sensing integrated circuit.
6. The electronic device of claim 5, wherein the current sensing integrated circuit includes a conversion time setting register which sets the conversion time duration, and
wherein the controller sets the conversion time duration by changing a value of the conversion time setting register through inter-integrated circuit communication between the controller integrated circuit and the current sensing integrated circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to K. Kiyabu whose telephone number is (571) 270-7836. The examiner can normally be reached Monday to Thursday 9:00 A.M. - 5:00 P.M. ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached at (571) 272-3017. The fax number for the organization where this application or proceeding is assigned is (571) 273-8300.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicants are encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patents/uspto-automated-interview-request-air-form.
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/K. K./
Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 6/8/26
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