CTNF 19/378,906 CTNF 88158 DETAILED ACTION Status of Application Claims 2-8 are pending in the instant application. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 2-3, 5-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (US 20170125122 A1), further in view of Park et al. (US 20190148477 A1) . Regarding claim 2, Miyake teaches a semiconductor device comprising: a first transistor, a second transistor, and a third transistor, (Fig. 4B: transistors 126, 128, 136) wherein the first transistor, the second transistor, and the third transistor each comprise a first gate and a second gate, (Fig. 4B: transistors 126, 128, 136 with first gate and second gate) wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, (Fig. 4B: one of a source and a drain of 126 is electrically connected to one of a source and a drain of 128) wherein the first gate of the first transistor is electrically connected to the second gate of the first transistor, (Fig. 4B: wherein the first gate of the first transistor 126 is electrically connected to the second gate of the first transistor 126) wherein the first gate of the second transistor is electrically connected to one of a source and a drain of the third transistor, (Fig. 4B: first gate of 126 is electrically connected to one of a source and a drain of the third transistor 136 through transistor 132 and 125 when 132 and 125 are on) wherein the second gate of the second transistor is electrically connected to a first wiring, (Fig. 4B: the second gate of the second transistor 128 is electrically connected to a first wiring 145 through 132 and 125) wherein the first gate of the third transistor is electrically connected to the first gate of the first transistor, (Fig. 4B: the first gate of the third transistor 136 is electrically connected to the first gate of the first transistor126 through 132 and 125) wherein the second gate of the third transistor is electrically connected to a second wiring, (Fig. 4B: the second gate of the third transistor is electrically connected to a second wiring 117) wherein the semiconductor device further comprises a conductive layer, (Para 174) However Miyake does not teach and wherein the conductive layer comprises a region which functions as the first gate of the first transistor and a region which functions as the first gate of the third transistor. However Park teaches wherein the conductive layer comprises a region which functions as the first gate of the first transistor and a region which functions as the first gate of the third transistor. (Para 100) Therefore it would have been obvious to one with ordinary skill, before the effective filing date of the invention, to modify Miyake with Park to teach wherein the conductive layer comprises a region which functions as the first gate of the first transistor and a region which functions as the first gate of the third transistor in order to produce the predictable result of display driver manufactured to drive the display with gates of different transistors sharing conductive layer. Regarding claim 3, Miyake and Park already teach the semiconductor device according to claim 2, And Miyake further teaches further comprising a capacitor, wherein a first terminal of the capacitor is electrically connected to the first gate of the second transistor. (Fig. 4B: 134 connected to first gate of 128) Regarding claim 5, Miyake teaches a semiconductor device comprising: a gate driver circuit comprises a first circuit and a second circuit, (Para 318, 356. Fig. 4B: first circuit with transistors 126, 128, 136. Second circuit-output 116and transistor 129. Para 127) wherein the first circuit comprises a first transistor, a second transistor, and a third transistor, (Fig. 4B: transistors 126, 128, 136) wherein the first transistor, the second transistor, and the third transistor each comprise a first gate and a second gate, (Fig. 4B: transistors 126, 128, 136 with first gate and second gate) wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, (Fig. 4B: one of a source and a drain of 126 is electrically connected to one of a source and a drain of 128) wherein the first gate of the first transistor is electrically connected to the second gate of the first transistor, (Fig. 4B: wherein the first gate of the first transistor 126 is electrically connected to the second gate of the first transistor 126) wherein the first gate of the second transistor is electrically connected to one of a source and a drain of the third transistor, (Fig. 4B: first gate of 126 is electrically connected to one of a source and a drain of the third transistor 136 through transistor 132 and 125 when 132 and 125 are on) wherein the second gate of the second transistor is electrically connected to a first wiring, (Fig. 4B: the second gate of the second transistor 128 is electrically connected to a first wiring 145 through 132 and 125) wherein the first gate of the third transistor is electrically connected to the first gate of the first transistor, (Fig. 4B: the first gate of the third transistor 136 is electrically connected to the first gate of the first transistor126 through 132 and 125) wherein the second gate of the third transistor is electrically connected to a second wiring, (Fig. 4B: the second gate of the third transistor is electrically connected to a second wiring 117) wherein an output terminal of the second circuit is electrically connected to the first gate of the first transistor, (fig. 4B; output 116 is connected to the first gate of the first transistor 126 through transistor 128) wherein the semiconductor device further comprises a conductive layer, (Para 174) However Miyake does not teach and wherein the conductive layer comprises a region which functions as the first gate of the first transistor and a region which functions as the first gate of the third transistor. However Park teaches wherein the conductive layer comprises a region which functions as the first gate of the first transistor and a region which functions as the first gate of the third transistor. (Para 100) Therefore it would have been obvious to one with ordinary skill, before the effective filing date of the invention, to modify Miyake with Park to teach wherein the conductive layer comprises a region which functions as the first gate of the first transistor and a region which functions as the first gate of the third transistor in order to produce the predictable result of display driver manufactured to drive the display with gates of different transistors sharing conductive layer Regarding claim 6, Miyake and Park already teach the semiconductor device according to claim 5, And Miyake further teaches further comprising a capacitor, wherein a first terminal of the capacitor is electrically connected to the first gate of the second transistor. (Fig. 4B: 134 connected to first gate of 128) Regarding claim 8, Miyake teaches a semiconductor device comprising: a first transistor, a second transistor, and a third transistor, (Fig. 4B: transistors 126, 128, 136) wherein the first transistor, the second transistor, and the third transistor each comprise a first gate and a second gate, (Fig. 4B: transistors 126, 128, 136 with first gate and second gate) wherein the first gate of the first transistor is electrically connected to the second gate of the first transistor, (Fig. 4B: wherein the first gate of the first transistor 126 is electrically connected to the second gate of the first transistor 126) wherein the second gate of the second transistor is electrically connected to a first wiring, (Fig. 4B: the second gate of the second transistor 128 is electrically connected to a first wiring 145 through 132 and 125) wherein the second gate of the third transistor is electrically connected to a second wiring, (Fig. 4B: the second gate of the third transistor 136 is electrically connected to a second wiring 117) wherein the semiconductor device further comprises a conductive layer, (Para 174) However Miyake and Park do not teach and wherein the conductive layer comprises a region which functions as the first gate of the first transistor and a region which functions as the first gate of the third transistor. However Park teaches wherein the conductive layer comprises a region which functions as the first gate of the first transistor and a region which functions as the first gate of the third transistor. (Para 100) Therefore it would have been obvious to one with ordinary skill, before the effective filing date of the invention, to modify Miyake with Park to teach wherein the conductive layer comprises a region which functions as the first gate of the first transistor and a region which functions as the first gate of the third transistor in order to produce the predictable result of display driver manufactured to drive the display with gates of different transistors sharing conductive layer . 07-21-aia AIA Claim s 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (US 20170125122 A1), in view of Park et al. (US 20190148477 A1), further in view of Xu et al. (US 20190250451 A1) . Regarding claim 4, Miyake and Park already teach the semiconductor device according to claim 3, However Miyake and Park do not teach wherein the conductive layer comprises a region which functions as the first terminal of the capacitor. However Xu teaches wherein the conductive layer comprises a region which functions as the first terminal of the capacitor. (Para 67: the common electrode line, the first terminal of the first capacitor C 1 , the bottom gate G 1 of the switch transistor, and the gate G 3 of the shared transistor are formed in the first conductive layer M 1 ) Therefore it would have been obvious to one with ordinary skill, before the effective filing date of the invention, to modify Miyake and Park with Xu to teach wherein the conductive layer comprises a region which functions as the first terminal of the capacitor in order to produce the predictable result of display driver manufactured to drive the display with capacitor terminal and gate of transistors sharing conductive layer. Regarding claim 7, refer to rejection for claim 4. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HANG LIN whose telephone number is (571)270-7596. The examiner can normally be reached Monday-Friday, 8am-5pm. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HANG LIN/ Primary Examiner, Art Unit 2626 Application/Control Number: 19/378,906 Page 2 Art Unit: 2626 Application/Control Number: 19/378,906 Page 3 Art Unit: 2626 Application/Control Number: 19/378,906 Page 4 Art Unit: 2626 Application/Control Number: 19/378,906 Page 5 Art Unit: 2626 Application/Control Number: 19/378,906 Page 6 Art Unit: 2626 Application/Control Number: 19/378,906 Page 7 Art Unit: 2626 Application/Control Number: 19/378,906 Page 8 Art Unit: 2626 Application/Control Number: 19/378,906 Page 9 Art Unit: 2626 Application/Control Number: 19/378,906 Page 10 Art Unit: 2626
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