DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 6, 9, and 11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al (US Pub. 20240371312) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding Claim 1, Kim discloses:
An electronic device, (at least refer to fig. 1 and paragraph 60. Describes a portable terminal) comprising:
A display panel, (at least refer to fig. 1 and paragraph 60. Describes a display device DD); and
A processor configured to control the display panel, (at least refer to fig. 1 and paragraph 99. Describes the timing controller 100C1 may provide the data driving circuit 100C4 with a driving signal DS that is obtained by processing the image data RGB so as to be appropriate for an operation condition of the display panel DP) wherein the display panel comprises:
A plurality of pixels connected to a plurality of data lines and a plurality of scan lines, (at least refer to fig. 4 and paragraph 93. Describes the display panel DP may include a plurality of scan lines SL1 to SLn, a plurality of emission control lines EL1 to ELn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX) respectively;
A plurality of scan stages connected to the plurality of scan lines, (at least refer to fig. 5-6 and paragraph 107. Describes each of the plurality of scan stages ST1 to ST4 may receive the first clock signal CLK1, the second clock signal CLK2, and a carry signal CRY, and the plurality of scan stages ST1 to ST4 may respectively output scan signals SS1, SS2, SS3, and SS4) respectively; and
A plurality of clock lines connected to the plurality of scan stages, (at least refer to fig. 5-6 and paragraph 107. Describes each of the plurality of scan stages ST1 to ST4 may receive the first clock signal CLK1, the second clock signal CLK2) respectively,
Wherein the plurality of pixels are configured to receive a corresponding data voltage, in response to a corresponding scan signal, (at least refer to fig. 4 and paragraph 154. Describes when a predetermined scan line is driven by the scan driving circuit 100C2, the data driving circuit 100C4 may output grayscale voltages to the plurality of data lines DL1 to DLm)
Wherein a first scan stage of the plurality of scan stages is configured to receive a logic clock signal, a clock signal, and a carry signal, and output a scan signal, (at least refer to fig. 15 and paragraphs 245, 248. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2. The plurality of scan stages ST1-2 to ST6-2 may respectively output scan signals SS1-2, SS2-2, SS3-2, SS4-2, SS5-2, and SS6-2. Para. 248, describes: The first scan stage ST1-2 among the plurality of scan stages ST1-2 to ST6-2 may receive the start signal FLM as the carry signal CRY)
Wherein the plurality of clock lines comprise a logic clock line configured to provide the logic clock signal and a scan clock line configured to provide the clock signal, (at least refer to fig. 15 and paragraph 245. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2.)
Wherein the scan clock line is adjacent the plurality of scan stages along a first direction, when viewed in a plan view, (at least refer to fig. 5, 15 and paragraph 245. Describes first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first clock signal CLK1-2 and a second clock signal CLK2-2 lines extends in the second direction DR2)
Wherein the plurality of clock lines extend in a second direction crossing the first direction, and wherein the logic clock line is spaced apart from the scan clock line along the first direction, when viewed in the plan view, (at least refer to fig. 15 and paragraph 245. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first logic clock signal INT1 and a second logic clock signal INT2 lines spaced apart from the first clock signal CLK1-2 and a second clock signal CLK2-2 lines all extending in the second direction DR2 intersecting the first direction lines of the scan signal).
Regarding Claim 2, Kim discloses:
Wherein the scan clock line is offset from the plurality of scan stages, when viewed in the plan view, (at least refer to fig. 5, 15 and paragraph 245. Describes first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first clock signal CLK1-2 and a second clock signal CLK2-2 lines extends in the second direction DR2).
Regarding Claim 6, Kim discloses:
Wherein the first scan stage is further configured to output the clock signal as the scan signal, in response to the carry signal, (at least refer to fig. 15 and paragraph 290. Describes When the start signal FLM of the high-level voltage VGH is provided to the first scan stage ST1-2, the first scan stage ST1a may output the first scan signal SS1-2 after a delay corresponding to one horizontal period. In this case, the start signal FLM may be output from the timing controller 100C1 and may be provided to the first scan stage ST1-2 as the carry signal CRY).
Regarding Claim 9, Kim discloses:
Wherein the clock signal comprises a first clock signal and a second clock signal different from the first clock signal, and wherein the scan clock line comprises: a first scan clock line configured to provide the first clock signal; and a second scan clock line configured to provide the second clock signal, (at least refer to fig. 5, 7 and paragraphs 135, 245. Describes the phase of the second clock signal CLK2 may be opposite to the phase of the first clock signal CLK1. Para. 245, describes: first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first clock signal CLK1-2 and a second clock signal CLK2-2 lines extends in the second direction DR2).
Regarding Claim 11, Kim discloses:
Wherein the second clock signal has a waveform shifted by a specific period from the first clock signal, (at least refer to fig. 5 and paragraphs 112. Describes a phase shift may be made in order of the first clock signal CLK1 and the second clock signal CLK2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-5, 8, 10, and 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US Pub. 20240371312).
Regarding Claim 12, Kim discloses:
An electronic device, (at least refer to fig. 1 and paragraph 60. Describes a portable terminal) comprising:
A plurality of scan stages, wherein a first scan stage of the plurality of scan stages is configured to receive a logic clock signal, a clock signal, and a carry signal, and output a scan signal, (at least refer to fig. 15 and paragraphs 245, 248. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2. The plurality of scan stages ST1-2 to ST6-2 may respectively output scan signals SS1-2, SS2-2, SS3-2, SS4-2, SS5-2, and SS6-2. Para. 248, describes: The first scan stage ST1-2 among the plurality of scan stages ST1-2 to ST6-2 may receive the start signal FLM as the carry signal CRY); and
A plurality of clock lines connected to the plurality of scan stages, respectively, wherein the plurality of clock lines comprise a logic clock line configured to provide the logic clock signal to the first scan stage and a scan clock line configured to provide the clock signal to the first scan stage, (at least refer to fig. 15 and paragraph 245. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2.) and
Wherein when viewed in a plan view, the logic clock line, the plurality of scan stages, and the scan clock line is offset from the plurality of scan stages, (at least refer to fig. 15 and paragraph 245. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first logic clock signal INT1 and a second logic clock signal INT2 lines spaced apart from the first clock signal CLK1-2 and a second clock signal CLK2-2 lines all extending in the second direction DR2 intersecting the first direction lines of the scan signal).
Kim does not disclose:
the logic clock line overlaps the plurality of scan stages
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987
Regarding Claim 3, Kim discloses:
Wherein the logic clock line with the plurality of scan stages, when viewed in the plan view, (at least refer to fig. 15 and paragraph 245. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first logic clock signal INT1 and a second logic clock signal INT2 lines spaced apart from the first clock signal CLK1-2 and a second clock signal CLK2-2 lines all extending in the second direction DR2 intersecting the first direction lines of the scan signal).
Kim does not disclose:
the logic clock line overlaps the plurality of scan stages
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987)
Regarding Claim 4, Kim discloses:
Wherein the logic clock line is with the plurality of scan stages, (at least refer to fig. 15 and paragraph 245. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first logic clock signal INT1 and a second logic clock signal INT2 lines spaced apart from the first clock signal CLK1-2 and a second clock signal CLK2-2 lines all extending in the second direction DR2 intersecting the first direction lines of the scan signal).
Kim does not disclose:
the logic clock line is on the plurality of scan stages
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987)
Regarding Claim 5, Kim discloses:
Wherein the logic clock signal has a square waveform which oscillates between a turn-on voltage level and a turn-off voltage level at a specific cycle, (at least refer to fig. 17 and paragraph 289. Describes in each of the first logic clock signal INT1 and the second logic clock signal INT2, the first voltage and the second voltage may be repeated at the given period. The first logic clock signal INT1 may be a signal obtained by shifting the first clock signal CLK1-2 as much as a given interval (or phase)).
Kim does not explicitly disclose:
square waveform
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987)
Regarding Claim 8, Kim discloses:
Wherein the logic clock line is spaced apart from the plurality of scan stages in the first direction, (at least refer to fig. 15 and paragraph 245. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first logic clock signal INT1 and a second logic clock signal INT2 lines spaced apart from the first clock signal CLK1-2 and a second clock signal CLK2-2 lines all extending in the second direction DR2 intersecting the first direction lines of the scan signal)
Kim does not disclose:
the scan clock line is between the logic clock line and the plurality of scan stages, when viewed in the plan view.
It would have been an obvious matter of design choice to have the scan clock line between the logic clock line and the plurality of scan stages since the applicant has not disclosed that the scan clock line is between the logic clock line and the plurality of scan stages solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the logic clock line between the scan clock line and the plurality of scan stages.
Regarding Claim 10, Kim discloses:
Wherein the second scan clock line is spaced apart from the plurality of scan stages, (at least refer to fig. 15 and paragraph 245. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first logic clock signal INT1 and a second logic clock signal INT2 lines spaced apart from the first clock signal CLK1-2 and a second clock signal CLK2-2 lines all extending in the second direction DR2 intersecting the first direction lines of the scan signal)
Kim does not disclose:
the first scan clock line is between the second scan clock line and the plurality of scan stages.
It would have been an obvious matter of design choice to have the first scan clock line between the second scan clock line and the plurality of scan stages since the applicant has not disclosed that the first scan clock line between the second scan clock line and the plurality of scan stages solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the second scan clock line between the first scan clock line and the plurality of scan stages.
Regarding Claim 13, Kim discloses:
Wherein the logic clock line is with the plurality of scan stages, (at least refer to fig. 15 and paragraph 245. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first logic clock signal INT1 and a second logic clock signal INT2 lines spaced apart from the first clock signal CLK1-2 and a second clock signal CLK2-2 lines all extending in the second direction DR2 intersecting the first direction lines of the scan signal).
Kim does not disclose:
the logic clock line is on the plurality of scan stages
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987)
Regarding Claim 14, Kim discloses:
Wherein the logic clock signal has a square waveform which oscillates between a turn-on voltage level and a turn-off voltage level at a specific cycle, (at least refer to fig. 17 and paragraph 289. Describes in each of the first logic clock signal INT1 and the second logic clock signal INT2, the first voltage and the second voltage may be repeated at the given period. The first logic clock signal INT1 may be a signal obtained by shifting the first clock signal CLK1-2 as much as a given interval (or phase)).
Kim does not explicitly disclose:
square waveform
It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987)
Regarding Claim 15, Kim discloses:
Wherein the first scan stage is further configured to output the clock signal as the scan signal, in response to the carry signal, (at least refer to fig. 15 and paragraph 290. Describes When the start signal FLM of the high-level voltage VGH is provided to the first scan stage ST1-2, the first scan stage ST1a may output the first scan signal SS1-2 after a delay corresponding to one horizontal period. In this case, the start signal FLM may be output from the timing controller 100C1 and may be provided to the first scan stage ST1-2 as the carry signal CRY).
Regarding Claim 17, Kim discloses:
Wherein the clock signal comprises a first clock signal and a second clock signal different from the first clock signal, (at least refer to fig. 5, 7 and paragraphs 135. Describes The phase of the second clock signal CLK2 may be opposite to the phase of the first clock signal CLK1).
Regarding Claim 18, Kim discloses:
Wherein the scan clock line comprises: a first scan clock line configured to provide the first clock signal; and a second scan clock line configured to provide the second clock signal, (at least refer to fig. 5, 7 and paragraph 245. Describes first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first clock signal CLK1-2 and a second clock signal CLK2-2 lines extends in the second direction DR2).
Regarding Claim 19, Kim discloses:
Wherein the second scan clock line is spaced apart from the plurality of scan stages, (at least refer to fig. 15 and paragraph 245. Describes each of the plurality of scan stages ST1-2 to ST6-2 may receive a first logic clock signal INT1, a second logic clock signal INT2, and one of a first clock signal CLK1-2 and a second clock signal CLK2-2. Depicts the first logic clock signal INT1 and a second logic clock signal INT2 lines spaced apart from the first clock signal CLK1-2 and a second clock signal CLK2-2 lines all extending in the second direction DR2 intersecting the first direction lines of the scan signal)
Kim does not disclose:
the first scan clock line is between the second scan clock line and the plurality of scan stages.
It would have been an obvious matter of design choice to have the first scan clock line between the second scan clock line and the plurality of scan stages since the applicant has not disclosed that the first scan clock line between the second scan clock line and the plurality of scan stages solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well with the second scan clock line between the first scan clock line and the plurality of scan stages.
Regarding Claim 20, Kim discloses:
Wherein the second clock signal has a waveform shifted by a specific period from the first clock signal, (at least refer to fig. 5 and paragraphs 112. Describes a phase shift may be made in order of the first clock signal CLK1 and the second clock signal CLK2).
Allowable Subject Matter
Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/IFEDAYO B ILUYOMADE/Primary Examiner, Art Unit 2624 08/06/2026
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