Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the application filed 11/5/2025 in which Claims 1-17 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-17 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 12,495,688. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are broader than the patent claims.
Claim 1 of the instant application
Claim 1 of U.S. Patent 12,495,688
1. A display device comprising: a first transistor including a first semiconductor layer; a second transistor including a second semiconductor layer and electrically connected to the first transistor;
1. A display device comprising: a first transistor including a first semiconductor layer; a second transistor including a second semiconductor layer and electrically connected to the first transistor;
a first insulating layer disposed on the first semiconductor layer and the second semiconductor layer; a first gate line disposed on the first insulating layer; a second insulating layer disposed on the first gate line;
a first insulating layer disposed on the first semiconductor layer and the second semiconductor layer; a first gate line disposed on the first insulating layer; a second insulating layer disposed on the first gate line;
a second gate line disposed on the second insulating layer; a third insulating layer disposed on the second gate line;
a second gate line disposed on the second insulating layer; a third insulating layer disposed on the second gate line;
a third transistor including a third semiconductor layer disposed on the third insulating layer and electrically connected to the first transistor;
a third transistor including a third semiconductor layer disposed on the third insulating layer and electrically connected to the first transistor;
a fourth insulating layer disposed on the third semiconductor layer;
a fourth insulating layer disposed on the third semiconductor layer;
an initializing voltage line carrying an initializing control signal disposed on the fourth insulating layer;
a fifth insulating layer disposed on the initializing voltage line; a data line carrying a data signal disposed on the fifth insulating layer; a driving voltage line carrying a driving voltage disposed on the fifth insulating layer;
a shielding electrode electrically connected to the initializing voltage line and overlapping at least a portion of a channel of the third semiconductor layer,
the shielding electrode and at least one of the data line and the driving voltage line being disposed on a same layer;
and a light emitting diode electrically connected to the first transistor.
and a light emitting diode electrically connected to the first transistor.
Conclusion
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached on (571) 272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EBONI N GILES/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
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