DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5-6, 9, 12, 14-15, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Kim; Hyun Joon, US 20220130337 A1] in view of [Park; Kyung Ho, US 20210090491 A1].
Regarding claim 1:
Kim discloses:
1. A scan driving circuit (300) [Kim: Fig.11: scan driver 330; ¶ 0092: “each of the multiple stages 331, 332, 333, 334, . . . may have a similar configuration to a configuration of a stage 100 of FIG. 1, a configuration of a stage 200 of FIG. 10, or the like”; Examiner: The recited logic circuit and first and second buffers are those of a single stage of scan driver 330, configured as stage 200 of Fig.10.], comprising:
a logic circuit (331) [Kim: Fig.10: logic circuit 210] configured to output a first logic signal (LS11) [Kim: Fig.10: second node NQB] and a second logic signal (LS21) [Kim: Fig.10: first node NQ], in response to a start signal (SS1) [Kim: ¶ 0052: “may receive, as an input signal SIN, a scan start signal FLM”] and a plurality of logic clock signals [Kim: ¶ 0055: “a first transistor T1 including a gate receiving the first clock signal CLK1”; ¶ 0080: “the stabilizer part 280 of the logic circuit 210 may receive a fourth clock signal CLK4 instead of a second clock signal CLK2”; Examiner: In the Fig.10, embodiment the logic circuit 210 receives two clock signals, CLK1 at the input part 140 and CLK4 at the stabilizer part 280.];
a first buffer (332) [Kim: Fig.10: first output buffer 120] configured to output a first scan signal [Kim: Fig.10: active-low scan signal PSS at first output node NO_PSS], in response to a first clock signal [Kim: ¶ 0060: “a second terminal receiving the second clock signal CLK2”], the first logic signal (LS11) [Kim: Fig.10: second node NQB] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0060: “a ninth transistor T9 including a gate electrically connected to the second node NQB”], and the second logic signal (LS21) [Kim: Fig.10: first node NQ] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0060: “an eighth transistor T8 including a gate electrically connected to the first node NQ”];
and a second buffer (333) [Kim: Fig.10: second output buffer 130] configured to output a second scan signal [Kim: Fig.10: active-high scan signal NSS at second output node NO_NSS], in response to a second clock signal [Kim: ¶ 0061: “a second terminal receiving the third clock signal CLK3”], the first logic signal (LS11) [Kim: Fig.10: second node NQB] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0061: “an eleventh transistor T11 including a gate electrically connected to the second node NQB”], and the second logic signal (LS21) [Kim: Fig.10: first node NQ] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0061: “a tenth transistor T10 including a gate electrically connected to the first node NQ”],
wherein the logic circuit (331) [Kim: Fig.10: logic circuit 210] is commonly connected to the first buffer (332) [Kim: Fig.10: first output buffer 120; ¶ 0063: “the first output buffer 120 that may output the active-low scan signal PSS based on the voltages of the first and second nodes NQ and NQB”] and the second buffer (333) [Kim: Fig.10: second output buffer 130; ¶ 0063: “the second output buffer 130 that may output the active-high scan signal NSS based on the voltages of the first and second nodes NQ and NQB”].
However, Kim does not expressly disclose:
wherein each of the first clock signal and the second clock signal has an amplitude smaller than an amplitude of each of the logic clock signals.
Park discloses:
wherein each of the first clock signal [Park: ¶ 0074: “a second electrode of the first transistor T1 may be connected to a scan clock line SCCK5, and a gate electrode of the first transistor T1 may be connected to a third node N3”; ¶ 0177: “ The first transistor T1 and the fourth transistor T4 may be scan buffer transistors”] and the second clock signal [Park: ¶ 0075: “a second electrode of the second transistor T2 may be connected to a sensing clock line SSCK5, and a gate electrode of the second transistor T2 may be connected to the third node N3”; ¶ 0177: “ The first transistor T1 and the fourth transistor T4 may be scan buffer transistors”] has an amplitude smaller than an amplitude of each of the logic clock signals [Park: Fig.5: SCCK1-SCCK6 and SSCK1-SSCK6 shown swinging between VON and VSS1; CRCK1-CRCK6 shown swinging between VON and VSS2 and VSS3; ¶ 0137: “ a low level of the scan clock signals and the sensing clock signals may correspond to the magnitude of a voltage applied to the first power line VSS1, and a high level of the scan clock signals and the sensing clock signals may correspond to the magnitude of a gate-on voltage VON”; ¶ 0137: “the voltage applied to the first power line VSS1 may be higher than that applied to the second power line VSS2 or the third power line VSS3”; Examiner: All three clock groups share the same high level VON, and the low level of the scan and sensing clocks is higher than that of the carry clocks, so the peak-to-peak amplitude of each of the scan and sensing clocks is smaller than that of the carry clocks.].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to supply Kim’s second and third clock signals, which drive the first and second output buffers, at a smaller voltage swing than Kim’s first and fourth clock signals, which drive the logic circuit, as taught by Park. Kim seeks reduced power consumption in its scan driver [Kim: ¶ 0063: “a size and power consumption of the scan driver according to an embodiment may be reduced”]. Park supplies a known means of obtaining it in a stage of the same kind, holding the clocks of a stage at a common high level and raising the low level of the clocks passed by the output buffers. Switching power on a clock varies with the square of the swing on that line, so the modification predictably reduces the power dissipation in Kim’s buffer clock lines. Kim routes its logic clocks and its buffer clocks on separate lines to separate blocks, so the change leaves the control of nodes NQ and NQB unaffected and requires no redesign.
Regarding claim 5:
Kim in view of Park discloses:
5. The scan driving circuit (300) [Kim: Fig.11: scan driver 330] of claim 1,
wherein the first buffer (332) [Kim: Fig.10: first output buffer 120] outputs the first scan signal corresponding to the first clock signal [Kim: ¶ 0070: “the eighth transistor T8 may be turned on in response to the voltage V_NQ of the first node NQ, and the second clock signal CLK2 having the first low level L may be output by the turned-on eighth transistor T8 as the active-low scan signal PSS having the first low level L at the first output node NO_PSS”], when the second logic signal (LS21) [Kim: Fig.10: first node NQ] is at an active level [Kim: ¶ 0052: “first and second clock signals CLK1 and CLK2 having a first low level as an active level”; Examiner: The transistors of Kim’s stage are PMOS, so the low level of node NQ is its active level and is the level that turns on the clock-passing transistor T8], and
wherein the second buffer (333) [Kim: Fig.10: second output buffer 130] outputs the second scan signal corresponding to the second clock signal [Kim: ¶ 0069: “the tenth transistor T10 may be turned on in response to the voltage V_NQ of the first node NQ having the first low level L, and the third clock signal CLK3 having the high level H may be output by the turned-on tenth transistor T10 as the active-high scan signal NSS having the high level H at the second output node NO_NSS”], when the second logic signal (LS21) [Kim: Fig.10: first node NQ] is at the active level [Kim: ¶ 0069: “the voltage V_NQ of the first node NQ having the first low level L”].
Regarding claim 6:
Kim in view of Park discloses:
6. The scan driving circuit (300) [Kim: Fig.11: scan driver 330] of claim 1,
wherein the first buffer (332) [Kim: Fig.10: first output buffer 120] outputs the first scan signal at an inactive level [Kim: ¶ 0077: “the active-low scan signal PSS and the active-high scan signal NSS at the first and second output nodes NO_PSS and NO_NSS may be stabilized by the turned-on ninth and eleventh transistors T9 and T11 to the high level H and the first low level L that may be the inactive level (or the OFF level), respectively”], when the first logic signal (LS11) [Kim: Fig.10: second node NQB] is at an active level [Kim: ¶ 0077: “If the voltage V_NQB of the second node NQB may have the second low level 2L, the ninth and eleventh transistors T9 and T11 may be fully turned on”; Examiner: The transistors of Kim’s stage are PMOS, so the low level of node NQB is its active level and is the level that turns on the ninth transistor T9, which supplies the high gate voltage VGH to the first output node NO_PSS.], and
wherein the second buffer (333) [Kim: Fig.10: second output buffer 130] outputs the second scan signal at the inactive level [Kim: ¶ 0077: “stabilized by the turned-on ninth and eleventh transistors T9 and T11 to the high level H and the first low level L that may be the inactive level (or the OFF level), respectively”], when the first logic signal (LS11) [Kim: Fig.10: second node NQB] is at the active level [Kim: ¶ 0077: “If the voltage V_NQB of the second node NQB may have the second low level 2L, the ninth and eleventh transistors T9 and T11 may be fully turned on”; The eleventh transistor T11 supplies the low gate voltage VGL to the second output node NO_NSS, which is the inactive level for the active-high scan signal NSS.].
Regarding claim 9:
Kim discloses:
9. An electronic device (10) [Kim: Fig.11: display device 300], comprising:
a display panel (DP) [Kim: Fig.11: display panel 310] including a first pixel (PXa) [Kim: Fig.12: pixel PX] and a second pixel (PXb) [Kim: ¶ 0085: “The display panel 310 may include data signal lines, active-low scan signal lines, active-high scan signal lines, emission signal lines, and the pixels PX electrically connected thereto”; Examiner: The display panel 310 contain a plurality of pixels PX, any two of which constitute the recited first and second pixels.];
and a scan driving circuit (300) [Kim: Fig.11: scan driver 330] configured to provide a first scan signal to the first pixel (PXa) [Kim: ¶ 0093: “a first stage 331 may output a first active-high scan signal NSS1 to a first pixel row in synchronization with the second N-type clock signal NCLK2, and may output a first active-low scan signal PSS1 to the first pixel row in synchronization with the second P-type clock signal PCLK2”] and a second scan signal to the second pixel (PXb) [Kim: ¶ 0093: “ a first stage 331 may output a first active-high scan signal NSS1 to a first pixel row in synchronization with the second N-type clock signal NCLK2”; Examiner: Both scan signals are supplied to the pixels of the first pixel row, so a first pixel of that row receives the first scan signals and a second, different, pixel pf that row receives the second scan signal. Claim 9 does not require that either pixel receive only of the two signals.], in response to a start signal (SS1) [Kim: ¶ 0052: “may receive, as an input signal SIN, a scan start signal FLM”], a plurality of logic clock signals, a first clock signal, and a second clock signal [Kim: ¶ 0089: “the scan control signal may include, but is not limited to, a scan start signal FLM, first and second P-type clock signals PCLK1 and PCLK2, and first and second N-type clock signals NCLK1 and NCLK2”; Examiner: In the Fig.10 stage these are CLK1 and CLK4 as the logic clock signals, CLK2 as the first clock signal and CLK3 as the second clock signal.],
wherein the scan driving circuit (300) [Kim: Fig.11: scan driver 330] includes:
a logic circuit (331) [Kim: Fig.10: logic circuit 210] configured to output a first logic signal (LS11) [Kim: Fig.10: second node NQB] and a second logic signal (LS21) [Kim: Fig.10: first node NQ], in response to the start signal (SS1) [Kim: ¶ 0052: “may receive, as an input signal SIN, a scan start signal FLM”] and the logic clock signals [Kim: ¶ 0055: “a first transistor T1 including a gate receiving the first clock signal CLK1”; ¶ 0080: “the stabilizer part 280 of the logic circuit 210 may receive a fourth clock signal CLK4 instead of a second clock signal CLK2”; Examiner: In the Fig.10, embodiment the logic circuit 210 receives two clock signals, CLK1 at the input part 140 and CLK4 at the stabilizer part 280.];
a first buffer (332) [Kim: Fig.10: first output buffer 120] configured to output the first scan signal [Kim: Fig.10: active-low scan signal PSS at first output node NO_PSS], in response to the first clock signal [Kim: ¶ 0060: “a second terminal receiving the second clock signal CLK2”], the first logic signal (LS11) [Kim: Fig.10: second node NQB] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0060: “ a ninth transistor T9 including a gate electrically connected to the second node NQB”], and the second logic signal (LS21) [Kim: Fig.10: first node NQ] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0060: “an eighth transistor T8 including a gate electrically connected to the first node NQ”];
and a second buffer (333) [Kim: Fig.10: second output buffer 130] configured to output the second scan signal [Kim: Fig.10: active-high scan signal NSS at second output node NO_NSS], in response to the second clock signal [Kim: ¶ 0061: “a second terminal receiving the third clock signal CLK3”], the first logic signal (LS11) [Kim: Fig.10: second node NQB] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0061: “an eleventh transistor T11 including a gate electrically connected to the second node NQB”], and the second logic signal (LS21) [Kim: Fig.10: first node NQ] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0061: “a tenth transistor T10 including a gate electrically connected to the first node NQ”],
wherein the logic circuit (331) [Kim: Fig.10: logic circuit 210] is commonly connected to the first buffer (332) [Kim: Fig.10: first output buffer 120; ¶ 0063: “the first output buffer 120 that may output the active-low scan signal PSS based on the voltages of the first and second nodes NQ and NQB”] and the second buffer (333) [Kim: Fig.10: second output buffer 130; ¶ 0063: “the second output buffer 130 that may output the active-high scan signal NSS based on the voltages of the first and second nodes NQ and NQB”].
However, Kim does not expressly disclose:
wherein each of the first clock signal and the second clock signal has an amplitude smaller than an amplitude of each of the logic clock signals.
Park discloses:
wherein each of the first clock signal [Park: ¶ 0074: “a second electrode of the first transistor T1 may be connected to a scan clock line SCCK5, and a gate electrode of the first transistor T1 may be connected to a third node N3”; ¶ 0177: “ The first transistor T1 and the fourth transistor T4 may be scan buffer transistors”] and the second clock signal [Park: ¶ 0075: “a second electrode of the second transistor T2 may be connected to a sensing clock line SSCK5, and a gate electrode of the second transistor T2 may be connected to the third node N3”; ¶ 0177: “ The first transistor T1 and the fourth transistor T4 may be scan buffer transistors”] has an amplitude smaller than an amplitude of each of the logic clock signals [Park: Fig.5: SCCK1-SCCK6 and SSCK1-SSCK6 shown swinging between VON and VSS1; CRCK1-CRCK6 shown swinging between VON and VSS2 and VSS3; ¶ 0137: “ a low level of the scan clock signals and the sensing clock signals may correspond to the magnitude of a voltage applied to the first power line VSS1, and a high level of the scan clock signals and the sensing clock signals may correspond to the magnitude of a gate-on voltage VON”; ¶ 0137: “the voltage applied to the first power line VSS1 may be higher than that applied to the second power line VSS2 or the third power line VSS3”; Examiner: All three clock groups share the same high level VON, and the low level of the scan and sensing clocks is higher than that of the carry clocks, so the peak-to-peak amplitude of each of the scan and sensing clocks is smaller than that of the carry clocks.].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to supply Kim’s second and third clock signals, which drive the first and second output buffers, at a smaller voltage swing than Kim’s first and fourth clock signals, which drive the logic circuit, as taught by Park. Kim seeks reduced power consumption in its scan driver [Kim: ¶ 0063: “a size and power consumption of the scan driver according to an embodiment may be reduced”]. Park supplies a known means of obtaining it in a stage of the same kind, holding the clocks of a stage at a common high level and raising the low level of the clocks passed by the output buffers. Switching power on a clock varies with the square of the swing on that line, so the modification predictably reduces the power dissipation in Kim’s buffer clock lines. Kim routes its logic clocks and its buffer clocks on separate lines to separate blocks, so the change leaves the control of nodes NQ and NQB unaffected and requires no redesign.
Regarding claim 12:
Kim in view of Park discloses:
12. The electronic device (10) [Kim: Fig.11: display device 300] of claim 9, further comprising: a driving controller (100) [Kim: ¶ 0095: “The controller (e.g., a timing controller (TCON)) 350”] configured to provide the start signal, the logic clock signals, the first clock signal, and the second clock signal [Kim: ¶ 0095: “ The controller 350 may generate the output image data ODAT, the data control signal DCTRL, the scan control signal and the emission control signal EMCTRL”; ¶ 0089: “the scan control signal may include, but is not limited to, a scan start signal FLM, first and second P-type clock signals PCLK1 and PCLK2, and first and second N-type clock signals NCLK1 and NCLK2”; Examiner: In the Fig.10 stage these are CLK1 and CLK4 as the logic clock signals, CLK2 as the first clock signal and CLK3 as the second clock signal, all supplied to the scan driver 330 by the controller 350 as components of the scan control signal.].
Regarding claim 14:
The limitations of claim 14 have been addressed in the discussion of claim 5 above.
Regarding claim 15:
The limitations of claim 15 have been addressed in the discussion of claim 6 above.
Regarding claim 19:
Kim discloses:
19. An electronic device (10) [Kim: Fig.19: electronic device 1100; ¶ 0103: “an electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input/output (I/O) device 1140, a power supply 1150, and a display device 1160”], comprising:
a processor (PP) [Kim: Fig.19: processor 1110; ¶ 0095: “an external host (e.g., a graphic processing unit (GPU) or a graphic card)”; Examiner: A graphic processing unit is a processor, the applicant’s specification at ¶ 0053 (PGPUB) identifies a graphics processing unit as one form the processor PP may take.] configured to output an image signal [Kim: ¶ 0095: “The controller (e.g., a timing controller (TCON)) 350 may receive input image data IDAT and a control signal CTRL from an external host (e.g., a graphic processing unit (GPU) or a graphic card)”] and a control signal [Kim: ¶ 0095: “he control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, or the like”];
and a display module (DM) [Kim: ¶ 0084: “a display device 300 according to an embodiment may include a display panel 310 that may include pixels PX, a data driver 320 that may provide data signals DS to the pixels PX, a scan driver 330 … and a controller 350”] configured to display an image, in response to the image signal and the control signal [Kim: ¶ 0095: “The controller 350 may generate the output image data ODAT, the data control signal DCTRL, the scan control signal and the emission control signal EMCTRL based on the input image data IDAT and the control signal CTRL”],
wherein the display module (DM) [Kim: ¶ 0107: “In the display device 1160, each stage of a scan driver may include a first output buffer that may output an active-low scan signal and a second output buffer that may output an active-high scan signal”] includes:
a display panel (DP) [Kim: Fig.11: display panel 310] including a first pixel (PXa) [Kim: Fig.12: pixel PX] and a second pixel (PXb) [Kim: ¶ 0085: “The display panel 310 may include data signal lines, active-low scan signal lines, active-high scan signal lines, emission signal lines, and the pixels PX electrically connected thereto”; Examiner: The display panel 310 contain a plurality of pixels PX, any two of which constitute the recited first and second pixels.];
a driving controller (100) [Kim: ¶ 0095: “The controller (e.g., a timing controller (TCON)) 350”] configured to output a scan control signal [Kim: ¶ 0095: “The controller 350 may generate the output image data ODAT, the data control signal DCTRL, the scan control signal and the emission control signal EMCTRL”], in response to the image signal and the control signal [Kim: ¶ 0095: “based on the input image data IDAT and the control signal CTRL”];
and a scan driving circuit (300) [Kim: Fig.11: scan driver 330] configured to provide a first scan signal to the first pixel (PXa) [Kim: ¶ 0093: “a first stage 331 may output a first active-high scan signal NSS1 to a first pixel row in synchronization with the second N-type clock signal NCLK2, and may output a first active-low scan signal PSS1 to the first pixel row in synchronization with the second P-type clock signal PCLK2”] and a second scan signal to the second pixel (PXb) [Kim: ¶ 0093: “ a first stage 331 may output a first active-high scan signal NSS1 to a first pixel row in synchronization with the second N-type clock signal NCLK2”; Examiner: Both scan signals are supplied to the pixels of the first pixel row, so a first pixel of that row receives the first scan signals and a second, different, pixel pf that row receives the second scan signal. Claim 9 does not require that either pixel receive only of the two signals.],
wherein the scan control signal includes a start signal (SS1) [Kim: ¶ 0052: “may receive, as an input signal SIN, a scan start signal FLM”], a plurality of logic clock signals, a first clock signal, and a second clock signal [Kim: ¶ 0089: “the scan control signal may include, but is not limited to, a scan start signal FLM, first and second P-type clock signals PCLK1 and PCLK2, and first and second N-type clock signals NCLK1 and NCLK2”; Examiner: In the Fig.10 stage these are CLK1 and CLK4 as the logic clock signals, CLK2 as the first clock signal and CLK3 as the second clock signal.],
wherein the scan driving circuit (300) [Kim: Fig.11: scan driver 330] includes: a logic circuit (331) [Kim: Fig.10: logic circuit 210] configured to output a first logic signal (LS11) [Kim: Fig.10: second node NQB] and a second logic signal (LS21) [Kim: Fig.10: first node NQ], in response to the start signal (SS1) [Kim: ¶ 0052: “may receive, as an input signal SIN, a scan start signal FLM”] and the logic clock signals [Kim: ¶ 0055: “a first transistor T1 including a gate receiving the first clock signal CLK1”; ¶ 0080: “the stabilizer part 280 of the logic circuit 210 may receive a fourth clock signal CLK4 instead of a second clock signal CLK2”; Examiner: In the Fig.10, embodiment the logic circuit 210 receives two clock signals, CLK1 at the input part 140 and CLK4 at the stabilizer part 280.];
a first buffer (332) [Kim: Fig.10: first output buffer 120] configured to output the first scan signal [Kim: Fig.10: active-low scan signal PSS at first output node NO_PSS], in response to the first clock signal [Kim: ¶ 0060: “a second terminal receiving the second clock signal CLK2”], the first logic signal (LS11) [Kim: Fig.10: second node NQB] which is received from the logic circuit (331) [Kim: 0060: “a ninth transistor T9 including a gate electrically connected to the second node NQB”], and the second logic signal (LS21) [Kim: Fig.10: first node NQ] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0060: “an eighth transistor T8 including a gate electrically connected to the first node NQ”];
and a second buffer (333) [Kim: Fig.10: second output buffer 130] configured to output the second scan signal [Kim: Fig.10: active-high scan signal NSS at second output node NO_NSS], in response to the second clock signal [Kim: ¶ 0061: “a second terminal receiving the third clock signal CLK3”], the first logic signal (LS11) [Kim: Fig.10: second node NQB] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0061: “an eleventh transistor T11 including a gate electrically connected to the second node NQB”], and the second logic signal (LS21) [Kim: Fig.10: first node NQ] which is received from the logic circuit (331) [Kim: Fig.10: logic circuit 210; ¶ 0061: “a tenth transistor T10 including a gate electrically connected to the first node NQ”],
wherein the logic circuit (331) [Kim: Fig.10: logic circuit 210] is commonly connected to the first buffer (332) [Kim: Fig.10: first output buffer 120; ¶ 0063: “the first output buffer 120 that may output the active-low scan signal PSS based on the voltages of the first and second nodes NQ and NQB”] and the second buffer (333) [Kim: Fig.10: second output buffer 130; ¶ 0063: “the second output buffer 130 that may output the active-high scan signal NSS based on the voltages of the first and second nodes NQ and NQB”].
However, Kim does not expressly disclose:
wherein each of the first clock signal and the second clock signal has an amplitude smaller than an amplitude of each of the logic clock signals.
Park discloses:
wherein each of the first clock signal [Park: ¶ 0074: “a second electrode of the first transistor T1 may be connected to a scan clock line SCCK5, and a gate electrode of the first transistor T1 may be connected to a third node N3”; ¶ 0177: “ The first transistor T1 and the fourth transistor T4 may be scan buffer transistors”] and the second clock signal [Park: ¶ 0075: “a second electrode of the second transistor T2 may be connected to a sensing clock line SSCK5, and a gate electrode of the second transistor T2 may be connected to the third node N3”; ¶ 0177: “ The first transistor T1 and the fourth transistor T4 may be scan buffer transistors”] has an amplitude smaller than an amplitude of each of the logic clock signals [Park: Fig.5: SCCK1-SCCK6 and SSCK1-SSCK6 shown swinging between VON and VSS1; CRCK1-CRCK6 shown swinging between VON and VSS2 and VSS3; ¶ 0137: “ a low level of the scan clock signals and the sensing clock signals may correspond to the magnitude of a voltage applied to the first power line VSS1, and a high level of the scan clock signals and the sensing clock signals may correspond to the magnitude of a gate-on voltage VON”; ¶ 0137: “the voltage applied to the first power line VSS1 may be higher than that applied to the second power line VSS2 or the third power line VSS3”; Examiner: All three clock groups share the same high level VON, and the low level of the scan and sensing clocks is higher than that of the carry clocks, so the peak-to-peak amplitude of each of the scan and sensing clocks is smaller than that of the carry clocks.].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to supply Kim’s second and third clock signals, which drive the first and second output buffers, at a smaller voltage swing than Kim’s first and fourth clock signals, which drive the logic circuit, as taught by Park. Kim seeks reduced power consumption in its scan driver [Kim: ¶ 0063: “a size and power consumption of the scan driver according to an embodiment may be reduced”]. Park supplies a known means of obtaining it in a stage of the same kind, holding the clocks of a stage at a common high level and raising the low level of the clocks passed by the output buffers. Switching power on a clock varies with the square of the swing on that line, so the modification predictably reduces the power dissipation in Kim’s buffer clock lines. Kim routes its logic clocks and its buffer clocks on separate lines to separate blocks, so the change leaves the control of nodes NQ and NQB unaffected and requires no redesign.
Claim(s) 4, 7-8, 13, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Kim; Hyun Joon, US 20220130337 A1] in view of [Park; Kyung Ho, US 20210090491 A1] and further in view of [Jo; Sunghak et al., US 20220208114 A1].
Regarding claim 4:
Kim in view of Park discloses:
4. The scan driving circuit (300) [Kim: Fig.11: scan driver 330] of claim 1.
However, Kim in view of Park does not expressly disclose:
wherein the first scan signal and the second scan signal are sequentially changed from an inactive level to an active level, when the first clock signal and the second clock signal are sequentially changed from the inactive level to the active level.
Jo discloses:
wherein the first scan signal [Jo: ¶ 0069: “A first end of each buffer BUF1 to BUF4 is configured to receive the clock signals CLK1 to CLK4, respectively, and a second end of each buffer BUF1 to BUF4 is connected to the gate lines GL1 to GL4”] and the second scan signal [Jo: ¶ 0069: “The pull-up transistors TU1 to TU4 are turned-on in response to the voltage of the Q′ nodes Q′1, Q′2, Q′3, and Q′4, and output the input clock signals CLK1 to CLK4 to the gate lines GL1 to GL4”; ¶ 0058: “the stage circuit may have a multi-buffer structure in which multiple buffers BUF1 to BUF8 are connected to one of the shift registers SR1 and SR2. For example, a first to a fourth buffers BUF1 to BUF4 may be connected to the first shift register SR1”; Examiner: The first and second buffers BUF and BUF2 are controlled from the same Q node and QB node of the one shift register SR1] are sequentially changed from an inactive level to an active level, when the first clock signal and the second clock signal are sequentially changed from the inactive level to the active level [Jo: ¶ 0052: “the generated gate signals are sequentially applied to gate lines GL1 to GL8”; Examiner: The first buffer BUF1 passes the first clock signal CLK1 to the first gate line GL1 and the second buffer BUF2 passes the second clock signal to the second gate line GL2, and the gate signals are applied to those gate lines in sequence. Because each buffer does no more than pass its own clock signal to its gate line, the clock signals change to their active levels in the same order as the gate signals they produce.].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to order Kim’s two scan signals so that the first changes to its active level before the second, in the sequence of their clock signals, as taught by Jo. Kim already changes its scan signals at separate, ordered time points, TP3 and TP4, each at the instant its buffer’s clock changes; only the order differs. Jo orders the buffers of a shared-logic stage so their gate signals reach successive gate lines in sequence, for the reason Kim shares, namely reducing driver area [Jo: ¶ 0060]. Kim supplies both clocks to the stage on separate external lines, so their phase order is already a matter of Kim’s timing control and the change require no modification to the stage.
Regarding claim 7:
Kim in view of Park discloses:
7. The scan driving circuit (300) [Kim: Fig.11: scan driver 330] of claim 1.
However, Kim in view of Park does not expressly disclose:
further comprising:
a third buffer configured to output a third scan signal, in response to a third clock signal, the first logic signal (LS11), and the second logic signal (LS21);
and a fourth buffer configured to output a fourth scan signal, in response to a fourth clock signal, the first logic signal (LS11), and the second logic signal (LS21).
Jo discloses:
further comprising:
a third buffer (GWA_A2) [Jo: ¶ 0058: “the stage circuit may have a multi-buffer structure in which multiple buffers BUF1 to BUF8 are connected to one of the shift registers SR1 and SR2. For example, a first to a fourth buffers BUF1 to BUF4 may be connected to the first shift register SR1”] configured to output a third scan signal [Jo: ¶ 0069: “a second end of each buffer BUF1 to BUF4 is connected to the gate lines GL1 to GL4”], in response to a third clock signal [Jo: ¶ 0069: “A first end of each buffer BUF1 to BUF4 is configured to receive the clock signals CLK1 to CLK4, respectively”], the first logic signal (LS11) [Jo: ¶ 0069: “The buffers BUF1 to BUF4 may further include pull-down transistors TD1 to TD4, respectively, that are turned on in response to the voltage of the QB node and output a low-potential voltage VSS to the gate lines GL1 to GL4”], and the second logic signal (LS21) [Jo: ¶ 0068: “ Each buffer BUF1 to BUF4 may include respective first transistors T11, T12, T13, and T14 that are connected between the Q node and a Q′ nodes Q′1, Q′2, Q′3, and Q′4”; Examiner: The third buffer is the buffer BUF3, which receives the clock signal CLK3 and drives the gate line GL3. Its pull-down transistor TD3 is gated from the QB node, which corresponds to the first logic signal, and its pull-up transistor TU3 is gated from the node Q’3, which receives the voltage of the Q node corresponding to the second logic signal.];
and a fourth buffer (GWB_B2) [Jo: ¶ 0058: “ a first to a fourth buffers BUF1 to BUF4 may be connected to the first shift register SR1”] configured to output a fourth scan signal [Jo: ¶ 0069: “ a second end of each buffer BUF1 to BUF4 is connected to the gate lines GL1 to GL4”], in response to a fourth clock signal [Jo: ¶ 0069: “The pull-up transistors TU1 to TU4 are turned-on in response to the voltage of the Q′ nodes Q′1, Q′2, Q′3, and Q′4, and output the input clock signals CLK1 to CLK4 to the gate lines GL1 to GL4”], the first logic signal (LS11) [Jo: ¶ 0069: “pull-down transistors TD1 to TD4, respectively, that are turned on in response to the voltage of the QB node”], and the second logic signal (LS21) [Jo: ¶ 0068: “ first transistors T11, T12, T13, and T14 that are connected between the Q node and a Q′ nodes Q′1, Q′2, Q′3, and Q′4”; Examiner: The fourth buffer is the buffer BUF4, which receives the clock signal CLK4 and drive the gate line GL4, and is controlled from the same QB node and Q node as the other three buffers of the stage.].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add third and fourth output buffers to Kim’s stage, each taking its own clock and controlled from the same nodes NQB and NQ, as taught by Jo. Jo puts four buffers on one shift register and shrink the driver [Jo: ¶ 0060], the same reduction Kim seeks. Kim already drives two buffers from one logic circuit and supplies its buffer clocks externally, so adding two more requires no change to the logic circuit and predictably yields fewer logic circuits per scan line.
Regarding claim 8:
Kim in view of Park and further in Jo discloses:
8. The scan driving circuit (300) [Kim: Fig.11: scan driver 330] of claim 7.
Jo further discloses:
wherein the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal [Jo: ¶ 0069: “a second end of each buffer BUF1 to BUF4 is connected to the gate lines GL1 to GL4”] are sequentially changed from an inactive level to an active level [Jo: ¶ 0052: “the generated gate signals are sequentially applied to gate lines GL1 to GL8”], when the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal [Jo: ¶ 0069: “A first end of each buffer BUF1 to BUF4 is configured to receive the clock signals CLK1 to CLK4, respectively”] are sequentially changed from the inactive level to the active level [Jo: ¶ 0069: “The pull-up transistors TU1 to TU4 are turned-on in response to the voltage of the Q′ nodes Q′1, Q′2, Q′3, and Q′4, and output the input clock signals CLK1 to CLK4 to the gate lines GL1 to GL4”; Examiner: Each of the four buffers does no more than pass its own cock signal to its own gate line, so the four clock signals change to their active levels in the same order, which Jo applies to the gate lines in sequence].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to phase the four clock signals, as taught by Jo, so that each buffer’s clock and its scan signal go active in turn. Jo drives four buffers from one set of node-control circuitry to four successive scan lines, applying their gate signals in sequence, and four successive scan lines serve no purpose unless driven in succession. Kim generates its buffer clocks outside the stage, so their relative phase is fixed upstream and the stage itself needs no change. The timing constraint Kim imposes on a buffer clock, that it fall while the controlling node remains bootstrapped, is met for every buffer regardless of driving order, since Jo transmits the bootstrapped voltage of the shared node to each buffer’s own control node.
Regarding claim 13:
The limitations of claim 13 have been addressed in the discussion of claim 4 above.
Regarding claim 20:
The limitations of claim 20 have been addressed in the discussion of claim 4 above.
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Kim; Hyun Joon, US 20220130337 A1] in view of [Park; Kyung Ho, US 20210090491 A1] and further in view of [Lin; Yi Cheng et al., US 20200234647 A1].
Regarding claim 16:
Kim in view of Park discloses:
16. The electronic device (10) [Kim: Fig.11: display device 300] of claim 9.
However, Kim in view of Park does not expressly disclose:
wherein a data line is commonly connected to the first pixel (PXa) and the second pixel (PXb), and
wherein the first scan signal and the second scan signal are sequentially changed from an inactive level to an active level.
Lin discloses:
wherein a data line [Lin: Fig.2: data line Data] is commonly connected to the first pixel (PXa) and the second pixel (PXb) [Lin: Fig.2: ¶ 0079: “as shown in FIG. 2, two pixel circuits 100 connected to the same data line Data in the same row are respectively”], and
wherein the first scan signal and the second scan signal are sequentially changed from an inactive level to an active level [Lin: ¶ 0079: “This arrangement enables the pixel circuits 100 of the sub-pixels in the (2n-1)th column and the pixel circuits 100 of the sub-pixels in the adjacent (2n)th column to be turned on in a time-sharing manner”; Examiner: Turning the two pixel circuits on in a time-sharing manner through two different gate lines requires the two gate signals to reach their active levels at different times, one after the other.].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to connect one data line to both pixels of Kim’s display panel and drive the two scan signals in sequence, as taught by Lin, which states the purpose [Lin: ¶ 0079: “ it is convenient to use the common data line Data to provide different data signals for the pixel circuits 100 sharing the data line Data”]. Kim’s stage already applies its two scan signals to a row at different time points, supplying the separated addressing that sharing a data line requires, so the modification halves the data lines and data driver output for a given pixel count while leaving the scan driver unchanged.
Regarding claim 17:
Kim in view of Park and further in view of Lin discloses:
17. The electronic device (10) [Kim: Fig.11: display device 300] of claim 16.
Lin further discloses:
wherein the first pixel (PXa) and the second pixel (PXb) are sequentially disposed in a first row [Lin: Fig.2; ¶ 0079: “two pixel circuits 100 connected to the same data line Data in the same row are respectively connected with two different gate lines Gate”].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to connect one data line to both pixels of Kim’s display panel and drive the two scan signals in sequence, as taught by Lin, which states the purpose [Lin: ¶ 0079: “ it is convenient to use the common data line Data to provide different data signals for the pixel circuits 100 sharing the data line Data”]. Kim’s stage already applies its two scan signals to a row at different time points, supplying the separated addressing that sharing a data line requires, so the modification halves the data lines and data driver output for a given pixel count while leaving the scan driver unchanged.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over [Kim; Hyun Joon, US 20220130337 A1] in view of [Park; Kyung Ho, US 20210090491 A1], [Lin; Yi Cheng et al., US 20200234647 A1] and further in view of [Jo; Sunghak et al., US 20220208114 A1].
Regarding claim 18:
Kim in view of Park and further in view of Lin discloses
18. The electronic device (10) [Kim: Fig.11: display device 300] of claim 17,
wherein the display panel (DP) [Kim: Fig.11: display panel 310] further includes: a third pixel and a fourth pixel disposed in a second row [Kim: ¶ 0093: “a second stage 332 may output a second active-high scan signal NSS2 to a second pixel row in synchronization with the first N-type clock signal NCLK1, and may output a second active-low scan signal PSS2 to the second pixel row in synchronization with the first P-type clock signal PCLK1”; Examiner: Kim’s display panel contains a plurality of pixel rows, and the pixels of its second pixel row include a third and fourth pixel.].
However, Kim in view of Park and further in view of Lin does not expressly disclose:
wherein the scan driving circuit (300) further includes:
a third buffer configured to output a third scan signal, in response to a third clock signal, the first logic signal (LS11), and the second logic signal (LS21);
and a fourth buffer configured to output a fourth scan signal, in response to a fourth clock signal, the first logic signal (LS11), and the second logic signal (LS21).
Jo discloses:
wherein the scan driving circuit (300) further includes:
a third buffer (GWA_A2) [Jo: ¶ 0058: “the stage circuit may have a multi-buffer structure in which multiple buffers BUF1 to BUF8 are connected to one of the shift registers SR1 and SR2. For example, a first to a fourth buffers BUF1 to BUF4 may be connected to the first shift register SR1”] configured to output a third scan signal [Jo: ¶ 0069: “a second end of each buffer BUF1 to BUF4 is connected to the gate lines GL1 to GL4”], in response to a third clock signal [Jo: ¶ 0069: “A first end of each buffer BUF1 to BUF4 is configured to receive the clock signals CLK1 to CLK4, respectively”], the first logic signal (LS11) [Jo: ¶ 0069: “The buffers BUF1 to BUF4 may further include pull-down transistors TD1 to TD4, respectively, that are turned on in response to the voltage of the QB node and output a low-potential voltage VSS to the gate lines GL1 to GL4”], and the second logic signal (LS21) [Jo: ¶ 0068: “ Each buffer BUF1 to BUF4 may include respective first transistors T11, T12, T13, and T14 that are connected between the Q node and a Q′ nodes Q′1, Q′2, Q′3, and Q′4”; Examiner: The third buffer is the buffer BUF3, which receives the clock signal CLK3 and drives the gate line GL3. Its pull-down transistor TD3 is gated from the QB node, which corresponds to the first logic signal, and its pull-up transistor TU3 is gated from the node Q’3, which receives the voltage of the Q node corresponding to the second logic signal.];
and a fourth buffer (GWB_B2) [Jo: ¶ 0058: “ a first to a fourth buffers BUF1 to BUF4 may be connected to the first shift register SR1”] configured to output a fourth scan signal [Jo: ¶ 0069: “ a second end of each buffer BUF1 to BUF4 is connected to the gate lines GL1 to GL4”], in response to a fourth clock signal [Jo: ¶ 0069: “The pull-up transistors TU1 to TU4 are turned-on in response to the voltage of the Q′ nodes Q′1, Q′2, Q′3, and Q′4, and output the input clock signals CLK1 to CLK4 to the gate lines GL1 to GL4”], the first logic signal (LS11) (LS11) [Jo: ¶ 0069: “pull-down transistors TD1 to TD4, respectively, that are turned on in response to the voltage of the QB node”], and the second logic signal (LS21) [Jo: ¶ 0068: “ first transistors T11, T12, T13, and T14 that are connected between the Q node and a Q′ nodes Q′1, Q′2, Q′3, and Q′4”; Examiner: The fourth buffer is the buffer BUF4, which receives the clock signal CLK4 and drive the gate line GL4, and is controlled from the same QB node and Q node as the other three buffers of the stage.].
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to add third and fourth output buffers to Kim’s stage, each taking its own clock and controlled from the same nodes NQB and NQ, as taught by Jo. Jo puts four buffers on one shift register and shrink the driver [Jo: ¶ 0060], the same reduction Kim seeks. Kim already drives two buffers from one logic circuit and supplies its buffer clocks externally, so adding two more requires no change to the logic circuit and predictably yields fewer logic circuits per scan line.
Allowable Subject Matter
Claim 2-3 and 10-11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the first buffer includes: a first transistor connected between a first voltage input terminal and a scan output terminal and configured to output the first scan signal, wherein the first transistor includes a gate electrode and is configured to receive the first logic signal; a second transistor connected between a first node and a second node, wherein the second transistor includes a gate electrode connected to a second voltage input terminal; a third transistor connected between the scan output terminal and a clock input terminal and configured to receive the first scan signal, wherein the third transistor includes a gate electrode connected to the second node; and a capacitor connected between the second node and the scan output terminal”, in combination with the other recited claim features.
Regarding claim 3:
The prior art does not teach or suggest either singularly or in combination the at least claimed “wherein the second buffer includes: a first transistor connected between a first voltage input terminal and a scan output terminal and configured to output the second scan signal, wherein the first transistor includes a gate electrode and is configured to receive the first logic signal; a second transistor connected between a first node and a second node, wherein the second transistor includes a gate electrode connected to a second voltage input terminal; a third transistor connected between the scan output terminal and a clock input terminal and configured to receive the second scan signal, wherein the third transistor includes a gate electrode connected to the second node; and a capacitor connected between the second node and the scan output terminal”, in combination with the other recited claim features.
Regarding claim 10:
The limitations of claim 10 have been addressed in the discussion of claim 2 above.
Regarding claim 11:
The limitations of claim 11 have been addressed in the discussion of claim 3 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[Lin; Cheng-Hsing, US 20250095557 A1] discloses:
“A scanning drive circuit includes: a start-up circuit, activated based on a start-up signal or a previous stage output signal to pre-charge a first internal node; a logic gate operating based on the start-up signal or the previous stage output signal and a first output signal to control a second voltage at a second internal node; a pull-down circuit determining whether to pull down a first voltage of the first internal node based on the second voltage of the second internal node; and a plurality of output circuits pre-charging a third internal node based on the first voltage of the first internal node and generating a plurality of output signals based on a scanning clock signal or a plurality of clock signals, and further determining whether to pull down the output signals based on the second voltage of the second internal node,” as recited in the abstract.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Koosha Sharifi-Tafreshi whose telephone number is (571)270-5897. The examiner can normally be reached Mon - Fri 8AM to 5PM EST.
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/KOOSHA SHARIFI-TAFRESHI/Primary Examiner, Art Unit 2628
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