DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
2. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
3. The abstract of the disclosure is objected to because it recites “Examples of the present application disclose” in line 1, which can be implied. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Memory with Loading Circuit Providing Drivers with Different Gate Voltages.”
Double Patenting
5. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
6. Claims 9 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 12494252 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 9 and 18 of the instant application recite a subset of the features of claim 4 in US 12494252 B2.
Claim Limitations of the Instant Application
Claim Limitations of US Patent 12494252 B2
Claim 9: The memory device of claim 5, wherein the voltage converter circuit comprises a first phase inverter, a second phase inverter, a first depletion-N-metal oxide semiconductor (NDMOS) transistor, a second NDMOS transistor, and a P-metal oxide semiconductor (PMOS) transistor, whereinan output terminal of the first phase inverter is coupled with an input terminal of the second phase inverter and a gate of the PMOS transistor, respectively, an output terminal of the second phase inverter is coupled with an input terminal of the first NDMOS transistor, and an output terminal of the first NDMOS transistor is coupled with a gate of the second NDMOS transistor; andan input terminal of the second NDMOS transistor is coupled with a first power loading terminal, an output terminal of the second NDMOS transistor is coupled with an input terminal of the PMOS transistor, and an output terminal of the PMOS transistor is connected in parallel with the output terminal of the first NDMOS transistor and then coupled with a first output terminal.
Claim 4: The memory of claim 3, wherein the voltage converter comprises a first phase inverter, a second phase inverter, a first depletion-N-metal oxide semiconductor (NDMOS) transistor, a second NDMOS transistor, and a P-metal oxide semiconductor (PMOS)transistor, wherein the voltage converter further comprises: an input terminal of the first phase inverter coupled with the control terminal, an output terminal of the first phase inverter respectively coupled with an input terminal of the second phase inverter and a gate of the PMOS transistor respectively, an output terminal of the second phase inverter coupled with an input terminal of the first NDMOS transistor, and an output terminal of the first NDMOS transistor coupled with a gate of the second NDMOS transistor; and an input terminal of the second NDMOS transistor coupled with the first power loading terminal, an output terminal of the second NDMOS transistor coupled with an input terminal of the PMOS transistor, and an output terminal of the PMOS transistor connected in parallel with the output terminal of the first NDMOS transistor and coupled with the first output terminal, and wherein the first voltage is equal to the third voltage.
Claim 18: The memory device of claim 14, wherein the voltage converter circuit comprises a first phase inverter, a second phase inverter, a first depletion-N-metal oxide semiconductor (NDMOS) transistor, a second NDMOS transistor, and a P-metal oxide semiconductor (PMOS) transistor, whereinan output terminal of the first phase inverter is coupled with an input terminal of the second phase inverter and a gate of the PMOS transistor, respectively, an output terminal of the second phase inverter is coupled with an input terminal of the first NDMOS transistor, and an output terminal of the first NDMOS transistor is coupled with a gate of the second NDMOS transistor, andan input terminal of the second NDMOS transistor is coupled with a first power loading terminal, an output terminal of the second NDMOS transistor is coupled with an input terminal of the PMOS transistor, and an output terminal of the PMOS transistor is connected in parallel with the output terminal of the first NDMOS transistor and then coupled with a first output terminal.
Claim 4: The memory of claim 3, wherein the voltage converter comprises a first phase inverter, a second phase inverter, a first depletion-N-metal oxide semiconductor (NDMOS) transistor, a second NDMOS transistor, and a P-metal oxide semiconductor (PMOS) transistor, wherein the voltage converter further comprises: an input terminal of the first phase inverter coupled with the control terminal, an output terminal of the first phase inverter respectively coupled with an input terminal of the second phase inverter and a gate of the PMOS transistor respectively, an output terminal of the second phase inverter coupled with an input terminal of the first NDMOS transistor, and an output terminal of the first NDMOS transistor coupled with a gate of the second NDMOS transistor; and an input terminal of the second NDMOS transistor coupled with the first power loading terminal, an output terminal of the second NDMOS transistor coupled with an input terminal of the PMOS transistor, and an output terminal of the PMOS transistor connected in parallel with the output terminal of the first NDMOS transistor and coupled with the first output terminal, and wherein the first voltage is equal to the third voltage.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Futatsuyama, et al (US 20060186942 A1), hereinafter Futatsuyama.
Regarding independent claim 1, Futatsuyama teaches a memory device (FIG. 1), comprising:
a memory array (FIG. 1, 101); and
a periphery circuit coupled to the memory array (FIG. 1, e.g., row decoder 105, voltage generating circuits 120, etc.; ¶[0036-0037]), the periphery circuit comprising:
a first driver comprising a first transistor (FIG. 5, QN9; ¶[0043]; note for convenience of explanation, the second embodiment of the level shifter (FIGS. 13-14, 54”) will be referenced in place of level shifter 54 going forward), wherein a first current terminal of the first transistor is coupled to at least one of a top select gate (FIG. 5, QN9 shown coupled to top select gate S1) or a bottom select gate, and a gate terminal of the first transistor is configured to receive a first voltage (FIG. 5, voltage at node N1 (output of INV1)); and
a second driver comprising a second transistor (FIG. 5, e.g., QN1; ¶[0043]), wherein a first current terminal of the second transistor is coupled to a first word line (FIG. 5, QN1 shown coupled to word line CG(1); ¶[0041]), and a gate terminal of the second transistor is configured to receive a second voltage (FIG. 5, voltage at node N10(OUTPUT)) different from the first voltage (voltage at node N1 will be either VSS or Vdd (see, e.g., ¶[0062], [0064]), while the voltage at node N10(OUTPUT) will be adjusted by the threshold voltage of transistor HNE2 (FIG. 14, OUTPUT waveform during period from t2 to t4 is Vdd-Vth(HNE2), during which time INPUT is Vdd and therefore the voltage at N1 will be Vss)).
Regarding claim 6, Futatsuyama teaches the limitations of claim 1.
Futatsuyama further teaches the first voltage is smaller than the second voltage in a normal programming mode of the memory devices (FIG. 14, first voltage OUTPUT is positive in the time period from t2 to tr2, while second voltage at node N1 (FIGS. 5 and 13) remains at Vss (FIG. 14, INPUT is Vdd and therefore N1 is Vss)).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Futatsuyama, et al (US 20060186942 A1), hereinafter Futatsuyama, in view of Kikuchi, et al (US 20230317181 A1), hereinafter Kikuchi.
Regarding independent claim 19, Futatsuyama teaches a memory device (FIG. 1), comprising:
a memory array (FIG. 1, 101); and
a periphery circuit coupled to the memory array (FIG. 1, e.g., row decoder 105, voltage generating circuits 120, etc.; ¶[0036-0037]), the periphery circuit comprising:
a first driver comprising a first transistor (FIG. 5, QN9; ¶[0043]; note for convenience of explanation, the second embodiment of the level shifter (FIGS. 13-14, 54”) will be referenced in place of level shifter 54 going forward), wherein a first current terminal of the first transistor is coupled to at least one of a top select gate (FIG. 5, QN9 shown coupled to top select gate S1) or a bottom select gate, and a gate terminal of the first transistor is configured to receive a first voltage (FIG. 5, voltage at node N1 (output of INV1)); and
a second driver comprising a second transistor (FIG. 5, e.g., QN1; ¶[0043]), wherein a first current terminal of the second transistor is coupled to a first word line (FIG. 5, QN1 shown coupled to word line CG(1); ¶[0041]), and a gate terminal of the second transistor is configured to receive a second voltage (FIG. 5, voltage at node N10(OUTPUT)) different from the first voltage (FIG. 5, voltage at node N10(OUTPUT)) different from the first voltage (voltage at node N1 will be either VSS or Vdd (see, e.g., ¶[0062], [0064]), while the voltage at node N10(OUTPUT) will be adjusted by the threshold voltage of transistor HNE2 (FIG. 14, OUTPUT waveform during period from t2 to t4 is Vdd-Vth(HNE2))).
Futatsuyama does not teach the memory device is part of a memory system, comprising a memory controller coupled to the memory device and configured to control the memory device.
Kikuchi teaches the memory device is part of a memory system (FIG. 1, ¶[0028]), comprising a memory controller (FIG. 1, 1) coupled to the memory device (FIG. 1, 2) and configured to control the memory device (¶[0030]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kikuchi into the method of Futatsuyama to include a controller in a system implementation. The ordinary artisan would have been motivated to modify Futatsuyama in the above manner for the purpose of controlling reads and writes of data in according with requests from a host (Kikuchi ¶[0030]).
Allowable Subject Matter
11. Claims 10-17 are allowed.
12. Claims 2-5, 7-8, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
13. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 2, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the periphery circuit further comprises a source follower circuit, wherein a first terminal of the source follower circuit is coupled to the gate terminal of the first transistor, and a second terminal of the source follower circuit is coupled to the gate terminal of the second transistor, and the first terminal of the source follower circuit is different from the second terminal of the source follower circuit. Claims 2-5 and 7-9 depend on claim 2, but claim 9 is rejected due to double patenting.
Regarding claim 10, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of a periphery circuit coupled to the memory array, the periphery circuit comprising:
a source follower circuit, wherein a first terminal of the source follower circuit is coupled to a gate terminal of the first transistor, a second terminal of the source follower circuit is coupled to a gate terminal of the second transistor, and the first terminal of the source follower circuit is different from the second terminal of the source follower circuit. Claims 11-18 depend on claim 10, but claim 18 is rejected due to double patenting.
Regarding claim 20, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the periphery circuit is further comprises a source follower circuit, wherein a first terminal of the source follower circuit is coupled to the gate terminal of the first transistor, a second terminal of the source follower circuit is coupled to the gate terminal of the second transistor, and the first terminal of the source follower circuit is different from the second terminal of the source follower circuit.
Citation of Relevant Art
14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen, et al (US 20090147799 A1) teaches a source follower, but as part of a data driver feeding the drain of the top transistor of an inverter stage.
Miyamoto (US 5831900 A) uses a source follower WL driver circuit, but the source follower is not a single-transistor, nor does it feed the gate of a WL driver transistor.
Ogura, et al (US 20020131304 A1) uses source followers as sub-bitline drivers.
Futatsuyama, et al (US 20010005015 A1) uses different driver gate voltages for word line drivers and top/bottom select line drivers, but does not disclose a source follower circuit feeding any driver gates.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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