Prosecution Insights
Last updated: July 17, 2026
Application No. 19/392,126

DISPLAY DEVICE

Non-Final OA §DP
Filed
Nov 17, 2025
Priority
Oct 16, 2020 — RE 10-2020-0134107 +1 more
Examiner
SHEN, YUZHEN
Art Unit
2623
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
1y 9m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
520 granted / 735 resolved
+8.7% vs TC avg
Moderate +13% lift
Without
With
+13.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
41 currently pending
Career history
780
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
90.0%
+50.0% vs TC avg
§102
3.8%
-36.2% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 735 resolved cases

Office Action

§DP
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority 2. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Obviousness-Type Double Patenting 3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Langi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761(CCPA1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321 (d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(1)(1) - 706.02(1)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321 (b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process /file/ efs/quidance/eTD-info-l.jsp. 4. Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12477908 B2. Although the claims at issue are not identical, they are not patentably distinct from each other. Present application (19392126) US Patent 12477908 B2 Claim 1 Claim 1 An electronic device, comprising: A display device, comprising: a first substrate; a first substrate; a conductive layer comprising a first voltage line configured to supply a first voltage, a second voltage line configured to supply a second voltage, and a third voltage line spaced from each other along a first direction on the first substrate, the first voltage being different from the second voltage; a conductive layer comprising a first voltage line configured to supply a first voltage, a second voltage line configured to supply a second voltage, and a third voltage line spaced from each other along a first direction on the first substrate, the first voltage being different from the second voltage; an interlayer insulating layer on the conductive layer; an interlayer insulating layer on the conductive layer; first and second electrodes on the interlayer insulating layer and spaced from each other along the first direction; first and second electrodes on the interlayer insulating layer and spaced from each other along the first direction; a plurality of light emitting elements having at least one end on and overlapping the first electrode or the second electrode; a plurality of light emitting elements having at least one end on and overlapping the first electrode or the second electrode; a first contact electrode on first ends of some of the plurality of light emitting elements and not overlapping the first electrode and the second electrode; and a second contact electrode on second ends of some of the plurality of light emitting elements, a first contact electrode on first ends of some of the plurality of light emitting elements and not overlapping the first electrode and the second electrode; and a second contact electrode on second ends of some of the plurality of light emitting elements, wherein the first electrode and the second electrode do not overlap the first voltage line and the third voltage line, respectively, wherein the first electrode and the second electrode do not overlap the first voltage line and the third voltage line, respectively, wherein the plurality of light emitting elements comprises first light emitting elements on the first electrode and the first voltage line, and second light emitting elements on the second electrode and the third voltage line, and wherein the plurality of light emitting elements comprises first light emitting elements on the first electrode and the first voltage line, and second light emitting elements on the second electrode and the third voltage line, and wherein the first voltage line, the second voltage line, and the third voltage line are located at a layer that is different from a layer in which the first contact electrode is located. wherein the first voltage line, the second voltage line, and the third voltage line are located at a layer that is different from a layer in which the first contact electrode is located. As shown in the comparison above, the instant application claim 1 is broader or same in every aspect than the patent claim 1 of US 12477908 B2 and is therefore an obvious variant thereof. Claims 2-14 recite the same or similar limitations as claims 2-14 of US 12477908 B2, and therefore are rejected. 5. Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 12477908 B2. Although the claims at issue are not identical, they are not patentably distinct from each other. Present application (19392126) US Patent 12477908 B2 Claim 15 Claim 15 An electronic device, comprising: A display device, comprising: a first substrate; a first substrate; a conductive layer comprising a first voltage line configured to supply a first voltage, and a second voltage line configured to supply a second voltage, on the first substrate and spaced from each other along a first direction and extending in a second direction, the first voltage being different from the second voltage; a conductive layer comprising a first voltage line configured to supply a first voltage, and a second voltage line configured to supply a second voltage, on the first substrate and spaced from each other along a first direction and extending in a second direction, the first voltage being different from the second voltage; an interlayer insulating layer on the conductive layer; an interlayer insulating layer on the conductive layer; a first electrode extending in the second direction and on the interlayer insulating layer, the first electrode overlapping the second voltage line; a first electrode extending in the second direction and on the interlayer insulating layer, the first electrode overlapping the second voltage line; a plurality of light emitting elements, at least one of the light emitting elements having one end on the first electrode and extending in one direction; a plurality of light emitting elements, at least one of the light emitting elements having one end on the first electrode and extending in one direction; a first contact electrode on an other end of the light emitting element; and a second contact electrode on the one end of the light emitting element and contacting the first electrode, a first contact electrode on an other end of the light emitting element; and a second contact electrode on the one end of the light emitting element and contacting the first electrode, wherein the first electrode and the first voltage line do not overlap each other in a thickness direction of the first substrate, and wherein the first electrode and the first voltage line do not overlap each other in a thickness direction of the first substrate, and wherein the first voltage line and the second voltage line are located at a layer that is different from a layer in which the first contact electrode is located. wherein the first voltage line and the second voltage line are located at a layer that is different from a layer in which the first contact electrode is located. As shown in the comparison above, the instant application claim 15 is broader or same in every aspect than the patent claim 15 of US 12477908 B2 and is therefore an obvious variant thereof. Claims 16-17 recite the same or similar limitations as claims 16-17 of US 12477908 B2, and therefore are rejected. Allowable Subject Matter 5. Claims 1-20 would be allowable if double patenting rejections are overcome. The following is an examiner’s statement of reasons for allowance: The present invention is directed to a display. The closet prior arts, Shibata (US 20110089850 A1), Shibata (US 20120326181 A1), Cho (US 20180019369 A1), Choi (US 20200212268 A1), Shibata (US 20110089850 A1), Im (US 20190115513 A1), Xi (US 10468394 B1), and Kwon (US 20200119244 A1), individually or in combination, discloses a display similar to the claimed invention, comprising: a first substrate; a conductive layer comprising a first voltage line configured to supply a first voltage, a second voltage line configured to supply a second voltage, and a third voltage line spaced from each other along a first direction on the first substrate, the first voltage being different from the second voltage; an interlayer insulating layer on the conductive layer; first and second electrodes on the interlayer insulating layer and spaced from each other along the first direction; a plurality of light emitting elements comprises first light emitting elements on the first electrode and the first voltage line, and second light emitting elements on the second electrode and the third voltage line, and wherein the first voltage line, the second voltage line, and the third voltage line are located at a layer that is different from a layer in which the first contact electrode is located, but fails to teach wherein the first voltage line and the second voltage line are located at a layer that is different from a layer in which the first contact electrode is located, and the plurality of light emitting elements having at least one end on and overlapping the first electrode or the second electrode; a first contact electrode on first ends of some of the plurality of light emitting elements and not overlapping the first electrode and the second electrode. Inquiry Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on Monday-Thursday 8:30am-5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YUZHEN SHEN/Primary Examiner, Art Unit 2623
Read full office action

Prosecution Timeline

Nov 17, 2025
Application Filed
Jun 04, 2026
Non-Final Rejection mailed — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684105
ELECTRONIC DEVICE FOR PROVIDING ADDITIONAL IMAGE AND OPERATING METHOD THEREOF
2y 8m to grant Granted Jul 14, 2026
Patent 12675971
METHODS AND SYSTEMS FOR AUTOMATED FOLLOW-UP READING OF MEDICAL IMAGE DATA
2y 7m to grant Granted Jul 07, 2026
Patent 12666791
DISPLAY DEVICE AND MOBILE TERMINAL INCLUDING THE SAME
3y 10m to grant Granted Jun 23, 2026
Patent 12665999
WEARABLE TERMINAL DEVICE, PROGRAM, AND DISPLAY METHOD
2y 9m to grant Granted Jun 23, 2026
Patent 12660443
Display Substrate, Preparation Method Therefor, and Display Apparatus
3y 1m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
84%
With Interview (+13.4%)
2y 5m (~1y 9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 735 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month