Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KR20260021509A (English machine translation).
Regarding claims 1, 18, CHO JAE HYUNG WO2014017472A1 (English machine translation), figs. 10-21, discloses a display device comprising: a display panel comprising a display area (DA)and a non-display area (NDA); a first gate driver (located in the non-display area adjacent to the display area (DA); an emission controller located in the non-display area adjacent to an edge of the display panel (see emission control stages, fig. 10); a second gate driver located in the non-display area between the first gate driver and the emission controller (see fig. 10, GBST and GWST); and a plurality of pixel power lines connected to pixels of the display area, wherein at least one of the plurality of pixel power lines overlaps at least one of the second gate driver or the emission controller (see figs. 10-21, pars. 27, 54, The power supply unit (700) can supply various power sources and voltages required for driving the light-emitting pixel drivers (EPDs).[For example, the power supply unit (700) can supply a first power supply (ELVDD of FIG. 8) and a second power supply (ELVSS of FIG. 8) for generating a driving signal transmitted to light-emitting elements (LEs), and a gate initialization voltage (VINT of FIG. 8) and an anode initialization voltage (VAINT of FIG. 8) for initializing light-emitting pixel drivers (EPDs), pars. 198, 200).
Regarding claims 2, 19, CHO JAE HYUNG WO2014017472A1 (English machine translation), figs. 10-21, discloses the display device of claim 1, wherein the plurality of pixel power lines comprises a bias voltage line, a first initialization voltage line, a common voltage line, a second-first initialization voltage line, and a second-second initialization voltage line ([The gate wirings (GL) may include a scan write wiring (GWL) that transmits a scan write signal (GW), a scan initialization wiring (GIL) that transmits a scan initialization signal (GI), an emission control wiring (ECL) that transmits an emission control signal (EC), a gate control wiring (GCL) that transmits a gate control signal (GC), and a bias control wiring (GBL) that transmits a bias control signal (GB).] [The circuit layer (120) may include a data line (DL) that transmits a data signal (Vdata), a first power line (VDL) that transmits a first power signal (ELVDD), a gate initialization voltage line (VIL) that transmits a gate initialization voltage (VINT), an anode initialization voltage line (VAIL) that transmits an anode initialization voltage (VAINT), and a bias voltage line (VBSL) that transmits a bias voltage (VBS). [Each of the light-emitting elements (LEs) may further include first common layers disposed between the anode electrodes (131) and the light-emitting layers (133), and second common layers disposed between the light-emitting layers (133) and the cathode electrodes (134).]
Regarding claims 3, 20, CHO JAE HYUNG WO2014017472A1 (English machine translation), figs. 10-21, discloses the display device of claim 2, wherein the second-first initialization voltage line overlaps the second gate driver, and wherein the second-second initialization voltage line overlaps the emission controller (see figs. 10-21, pars. 27, 54, The power supply unit (700) can supply various power sources and voltages required for driving the light-emitting pixel drivers (EPDs).[For example, the power supply unit (700) can supply a first power supply (ELVDD of FIG. 8) and a second power supply (ELVSS of FIG. 8) for generating a driving signal transmitted to light-emitting elements (LEs), and a gate initialization voltage (VINT of FIG. 8) and an anode initialization voltage (VAINT of FIG. 8) for initializing light-emitting pixel drivers (EPDs), pars. 198, 200).
Regarding claim 4, CHO JAE HYUNG WO2014017472A1 (English machine translation), figs. 10-21, discloses the display device of claim 3, wherein the bias voltage line, the first initialization voltage line, and the common voltage line overlap the first gate driver([The gate wirings (GL) may include a scan write wiring (GWL) that transmits a scan write signal (GW), a scan initialization wiring (GIL) that transmits a scan initialization signal (GI), an emission control wiring (ECL) that transmits an emission control signal (EC), a gate control wiring (GCL) that transmits a gate control signal (GC), and a bias control wiring (GBL) that transmits a bias control signal (GB).] [The circuit layer (120) may include a data line (DL) that transmits a data signal (Vdata), a first power line (VDL) that transmits a first power signal (ELVDD), a gate initialization voltage line (VIL) that transmits a gate initialization voltage (VINT), an anode initialization voltage line (VAIL) that transmits an anode initialization voltage (VAINT), and a bias voltage line (VBSL) that transmits a bias voltage (VBS). [Each of the light-emitting elements (LEs) may further include first common layers disposed between the anode electrodes (131) and the light-emitting layers (133), and second common layers disposed between the light-emitting layers (133) and the cathode electrodes (134).
Regarding claim 5, CHO JAE HYUNG WO2014017472A1 (English machine translation), figs. 10-21, discloses the display device of claim 2, wherein the bias voltage line overlaps the second gate driver, and wherein the first initialization voltage line overlaps the emission controller ([The gate wirings (GL) may include a scan write wiring (GWL) that transmits a scan write signal (GW), a scan initialization wiring (GIL) that transmits a scan initialization signal (GI), an emission control wiring (ECL) that transmits an emission control signal (EC), a gate control wiring (GCL) that transmits a gate control signal (GC), and a bias control wiring (GBL) that transmits a bias control signal (GB).] [The circuit layer (120) may include a data line (DL) that transmits a data signal (Vdata), a first power line (VDL) that transmits a first power signal (ELVDD), a gate initialization voltage line (VIL) that transmits a gate initialization voltage (VINT), an anode initialization voltage line (VAIL) that transmits an anode initialization voltage (VAINT), and a bias voltage line (VBSL) that transmits a bias voltage (VBS). [Each of the light-emitting elements (LEs) may further include first common layers disposed between the anode electrodes (131) and the light-emitting layers (133), and second common layers disposed between the light-emitting layers (133) and the cathode electrodes (134).].
Regarding claim 6, CHO JAE HYUNG WO2014017472A1 (English machine translation), figs. 10-21, discloses the display device of claim 5, wherein the common voltage line, the second-first initialization voltage line, and the second-second initialization voltage line overlap the first gate driver ([The gate wirings (GL) may include a scan write wiring (GWL) that transmits a scan write signal (GW), a scan initialization wiring (GIL) that transmits a scan initialization signal (GI), an emission control wiring (ECL) that transmits an emission control signal (EC), a gate control wiring (GCL) that transmits a gate control signal (GC), and a bias control wiring (GBL) that transmits a bias control signal (GB).] [The circuit layer (120) may include a data line (DL) that transmits a data signal (Vdata), a first power line (VDL) that transmits a first power signal (ELVDD), a gate initialization voltage line (VIL) that transmits a gate initialization voltage (VINT), an anode initialization voltage line (VAIL) that transmits an anode initialization voltage (VAINT), and a bias voltage line (VBSL) that transmits a bias voltage (VBS). [Each of the light-emitting elements (LEs) may further include first common layers disposed between the anode electrodes (131) and the light-emitting layers (133), and second common layers disposed between the light-emitting layers (133) and the cathode electrodes (134).].
Allowable Subject Matter
Claims 7-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the references cited in record disclose or suggest the display device of claim 4, further comprising: a write high voltage line, a write low voltage line, a write start clock line, a first write clock line, a second write clock line, a third write clock line, and a fourth write clock line connected to the first gate driver; a bias high voltage line, a bias low voltage line, and a bias start clock line connected to the second gate driver; an emission high voltage line, an emission low voltage line, and an
emission start clock line connected to the emission controller; and a common low voltage line, a first common clock line, and a second common clock line connected to the second gate driver and the emission controller, wherein the bias start clock line is connected to the second gate driver and the emission controller; and/or the display device of claim 11, wherein the write high voltage line, the
write low voltage line, the write start clock line, the first write clock line, the second write clock line, the third write clock line, and the fourth write clock line overlap the first gate driver, wherein the bias high voltage line, the bias low voltage line, the bias start clock line, and the second common clock line overlap the second gate driver, and wherein the emission high voltage line, the emission low voltage line, the common low voltage line, the emission start clock line, and the first common clock line overlap the emission controller.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Van N Chow whose telephone number is (571)272-7590. The examiner can normally be reached M-F 10-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Ke can be reached at 5712727776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VAN N CHOW/Primary Examiner, Art Unit 2627
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